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1// SPDX-License-Identifier: GPL-2.0+2 3/*4 * Copyright 2021 Pengutronix, Lucas Stach <kernel@pengutronix.de>5 */6 7#include <linux/bitfield.h>8#include <linux/device.h>9#include <linux/interconnect.h>10#include <linux/module.h>11#include <linux/of.h>12#include <linux/of_platform.h>13#include <linux/platform_device.h>14#include <linux/pm_domain.h>15#include <linux/pm_runtime.h>16#include <linux/regmap.h>17#include <linux/clk.h>18 19#include <dt-bindings/power/imx8mm-power.h>20#include <dt-bindings/power/imx8mn-power.h>21#include <dt-bindings/power/imx8mp-power.h>22#include <dt-bindings/power/imx8mq-power.h>23 24#define BLK_SFT_RSTN 0x025#define BLK_CLK_EN 0x426#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */27 28struct imx8m_blk_ctrl_domain;29 30struct imx8m_blk_ctrl {31 struct device *dev;32 struct notifier_block power_nb;33 struct device *bus_power_dev;34 struct regmap *regmap;35 struct imx8m_blk_ctrl_domain *domains;36 struct genpd_onecell_data onecell_data;37};38 39struct imx8m_blk_ctrl_domain_data {40 const char *name;41 const char * const *clk_names;42 const char * const *path_names;43 const char *gpc_name;44 int num_clks;45 int num_paths;46 u32 rst_mask;47 u32 clk_mask;48 49 /*50 * i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register51 * which is used to control the reset for the MIPI Phy.52 * Since it's only present in certain circumstances,53 * an if-statement should be used before setting and clearing this54 * register.55 */56 u32 mipi_phy_rst_mask;57};58 59#define DOMAIN_MAX_CLKS 460#define DOMAIN_MAX_PATHS 461 62struct imx8m_blk_ctrl_domain {63 struct generic_pm_domain genpd;64 const struct imx8m_blk_ctrl_domain_data *data;65 struct clk_bulk_data clks[DOMAIN_MAX_CLKS];66 struct icc_bulk_data paths[DOMAIN_MAX_PATHS];67 struct device *power_dev;68 struct imx8m_blk_ctrl *bc;69 int num_paths;70};71 72struct imx8m_blk_ctrl_data {73 int max_reg;74 notifier_fn_t power_notifier_fn;75 const struct imx8m_blk_ctrl_domain_data *domains;76 int num_domains;77};78 79static inline struct imx8m_blk_ctrl_domain *80to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd)81{82 return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd);83}84 85static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd)86{87 struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);88 const struct imx8m_blk_ctrl_domain_data *data = domain->data;89 struct imx8m_blk_ctrl *bc = domain->bc;90 int ret;91 92 /* make sure bus domain is awake */93 ret = pm_runtime_get_sync(bc->bus_power_dev);94 if (ret < 0) {95 pm_runtime_put_noidle(bc->bus_power_dev);96 dev_err(bc->dev, "failed to power up bus domain\n");97 return ret;98 }99 100 /* put devices into reset */101 regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);102 if (data->mipi_phy_rst_mask)103 regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);104 105 /* enable upstream and blk-ctrl clocks to allow reset to propagate */106 ret = clk_bulk_prepare_enable(data->num_clks, domain->clks);107 if (ret) {108 dev_err(bc->dev, "failed to enable clocks\n");109 goto bus_put;110 }111 regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);112 113 /* power up upstream GPC domain */114 ret = pm_runtime_get_sync(domain->power_dev);115 if (ret < 0) {116 dev_err(bc->dev, "failed to power up peripheral domain\n");117 goto clk_disable;118 }119 120 /* wait for reset to propagate */121 udelay(5);122 123 /* release reset */124 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);125 if (data->mipi_phy_rst_mask)126 regmap_set_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);127 128 ret = icc_bulk_set_bw(domain->num_paths, domain->paths);129 if (ret)130 dev_err(bc->dev, "failed to set icc bw\n");131 132 /* disable upstream clocks */133 clk_bulk_disable_unprepare(data->num_clks, domain->clks);134 135 return 0;136 137clk_disable:138 clk_bulk_disable_unprepare(data->num_clks, domain->clks);139bus_put:140 pm_runtime_put(bc->bus_power_dev);141 142 return ret;143}144 145static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd)146{147 struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd);148 const struct imx8m_blk_ctrl_domain_data *data = domain->data;149 struct imx8m_blk_ctrl *bc = domain->bc;150 151 /* put devices into reset and disable clocks */152 if (data->mipi_phy_rst_mask)153 regmap_clear_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask);154 155 regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask);156 regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask);157 158 /* power down upstream GPC domain */159 pm_runtime_put(domain->power_dev);160 161 /* allow bus domain to suspend */162 pm_runtime_put(bc->bus_power_dev);163 164 return 0;165}166 167static struct lock_class_key blk_ctrl_genpd_lock_class;168 169static int imx8m_blk_ctrl_probe(struct platform_device *pdev)170{171 const struct imx8m_blk_ctrl_data *bc_data;172 struct device *dev = &pdev->dev;173 struct imx8m_blk_ctrl *bc;174 void __iomem *base;175 int i, ret;176 177 struct regmap_config regmap_config = {178 .reg_bits = 32,179 .val_bits = 32,180 .reg_stride = 4,181 };182 183 bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);184 if (!bc)185 return -ENOMEM;186 187 bc->dev = dev;188 189 bc_data = of_device_get_match_data(dev);190 191 base = devm_platform_ioremap_resource(pdev, 0);192 if (IS_ERR(base))193 return PTR_ERR(base);194 195 regmap_config.max_register = bc_data->max_reg;196 bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config);197 if (IS_ERR(bc->regmap))198 return dev_err_probe(dev, PTR_ERR(bc->regmap),199 "failed to init regmap\n");200 201 bc->domains = devm_kcalloc(dev, bc_data->num_domains,202 sizeof(struct imx8m_blk_ctrl_domain),203 GFP_KERNEL);204 if (!bc->domains)205 return -ENOMEM;206 207 bc->onecell_data.num_domains = bc_data->num_domains;208 bc->onecell_data.domains =209 devm_kcalloc(dev, bc_data->num_domains,210 sizeof(struct generic_pm_domain *), GFP_KERNEL);211 if (!bc->onecell_data.domains)212 return -ENOMEM;213 214 bc->bus_power_dev = dev_pm_domain_attach_by_name(dev, "bus");215 if (IS_ERR(bc->bus_power_dev)) {216 if (PTR_ERR(bc->bus_power_dev) == -ENODEV)217 return dev_err_probe(dev, -EPROBE_DEFER,218 "failed to attach power domain \"bus\"\n");219 else220 return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),221 "failed to attach power domain \"bus\"\n");222 }223 224 for (i = 0; i < bc_data->num_domains; i++) {225 const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i];226 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];227 int j;228 229 domain->data = data;230 domain->num_paths = data->num_paths;231 232 for (j = 0; j < data->num_clks; j++)233 domain->clks[j].id = data->clk_names[j];234 235 for (j = 0; j < data->num_paths; j++) {236 domain->paths[j].name = data->path_names[j];237 /* Fake value for now, just let ICC could configure NoC mode/priority */238 domain->paths[j].avg_bw = 1;239 domain->paths[j].peak_bw = 1;240 }241 242 ret = devm_of_icc_bulk_get(dev, data->num_paths, domain->paths);243 if (ret) {244 if (ret != -EPROBE_DEFER) {245 dev_warn_once(dev, "Could not get interconnect paths, NoC will stay unconfigured!\n");246 domain->num_paths = 0;247 } else {248 dev_err_probe(dev, ret, "failed to get noc entries\n");249 goto cleanup_pds;250 }251 }252 253 ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks);254 if (ret) {255 dev_err_probe(dev, ret, "failed to get clock\n");256 goto cleanup_pds;257 }258 259 domain->power_dev =260 dev_pm_domain_attach_by_name(dev, data->gpc_name);261 if (IS_ERR_OR_NULL(domain->power_dev)) {262 if (!domain->power_dev)263 ret = -ENODEV;264 else265 ret = PTR_ERR(domain->power_dev);266 dev_err_probe(dev, ret,267 "failed to attach power domain \"%s\"\n",268 data->gpc_name);269 goto cleanup_pds;270 }271 272 domain->genpd.name = data->name;273 domain->genpd.power_on = imx8m_blk_ctrl_power_on;274 domain->genpd.power_off = imx8m_blk_ctrl_power_off;275 domain->bc = bc;276 277 ret = pm_genpd_init(&domain->genpd, NULL, true);278 if (ret) {279 dev_err_probe(dev, ret,280 "failed to init power domain \"%s\"\n",281 data->gpc_name);282 dev_pm_domain_detach(domain->power_dev, true);283 goto cleanup_pds;284 }285 286 /*287 * We use runtime PM to trigger power on/off of the upstream GPC288 * domain, as a strict hierarchical parent/child power domain289 * setup doesn't allow us to meet the sequencing requirements.290 * This means we have nested locking of genpd locks, without the291 * nesting being visible at the genpd level, so we need a292 * separate lock class to make lockdep aware of the fact that293 * this are separate domain locks that can be nested without a294 * self-deadlock.295 */296 lockdep_set_class(&domain->genpd.mlock,297 &blk_ctrl_genpd_lock_class);298 299 bc->onecell_data.domains[i] = &domain->genpd;300 }301 302 ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);303 if (ret) {304 dev_err_probe(dev, ret, "failed to add power domain provider\n");305 goto cleanup_pds;306 }307 308 bc->power_nb.notifier_call = bc_data->power_notifier_fn;309 ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);310 if (ret) {311 dev_err_probe(dev, ret, "failed to add power notifier\n");312 goto cleanup_provider;313 }314 315 dev_set_drvdata(dev, bc);316 317 ret = devm_of_platform_populate(dev);318 if (ret)319 goto cleanup_provider;320 321 return 0;322 323cleanup_provider:324 of_genpd_del_provider(dev->of_node);325cleanup_pds:326 for (i--; i >= 0; i--) {327 pm_genpd_remove(&bc->domains[i].genpd);328 dev_pm_domain_detach(bc->domains[i].power_dev, true);329 }330 331 dev_pm_domain_detach(bc->bus_power_dev, true);332 333 return ret;334}335 336static void imx8m_blk_ctrl_remove(struct platform_device *pdev)337{338 struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);339 int i;340 341 of_genpd_del_provider(pdev->dev.of_node);342 343 for (i = 0; bc->onecell_data.num_domains; i++) {344 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];345 346 pm_genpd_remove(&domain->genpd);347 dev_pm_domain_detach(domain->power_dev, true);348 }349 350 dev_pm_genpd_remove_notifier(bc->bus_power_dev);351 352 dev_pm_domain_detach(bc->bus_power_dev, true);353}354 355#ifdef CONFIG_PM_SLEEP356static int imx8m_blk_ctrl_suspend(struct device *dev)357{358 struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);359 int ret, i;360 361 /*362 * This may look strange, but is done so the generic PM_SLEEP code363 * can power down our domains and more importantly power them up again364 * after resume, without tripping over our usage of runtime PM to365 * control the upstream GPC domains. Things happen in the right order366 * in the system suspend/resume paths due to the device parent/child367 * hierarchy.368 */369 ret = pm_runtime_get_sync(bc->bus_power_dev);370 if (ret < 0) {371 pm_runtime_put_noidle(bc->bus_power_dev);372 return ret;373 }374 375 for (i = 0; i < bc->onecell_data.num_domains; i++) {376 struct imx8m_blk_ctrl_domain *domain = &bc->domains[i];377 378 ret = pm_runtime_get_sync(domain->power_dev);379 if (ret < 0) {380 pm_runtime_put_noidle(domain->power_dev);381 goto out_fail;382 }383 }384 385 return 0;386 387out_fail:388 for (i--; i >= 0; i--)389 pm_runtime_put(bc->domains[i].power_dev);390 391 pm_runtime_put(bc->bus_power_dev);392 393 return ret;394}395 396static int imx8m_blk_ctrl_resume(struct device *dev)397{398 struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev);399 int i;400 401 for (i = 0; i < bc->onecell_data.num_domains; i++)402 pm_runtime_put(bc->domains[i].power_dev);403 404 pm_runtime_put(bc->bus_power_dev);405 406 return 0;407}408#endif409 410static const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = {411 SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend, imx8m_blk_ctrl_resume)412};413 414static int imx8mm_vpu_power_notifier(struct notifier_block *nb,415 unsigned long action, void *data)416{417 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,418 power_nb);419 420 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)421 return NOTIFY_OK;422 423 /*424 * The ADB in the VPUMIX domain has no separate reset and clock425 * enable bits, but is ungated together with the VPU clocks. To426 * allow the handshake with the GPC to progress we put the VPUs427 * in reset and ungate the clocks.428 */429 regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1) | BIT(2));430 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1) | BIT(2));431 432 if (action == GENPD_NOTIFY_ON) {433 /*434 * On power up we have no software backchannel to the GPC to435 * wait for the ADB handshake to happen, so we just delay for a436 * bit. On power down the GPC driver waits for the handshake.437 */438 udelay(5);439 440 /* set "fuse" bits to enable the VPUs */441 regmap_set_bits(bc->regmap, 0x8, 0xffffffff);442 regmap_set_bits(bc->regmap, 0xc, 0xffffffff);443 regmap_set_bits(bc->regmap, 0x10, 0xffffffff);444 regmap_set_bits(bc->regmap, 0x14, 0xffffffff);445 }446 447 return NOTIFY_OK;448}449 450static const struct imx8m_blk_ctrl_domain_data imx8mm_vpu_blk_ctl_domain_data[] = {451 [IMX8MM_VPUBLK_PD_G1] = {452 .name = "vpublk-g1",453 .clk_names = (const char *[]){ "g1", },454 .num_clks = 1,455 .gpc_name = "g1",456 .rst_mask = BIT(1),457 .clk_mask = BIT(1),458 },459 [IMX8MM_VPUBLK_PD_G2] = {460 .name = "vpublk-g2",461 .clk_names = (const char *[]){ "g2", },462 .num_clks = 1,463 .gpc_name = "g2",464 .rst_mask = BIT(0),465 .clk_mask = BIT(0),466 },467 [IMX8MM_VPUBLK_PD_H1] = {468 .name = "vpublk-h1",469 .clk_names = (const char *[]){ "h1", },470 .num_clks = 1,471 .gpc_name = "h1",472 .rst_mask = BIT(2),473 .clk_mask = BIT(2),474 },475};476 477static const struct imx8m_blk_ctrl_data imx8mm_vpu_blk_ctl_dev_data = {478 .max_reg = 0x18,479 .power_notifier_fn = imx8mm_vpu_power_notifier,480 .domains = imx8mm_vpu_blk_ctl_domain_data,481 .num_domains = ARRAY_SIZE(imx8mm_vpu_blk_ctl_domain_data),482};483 484static const struct imx8m_blk_ctrl_domain_data imx8mp_vpu_blk_ctl_domain_data[] = {485 [IMX8MP_VPUBLK_PD_G1] = {486 .name = "vpublk-g1",487 .clk_names = (const char *[]){ "g1", },488 .num_clks = 1,489 .gpc_name = "g1",490 .rst_mask = BIT(1),491 .clk_mask = BIT(1),492 .path_names = (const char *[]){"g1"},493 .num_paths = 1,494 },495 [IMX8MP_VPUBLK_PD_G2] = {496 .name = "vpublk-g2",497 .clk_names = (const char *[]){ "g2", },498 .num_clks = 1,499 .gpc_name = "g2",500 .rst_mask = BIT(0),501 .clk_mask = BIT(0),502 .path_names = (const char *[]){"g2"},503 .num_paths = 1,504 },505 [IMX8MP_VPUBLK_PD_VC8000E] = {506 .name = "vpublk-vc8000e",507 .clk_names = (const char *[]){ "vc8000e", },508 .num_clks = 1,509 .gpc_name = "vc8000e",510 .rst_mask = BIT(2),511 .clk_mask = BIT(2),512 .path_names = (const char *[]){"vc8000e"},513 .num_paths = 1,514 },515};516 517static const struct imx8m_blk_ctrl_data imx8mp_vpu_blk_ctl_dev_data = {518 .max_reg = 0x18,519 .power_notifier_fn = imx8mm_vpu_power_notifier,520 .domains = imx8mp_vpu_blk_ctl_domain_data,521 .num_domains = ARRAY_SIZE(imx8mp_vpu_blk_ctl_domain_data),522};523 524static int imx8mm_disp_power_notifier(struct notifier_block *nb,525 unsigned long action, void *data)526{527 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,528 power_nb);529 530 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)531 return NOTIFY_OK;532 533 /* Enable bus clock and deassert bus reset */534 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12));535 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6));536 537 /*538 * On power up we have no software backchannel to the GPC to539 * wait for the ADB handshake to happen, so we just delay for a540 * bit. On power down the GPC driver waits for the handshake.541 */542 if (action == GENPD_NOTIFY_ON)543 udelay(5);544 545 546 return NOTIFY_OK;547}548 549static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] = {550 [IMX8MM_DISPBLK_PD_CSI_BRIDGE] = {551 .name = "dispblk-csi-bridge",552 .clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb",553 "csi-bridge-core", },554 .num_clks = 3,555 .gpc_name = "csi-bridge",556 .rst_mask = BIT(0) | BIT(1) | BIT(2),557 .clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),558 },559 [IMX8MM_DISPBLK_PD_LCDIF] = {560 .name = "dispblk-lcdif",561 .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },562 .num_clks = 3,563 .gpc_name = "lcdif",564 .clk_mask = BIT(6) | BIT(7),565 },566 [IMX8MM_DISPBLK_PD_MIPI_DSI] = {567 .name = "dispblk-mipi-dsi",568 .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },569 .num_clks = 2,570 .gpc_name = "mipi-dsi",571 .rst_mask = BIT(5),572 .clk_mask = BIT(8) | BIT(9),573 .mipi_phy_rst_mask = BIT(17),574 },575 [IMX8MM_DISPBLK_PD_MIPI_CSI] = {576 .name = "dispblk-mipi-csi",577 .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },578 .num_clks = 2,579 .gpc_name = "mipi-csi",580 .rst_mask = BIT(3) | BIT(4),581 .clk_mask = BIT(10) | BIT(11),582 .mipi_phy_rst_mask = BIT(16),583 },584};585 586static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = {587 .max_reg = 0x2c,588 .power_notifier_fn = imx8mm_disp_power_notifier,589 .domains = imx8mm_disp_blk_ctl_domain_data,590 .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data),591};592 593 594static int imx8mn_disp_power_notifier(struct notifier_block *nb,595 unsigned long action, void *data)596{597 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,598 power_nb);599 600 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)601 return NOTIFY_OK;602 603 /* Enable bus clock and deassert bus reset */604 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));605 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));606 607 /*608 * On power up we have no software backchannel to the GPC to609 * wait for the ADB handshake to happen, so we just delay for a610 * bit. On power down the GPC driver waits for the handshake.611 */612 if (action == GENPD_NOTIFY_ON)613 udelay(5);614 615 616 return NOTIFY_OK;617}618 619static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = {620 [IMX8MN_DISPBLK_PD_MIPI_DSI] = {621 .name = "dispblk-mipi-dsi",622 .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },623 .num_clks = 2,624 .gpc_name = "mipi-dsi",625 .rst_mask = BIT(0) | BIT(1),626 .clk_mask = BIT(0) | BIT(1),627 .mipi_phy_rst_mask = BIT(17),628 },629 [IMX8MN_DISPBLK_PD_MIPI_CSI] = {630 .name = "dispblk-mipi-csi",631 .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },632 .num_clks = 2,633 .gpc_name = "mipi-csi",634 .rst_mask = BIT(2) | BIT(3),635 .clk_mask = BIT(2) | BIT(3),636 .mipi_phy_rst_mask = BIT(16),637 },638 [IMX8MN_DISPBLK_PD_LCDIF] = {639 .name = "dispblk-lcdif",640 .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },641 .num_clks = 3,642 .gpc_name = "lcdif",643 .rst_mask = BIT(4) | BIT(5),644 .clk_mask = BIT(4) | BIT(5),645 },646 [IMX8MN_DISPBLK_PD_ISI] = {647 .name = "dispblk-isi",648 .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root",649 "disp_apb_root"},650 .num_clks = 4,651 .gpc_name = "isi",652 .rst_mask = BIT(6) | BIT(7),653 .clk_mask = BIT(6) | BIT(7),654 },655};656 657static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {658 .max_reg = 0x84,659 .power_notifier_fn = imx8mn_disp_power_notifier,660 .domains = imx8mn_disp_blk_ctl_domain_data,661 .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),662};663 664#define LCDIF_ARCACHE_CTRL 0x4c665#define LCDIF_1_RD_HURRY GENMASK(15, 13)666#define LCDIF_0_RD_HURRY GENMASK(12, 10)667 668static int imx8mp_media_power_notifier(struct notifier_block *nb,669 unsigned long action, void *data)670{671 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,672 power_nb);673 674 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)675 return NOTIFY_OK;676 677 /* Enable bus clock and deassert bus reset */678 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));679 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));680 681 if (action == GENPD_NOTIFY_ON) {682 /*683 * On power up we have no software backchannel to the GPC to684 * wait for the ADB handshake to happen, so we just delay for a685 * bit. On power down the GPC driver waits for the handshake.686 */687 udelay(5);688 689 /*690 * Set panic read hurry level for both LCDIF interfaces to691 * maximum priority to minimize chances of display FIFO692 * underflow.693 */694 regmap_set_bits(bc->regmap, LCDIF_ARCACHE_CTRL,695 FIELD_PREP(LCDIF_1_RD_HURRY, 7) |696 FIELD_PREP(LCDIF_0_RD_HURRY, 7));697 }698 699 return NOTIFY_OK;700}701 702/*703 * From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1,704 * section 13.2.2, 13.2.3705 * isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks706 */707static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = {708 [IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = {709 .name = "mediablk-mipi-dsi-1",710 .clk_names = (const char *[]){ "apb", "phy", },711 .num_clks = 2,712 .gpc_name = "mipi-dsi1",713 .rst_mask = BIT(0) | BIT(1),714 .clk_mask = BIT(0) | BIT(1),715 .mipi_phy_rst_mask = BIT(17),716 },717 [IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = {718 .name = "mediablk-mipi-csi2-1",719 .clk_names = (const char *[]){ "apb", "cam1" },720 .num_clks = 2,721 .gpc_name = "mipi-csi1",722 .rst_mask = BIT(2) | BIT(3),723 .clk_mask = BIT(2) | BIT(3),724 .mipi_phy_rst_mask = BIT(16),725 },726 [IMX8MP_MEDIABLK_PD_LCDIF_1] = {727 .name = "mediablk-lcdif-1",728 .clk_names = (const char *[]){ "disp1", "apb", "axi", },729 .num_clks = 3,730 .gpc_name = "lcdif1",731 .rst_mask = BIT(4) | BIT(5) | BIT(23),732 .clk_mask = BIT(4) | BIT(5) | BIT(23),733 .path_names = (const char *[]){"lcdif-rd", "lcdif-wr"},734 .num_paths = 2,735 },736 [IMX8MP_MEDIABLK_PD_ISI] = {737 .name = "mediablk-isi",738 .clk_names = (const char *[]){ "axi", "apb" },739 .num_clks = 2,740 .gpc_name = "isi",741 .rst_mask = BIT(6) | BIT(7),742 .clk_mask = BIT(6) | BIT(7),743 .path_names = (const char *[]){"isi0", "isi1", "isi2"},744 .num_paths = 3,745 },746 [IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = {747 .name = "mediablk-mipi-csi2-2",748 .clk_names = (const char *[]){ "apb", "cam2" },749 .num_clks = 2,750 .gpc_name = "mipi-csi2",751 .rst_mask = BIT(9) | BIT(10),752 .clk_mask = BIT(9) | BIT(10),753 .mipi_phy_rst_mask = BIT(30),754 },755 [IMX8MP_MEDIABLK_PD_LCDIF_2] = {756 .name = "mediablk-lcdif-2",757 .clk_names = (const char *[]){ "disp2", "apb", "axi", },758 .num_clks = 3,759 .gpc_name = "lcdif2",760 .rst_mask = BIT(11) | BIT(12) | BIT(24),761 .clk_mask = BIT(11) | BIT(12) | BIT(24),762 .path_names = (const char *[]){"lcdif-rd", "lcdif-wr"},763 .num_paths = 2,764 },765 [IMX8MP_MEDIABLK_PD_ISP] = {766 .name = "mediablk-isp",767 .clk_names = (const char *[]){ "isp", "axi", "apb" },768 .num_clks = 3,769 .gpc_name = "isp",770 .rst_mask = BIT(16) | BIT(17) | BIT(18),771 .clk_mask = BIT(16) | BIT(17) | BIT(18),772 .path_names = (const char *[]){"isp0", "isp1"},773 .num_paths = 2,774 },775 [IMX8MP_MEDIABLK_PD_DWE] = {776 .name = "mediablk-dwe",777 .clk_names = (const char *[]){ "axi", "apb" },778 .num_clks = 2,779 .gpc_name = "dwe",780 .rst_mask = BIT(19) | BIT(20) | BIT(21),781 .clk_mask = BIT(19) | BIT(20) | BIT(21),782 .path_names = (const char *[]){"dwe"},783 .num_paths = 1,784 },785 [IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = {786 .name = "mediablk-mipi-dsi-2",787 .clk_names = (const char *[]){ "phy", },788 .num_clks = 1,789 .gpc_name = "mipi-dsi2",790 .rst_mask = BIT(22),791 .clk_mask = BIT(22),792 .mipi_phy_rst_mask = BIT(29),793 },794};795 796static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = {797 .max_reg = 0x138,798 .power_notifier_fn = imx8mp_media_power_notifier,799 .domains = imx8mp_media_blk_ctl_domain_data,800 .num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data),801};802 803static int imx8mq_vpu_power_notifier(struct notifier_block *nb,804 unsigned long action, void *data)805{806 struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,807 power_nb);808 809 if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)810 return NOTIFY_OK;811 812 /*813 * The ADB in the VPUMIX domain has no separate reset and clock814 * enable bits, but is ungated and reset together with the VPUs. The815 * reset and clock enable inputs to the ADB is a logical OR of the816 * VPU bits. In order to set the G2 fuse bits, the G2 clock must817 * also be enabled.818 */819 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1));820 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1));821 822 if (action == GENPD_NOTIFY_ON) {823 /*824 * On power up we have no software backchannel to the GPC to825 * wait for the ADB handshake to happen, so we just delay for a826 * bit. On power down the GPC driver waits for the handshake.827 */828 udelay(5);829 830 /* set "fuse" bits to enable the VPUs */831 regmap_set_bits(bc->regmap, 0x8, 0xffffffff);832 regmap_set_bits(bc->regmap, 0xc, 0xffffffff);833 regmap_set_bits(bc->regmap, 0x10, 0xffffffff);834 }835 836 return NOTIFY_OK;837}838 839static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = {840 [IMX8MQ_VPUBLK_PD_G1] = {841 .name = "vpublk-g1",842 .clk_names = (const char *[]){ "g1", },843 .num_clks = 1,844 .gpc_name = "g1",845 .rst_mask = BIT(1),846 .clk_mask = BIT(1),847 },848 [IMX8MQ_VPUBLK_PD_G2] = {849 .name = "vpublk-g2",850 .clk_names = (const char *[]){ "g2", },851 .num_clks = 1,852 .gpc_name = "g2",853 .rst_mask = BIT(0),854 .clk_mask = BIT(0),855 },856};857 858static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = {859 .max_reg = 0x14,860 .power_notifier_fn = imx8mq_vpu_power_notifier,861 .domains = imx8mq_vpu_blk_ctl_domain_data,862 .num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data),863};864 865static const struct of_device_id imx8m_blk_ctrl_of_match[] = {866 {867 .compatible = "fsl,imx8mm-vpu-blk-ctrl",868 .data = &imx8mm_vpu_blk_ctl_dev_data869 }, {870 .compatible = "fsl,imx8mm-disp-blk-ctrl",871 .data = &imx8mm_disp_blk_ctl_dev_data872 }, {873 .compatible = "fsl,imx8mn-disp-blk-ctrl",874 .data = &imx8mn_disp_blk_ctl_dev_data875 }, {876 .compatible = "fsl,imx8mp-media-blk-ctrl",877 .data = &imx8mp_media_blk_ctl_dev_data878 }, {879 .compatible = "fsl,imx8mq-vpu-blk-ctrl",880 .data = &imx8mq_vpu_blk_ctl_dev_data881 }, {882 .compatible = "fsl,imx8mp-vpu-blk-ctrl",883 .data = &imx8mp_vpu_blk_ctl_dev_data884 }, {885 /* Sentinel */886 }887};888MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);889 890static struct platform_driver imx8m_blk_ctrl_driver = {891 .probe = imx8m_blk_ctrl_probe,892 .remove_new = imx8m_blk_ctrl_remove,893 .driver = {894 .name = "imx8m-blk-ctrl",895 .pm = &imx8m_blk_ctrl_pm_ops,896 .of_match_table = imx8m_blk_ctrl_of_match,897 },898};899module_platform_driver(imx8m_blk_ctrl_driver);900MODULE_LICENSE("GPL");901