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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (c) 2022 MediaTek Inc.4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>5 */6 7#ifndef __SOC_MEDIATEK_MT8186_PM_DOMAINS_H8#define __SOC_MEDIATEK_MT8186_PM_DOMAINS_H9 10#include "mtk-pm-domains.h"11#include <dt-bindings/power/mt8186-power.h>12 13/*14 * MT8186 power domain support15 */16 17static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {18 [MT8186_POWER_DOMAIN_MFG0] = {19 .name = "mfg0",20 .sta_mask = BIT(2),21 .ctl_offs = 0x308,22 .pwr_sta_offs = 0x16C,23 .pwr_sta2nd_offs = 0x170,24 .sram_pdn_bits = BIT(8),25 .sram_pdn_ack_bits = BIT(12),26 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,27 },28 [MT8186_POWER_DOMAIN_MFG1] = {29 .name = "mfg1",30 .sta_mask = BIT(3),31 .ctl_offs = 0x30c,32 .pwr_sta_offs = 0x16C,33 .pwr_sta2nd_offs = 0x170,34 .sram_pdn_bits = BIT(8),35 .sram_pdn_ack_bits = BIT(12),36 .bp_cfg = {37 BUS_PROT_WR_IGN(INFRA,38 MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,39 MT8186_TOP_AXI_PROT_EN_1_SET,40 MT8186_TOP_AXI_PROT_EN_1_CLR,41 MT8186_TOP_AXI_PROT_EN_1_STA),42 BUS_PROT_WR_IGN(INFRA,43 MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,44 MT8186_TOP_AXI_PROT_EN_SET,45 MT8186_TOP_AXI_PROT_EN_CLR,46 MT8186_TOP_AXI_PROT_EN_STA),47 BUS_PROT_WR_IGN(INFRA,48 MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,49 MT8186_TOP_AXI_PROT_EN_SET,50 MT8186_TOP_AXI_PROT_EN_CLR,51 MT8186_TOP_AXI_PROT_EN_STA),52 BUS_PROT_WR_IGN(INFRA,53 MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,54 MT8186_TOP_AXI_PROT_EN_1_SET,55 MT8186_TOP_AXI_PROT_EN_1_CLR,56 MT8186_TOP_AXI_PROT_EN_1_STA),57 },58 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,59 },60 [MT8186_POWER_DOMAIN_MFG2] = {61 .name = "mfg2",62 .sta_mask = BIT(4),63 .ctl_offs = 0x310,64 .pwr_sta_offs = 0x16C,65 .pwr_sta2nd_offs = 0x170,66 .sram_pdn_bits = BIT(8),67 .sram_pdn_ack_bits = BIT(12),68 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,69 },70 [MT8186_POWER_DOMAIN_MFG3] = {71 .name = "mfg3",72 .sta_mask = BIT(5),73 .ctl_offs = 0x314,74 .pwr_sta_offs = 0x16C,75 .pwr_sta2nd_offs = 0x170,76 .sram_pdn_bits = BIT(8),77 .sram_pdn_ack_bits = BIT(12),78 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,79 },80 [MT8186_POWER_DOMAIN_SSUSB] = {81 .name = "ssusb",82 .sta_mask = BIT(20),83 .ctl_offs = 0x9F0,84 .pwr_sta_offs = 0x16C,85 .pwr_sta2nd_offs = 0x170,86 .sram_pdn_bits = BIT(8),87 .sram_pdn_ack_bits = BIT(12),88 .caps = MTK_SCPD_ACTIVE_WAKEUP,89 },90 [MT8186_POWER_DOMAIN_SSUSB_P1] = {91 .name = "ssusb_p1",92 .sta_mask = BIT(19),93 .ctl_offs = 0x9F4,94 .pwr_sta_offs = 0x16C,95 .pwr_sta2nd_offs = 0x170,96 .sram_pdn_bits = BIT(8),97 .sram_pdn_ack_bits = BIT(12),98 .caps = MTK_SCPD_ACTIVE_WAKEUP,99 },100 [MT8186_POWER_DOMAIN_DIS] = {101 .name = "dis",102 .sta_mask = BIT(21),103 .ctl_offs = 0x354,104 .pwr_sta_offs = 0x16C,105 .pwr_sta2nd_offs = 0x170,106 .sram_pdn_bits = BIT(8),107 .sram_pdn_ack_bits = BIT(12),108 .bp_cfg = {109 BUS_PROT_WR_IGN(INFRA,110 MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,111 MT8186_TOP_AXI_PROT_EN_1_SET,112 MT8186_TOP_AXI_PROT_EN_1_CLR,113 MT8186_TOP_AXI_PROT_EN_1_STA),114 BUS_PROT_WR_IGN(INFRA,115 MT8186_TOP_AXI_PROT_EN_DIS_STEP2,116 MT8186_TOP_AXI_PROT_EN_SET,117 MT8186_TOP_AXI_PROT_EN_CLR,118 MT8186_TOP_AXI_PROT_EN_STA),119 },120 },121 [MT8186_POWER_DOMAIN_IMG] = {122 .name = "img",123 .sta_mask = BIT(13),124 .ctl_offs = 0x334,125 .pwr_sta_offs = 0x16C,126 .pwr_sta2nd_offs = 0x170,127 .sram_pdn_bits = BIT(8),128 .sram_pdn_ack_bits = BIT(12),129 .bp_cfg = {130 BUS_PROT_WR_IGN(INFRA,131 MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,132 MT8186_TOP_AXI_PROT_EN_1_SET,133 MT8186_TOP_AXI_PROT_EN_1_CLR,134 MT8186_TOP_AXI_PROT_EN_1_STA),135 BUS_PROT_WR_IGN(INFRA,136 MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,137 MT8186_TOP_AXI_PROT_EN_1_SET,138 MT8186_TOP_AXI_PROT_EN_1_CLR,139 MT8186_TOP_AXI_PROT_EN_1_STA),140 },141 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,142 },143 [MT8186_POWER_DOMAIN_IMG2] = {144 .name = "img2",145 .sta_mask = BIT(14),146 .ctl_offs = 0x338,147 .pwr_sta_offs = 0x16C,148 .pwr_sta2nd_offs = 0x170,149 .sram_pdn_bits = BIT(8),150 .sram_pdn_ack_bits = BIT(12),151 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,152 },153 [MT8186_POWER_DOMAIN_IPE] = {154 .name = "ipe",155 .sta_mask = BIT(15),156 .ctl_offs = 0x33C,157 .pwr_sta_offs = 0x16C,158 .pwr_sta2nd_offs = 0x170,159 .sram_pdn_bits = BIT(8),160 .sram_pdn_ack_bits = BIT(12),161 .bp_cfg = {162 BUS_PROT_WR_IGN(INFRA,163 MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,164 MT8186_TOP_AXI_PROT_EN_1_SET,165 MT8186_TOP_AXI_PROT_EN_1_CLR,166 MT8186_TOP_AXI_PROT_EN_1_STA),167 BUS_PROT_WR_IGN(INFRA,168 MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,169 MT8186_TOP_AXI_PROT_EN_1_SET,170 MT8186_TOP_AXI_PROT_EN_1_CLR,171 MT8186_TOP_AXI_PROT_EN_1_STA),172 },173 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,174 },175 [MT8186_POWER_DOMAIN_CAM] = {176 .name = "cam",177 .sta_mask = BIT(23),178 .ctl_offs = 0x35C,179 .pwr_sta_offs = 0x16C,180 .pwr_sta2nd_offs = 0x170,181 .sram_pdn_bits = BIT(8),182 .sram_pdn_ack_bits = BIT(12),183 .bp_cfg = {184 BUS_PROT_WR_IGN(INFRA,185 MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,186 MT8186_TOP_AXI_PROT_EN_1_SET,187 MT8186_TOP_AXI_PROT_EN_1_CLR,188 MT8186_TOP_AXI_PROT_EN_1_STA),189 BUS_PROT_WR_IGN(INFRA,190 MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,191 MT8186_TOP_AXI_PROT_EN_1_SET,192 MT8186_TOP_AXI_PROT_EN_1_CLR,193 MT8186_TOP_AXI_PROT_EN_1_STA),194 },195 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,196 },197 [MT8186_POWER_DOMAIN_CAM_RAWA] = {198 .name = "cam_rawa",199 .sta_mask = BIT(24),200 .ctl_offs = 0x360,201 .pwr_sta_offs = 0x16C,202 .pwr_sta2nd_offs = 0x170,203 .sram_pdn_bits = BIT(8),204 .sram_pdn_ack_bits = BIT(12),205 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,206 },207 [MT8186_POWER_DOMAIN_CAM_RAWB] = {208 .name = "cam_rawb",209 .sta_mask = BIT(25),210 .ctl_offs = 0x364,211 .pwr_sta_offs = 0x16C,212 .pwr_sta2nd_offs = 0x170,213 .sram_pdn_bits = BIT(8),214 .sram_pdn_ack_bits = BIT(12),215 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,216 },217 [MT8186_POWER_DOMAIN_VENC] = {218 .name = "venc",219 .sta_mask = BIT(18),220 .ctl_offs = 0x348,221 .pwr_sta_offs = 0x16C,222 .pwr_sta2nd_offs = 0x170,223 .sram_pdn_bits = BIT(8),224 .sram_pdn_ack_bits = BIT(12),225 .bp_cfg = {226 BUS_PROT_WR_IGN(INFRA,227 MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,228 MT8186_TOP_AXI_PROT_EN_1_SET,229 MT8186_TOP_AXI_PROT_EN_1_CLR,230 MT8186_TOP_AXI_PROT_EN_1_STA),231 BUS_PROT_WR_IGN(INFRA,232 MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,233 MT8186_TOP_AXI_PROT_EN_1_SET,234 MT8186_TOP_AXI_PROT_EN_1_CLR,235 MT8186_TOP_AXI_PROT_EN_1_STA),236 },237 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,238 },239 [MT8186_POWER_DOMAIN_VDEC] = {240 .name = "vdec",241 .sta_mask = BIT(16),242 .ctl_offs = 0x340,243 .pwr_sta_offs = 0x16C,244 .pwr_sta2nd_offs = 0x170,245 .sram_pdn_bits = BIT(8),246 .sram_pdn_ack_bits = BIT(12),247 .bp_cfg = {248 BUS_PROT_WR_IGN(INFRA,249 MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,250 MT8186_TOP_AXI_PROT_EN_1_SET,251 MT8186_TOP_AXI_PROT_EN_1_CLR,252 MT8186_TOP_AXI_PROT_EN_1_STA),253 BUS_PROT_WR_IGN(INFRA,254 MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,255 MT8186_TOP_AXI_PROT_EN_1_SET,256 MT8186_TOP_AXI_PROT_EN_1_CLR,257 MT8186_TOP_AXI_PROT_EN_1_STA),258 },259 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,260 },261 [MT8186_POWER_DOMAIN_WPE] = {262 .name = "wpe",263 .sta_mask = BIT(0),264 .ctl_offs = 0x3F8,265 .pwr_sta_offs = 0x16C,266 .pwr_sta2nd_offs = 0x170,267 .sram_pdn_bits = BIT(8),268 .sram_pdn_ack_bits = BIT(12),269 .bp_cfg = {270 BUS_PROT_WR_IGN(INFRA,271 MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,272 MT8186_TOP_AXI_PROT_EN_2_SET,273 MT8186_TOP_AXI_PROT_EN_2_CLR,274 MT8186_TOP_AXI_PROT_EN_2_STA),275 BUS_PROT_WR_IGN(INFRA,276 MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,277 MT8186_TOP_AXI_PROT_EN_2_SET,278 MT8186_TOP_AXI_PROT_EN_2_CLR,279 MT8186_TOP_AXI_PROT_EN_2_STA),280 },281 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,282 },283 [MT8186_POWER_DOMAIN_CONN_ON] = {284 .name = "conn_on",285 .sta_mask = BIT(1),286 .ctl_offs = 0x304,287 .pwr_sta_offs = 0x16C,288 .pwr_sta2nd_offs = 0x170,289 .bp_cfg = {290 BUS_PROT_WR_IGN(INFRA,291 MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,292 MT8186_TOP_AXI_PROT_EN_1_SET,293 MT8186_TOP_AXI_PROT_EN_1_CLR,294 MT8186_TOP_AXI_PROT_EN_1_STA),295 BUS_PROT_WR_IGN(INFRA,296 MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,297 MT8186_TOP_AXI_PROT_EN_SET,298 MT8186_TOP_AXI_PROT_EN_CLR,299 MT8186_TOP_AXI_PROT_EN_STA),300 BUS_PROT_WR_IGN(INFRA,301 MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,302 MT8186_TOP_AXI_PROT_EN_SET,303 MT8186_TOP_AXI_PROT_EN_CLR,304 MT8186_TOP_AXI_PROT_EN_STA),305 BUS_PROT_WR_IGN(INFRA,306 MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,307 MT8186_TOP_AXI_PROT_EN_SET,308 MT8186_TOP_AXI_PROT_EN_CLR,309 MT8186_TOP_AXI_PROT_EN_STA),310 },311 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,312 },313 [MT8186_POWER_DOMAIN_CSIRX_TOP] = {314 .name = "csirx_top",315 .sta_mask = BIT(6),316 .ctl_offs = 0x318,317 .pwr_sta_offs = 0x16C,318 .pwr_sta2nd_offs = 0x170,319 .sram_pdn_bits = BIT(8),320 .sram_pdn_ack_bits = BIT(12),321 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,322 },323 [MT8186_POWER_DOMAIN_ADSP_AO] = {324 .name = "adsp_ao",325 .sta_mask = BIT(17),326 .ctl_offs = 0x9FC,327 .pwr_sta_offs = 0x16C,328 .pwr_sta2nd_offs = 0x170,329 },330 [MT8186_POWER_DOMAIN_ADSP_INFRA] = {331 .name = "adsp_infra",332 .sta_mask = BIT(10),333 .ctl_offs = 0x9F8,334 .pwr_sta_offs = 0x16C,335 .pwr_sta2nd_offs = 0x170,336 },337 [MT8186_POWER_DOMAIN_ADSP_TOP] = {338 .name = "adsp_top",339 .sta_mask = BIT(31),340 .ctl_offs = 0x3E4,341 .pwr_sta_offs = 0x16C,342 .pwr_sta2nd_offs = 0x170,343 .sram_pdn_bits = BIT(8),344 .sram_pdn_ack_bits = BIT(12),345 .bp_cfg = {346 BUS_PROT_WR_IGN(INFRA,347 MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,348 MT8186_TOP_AXI_PROT_EN_3_SET,349 MT8186_TOP_AXI_PROT_EN_3_CLR,350 MT8186_TOP_AXI_PROT_EN_3_STA),351 BUS_PROT_WR_IGN(INFRA,352 MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,353 MT8186_TOP_AXI_PROT_EN_3_SET,354 MT8186_TOP_AXI_PROT_EN_3_CLR,355 MT8186_TOP_AXI_PROT_EN_3_STA),356 },357 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,358 },359};360 361static const struct scpsys_soc_data mt8186_scpsys_data = {362 .domains_data = scpsys_domain_data_mt8186,363 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8186),364};365 366#endif /* __SOC_MEDIATEK_MT8186_PM_DOMAINS_H */367