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1/* SPDX-License-Identifier: GPL-2.0-only */2 3#ifndef __SOC_MEDIATEK_MT8365_PM_DOMAINS_H4#define __SOC_MEDIATEK_MT8365_PM_DOMAINS_H5 6#include "mtk-pm-domains.h"7#include <dt-bindings/power/mediatek,mt8365-power.h>8 9/*10 * MT8365 power domain support11 */12 13#define MT8365_BUS_PROT_INFRA_WR_TOPAXI(_mask) \14 BUS_PROT_WR(INFRA, _mask, \15 MT8365_INFRA_TOPAXI_PROTECTEN_SET, \16 MT8365_INFRA_TOPAXI_PROTECTEN_CLR, \17 MT8365_INFRA_TOPAXI_PROTECTEN_STA1)18 19#define MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(_mask) \20 BUS_PROT_WR(INFRA, _mask, \21 MT8365_INFRA_TOPAXI_PROTECTEN_1_SET, \22 MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR, \23 MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1)24 25#define MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(port) \26 BUS_PROT_WR(SMI, BIT(port), \27 MT8365_SMI_COMMON_CLAMP_EN_SET, \28 MT8365_SMI_COMMON_CLAMP_EN_CLR, \29 MT8365_SMI_COMMON_CLAMP_EN)30 31#define MT8365_BUS_PROT_WAY_EN(_set_mask, _set, _sta_mask, _sta) \32 _BUS_PROT(_set_mask, _set, _set, _sta_mask, _sta, \33 BUS_PROT_COMPONENT_INFRA | \34 BUS_PROT_STA_COMPONENT_INFRA_NAO | \35 BUS_PROT_INVERTED | \36 BUS_PROT_REG_UPDATE)37 38static const struct scpsys_domain_data scpsys_domain_data_mt8365[] = {39 [MT8365_POWER_DOMAIN_MM] = {40 .name = "mm",41 .sta_mask = PWR_STATUS_DISP,42 .ctl_offs = 0x30c,43 .pwr_sta_offs = 0x0180,44 .pwr_sta2nd_offs = 0x0184,45 .sram_pdn_bits = GENMASK(8, 8),46 .sram_pdn_ack_bits = GENMASK(12, 12),47 .bp_cfg = {48 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(49 MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_0 |50 MT8365_INFRA_TOPAXI_PROTECTEN_1_MM2INFRA_AXI_GALS_MST_1),51 MT8365_BUS_PROT_INFRA_WR_TOPAXI(52 MT8365_INFRA_TOPAXI_PROTECTEN_MM_M0 |53 MT8365_INFRA_TOPAXI_PROTECTEN_MDMCU_M1 |54 MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_0 |55 MT8365_INFRA_TOPAXI_PROTECTEN_MM2INFRA_AXI_GALS_SLV_1),56 MT8365_BUS_PROT_WAY_EN(57 MT8365_INFRA_TOPAXI_SI0_WAY_EN_MMAPB_S,58 MT8365_INFRA_TOPAXI_SI0_CTL,59 MT8365_INFRA_NAO_TOPAXI_SI0_CTRL_UPDATED,60 MT8365_INFRA_NAO_TOPAXI_SI0_STA),61 MT8365_BUS_PROT_WAY_EN(62 MT8365_INFRA_TOPAXI_SI2_WAY_EN_PERI_M1,63 MT8365_INFRA_TOPAXI_SI2_CTL,64 MT8365_INFRA_NAO_TOPAXI_SI2_CTRL_UPDATED,65 MT8365_INFRA_NAO_TOPAXI_SI2_STA),66 MT8365_BUS_PROT_INFRA_WR_TOPAXI(67 MT8365_INFRA_TOPAXI_PROTECTEN_MMAPB_S),68 },69 .caps = MTK_SCPD_STRICT_BUS_PROTECTION | MTK_SCPD_HAS_INFRA_NAO,70 },71 [MT8365_POWER_DOMAIN_VENC] = {72 .name = "venc",73 .sta_mask = PWR_STATUS_VENC,74 .ctl_offs = 0x0304,75 .pwr_sta_offs = 0x0180,76 .pwr_sta2nd_offs = 0x0184,77 .sram_pdn_bits = GENMASK(8, 8),78 .sram_pdn_ack_bits = GENMASK(12, 12),79 .bp_cfg = {80 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(1),81 },82 },83 [MT8365_POWER_DOMAIN_AUDIO] = {84 .name = "audio",85 .sta_mask = PWR_STATUS_AUDIO,86 .ctl_offs = 0x0314,87 .pwr_sta_offs = 0x0180,88 .pwr_sta2nd_offs = 0x0184,89 .sram_pdn_bits = GENMASK(12, 8),90 .sram_pdn_ack_bits = GENMASK(17, 13),91 .bp_cfg = {92 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(93 MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_MP1_L2C_AFIFO |94 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_AUDIO_M),95 },96 .caps = MTK_SCPD_ACTIVE_WAKEUP,97 },98 [MT8365_POWER_DOMAIN_CONN] = {99 .name = "conn",100 .sta_mask = PWR_STATUS_CONN,101 .ctl_offs = 0x032c,102 .pwr_sta_offs = 0x0180,103 .pwr_sta2nd_offs = 0x0184,104 .sram_pdn_bits = 0,105 .sram_pdn_ack_bits = 0,106 .bp_cfg = {107 MT8365_BUS_PROT_INFRA_WR_TOPAXI(108 MT8365_INFRA_TOPAXI_PROTECTEN_AP2CONN_AHB),109 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(110 MT8365_INFRA_TOPAXI_PROTECTEN_1_CONN2INFRA_AXI_GALS_MST),111 MT8365_BUS_PROT_INFRA_WR_TOPAXI(112 MT8365_INFRA_TOPAXI_PROTECTEN_CONN2INFRA_AHB),113 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(114 MT8365_INFRA_TOPAXI_PROTECTEN_1_INFRA2CONN_AHB_GALS_SLV),115 },116 .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_KEEP_DEFAULT_OFF,117 },118 [MT8365_POWER_DOMAIN_MFG] = {119 .name = "mfg",120 .sta_mask = PWR_STATUS_MFG,121 .ctl_offs = 0x0338,122 .pwr_sta_offs = 0x0180,123 .pwr_sta2nd_offs = 0x0184,124 .sram_pdn_bits = GENMASK(9, 8),125 .sram_pdn_ack_bits = GENMASK(13, 12),126 .bp_cfg = {127 MT8365_BUS_PROT_INFRA_WR_TOPAXI(BIT(25)),128 MT8365_BUS_PROT_INFRA_WR_TOPAXI(129 MT8365_INFRA_TOPAXI_PROTECTEN_MFG_M0 |130 MT8365_INFRA_TOPAXI_PROTECTEN_INFRA2MFG),131 },132 },133 [MT8365_POWER_DOMAIN_CAM] = {134 .name = "cam",135 .sta_mask = BIT(25),136 .ctl_offs = 0x0344,137 .pwr_sta_offs = 0x0180,138 .pwr_sta2nd_offs = 0x0184,139 .sram_pdn_bits = GENMASK(9, 8),140 .sram_pdn_ack_bits = GENMASK(13, 12),141 .bp_cfg = {142 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(143 MT8365_INFRA_TOPAXI_PROTECTEN_1_CAM2MM_AXI_GALS_MST),144 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(2),145 },146 },147 [MT8365_POWER_DOMAIN_VDEC] = {148 .name = "vdec",149 .sta_mask = BIT(31),150 .ctl_offs = 0x0370,151 .pwr_sta_offs = 0x0180,152 .pwr_sta2nd_offs = 0x0184,153 .sram_pdn_bits = GENMASK(8, 8),154 .sram_pdn_ack_bits = GENMASK(12, 12),155 .bp_cfg = {156 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(3),157 },158 },159 [MT8365_POWER_DOMAIN_APU] = {160 .name = "apu",161 .sta_mask = BIT(16),162 .ctl_offs = 0x0378,163 .pwr_sta_offs = 0x0180,164 .pwr_sta2nd_offs = 0x0184,165 .sram_pdn_bits = GENMASK(14, 8),166 .sram_pdn_ack_bits = GENMASK(21, 15),167 .bp_cfg = {168 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(169 MT8365_INFRA_TOPAXI_PROTECTEN_1_APU2AP |170 MT8365_INFRA_TOPAXI_PROTECTEN_1_APU_CBIP_GALS_MST),171 MT8365_BUS_PROT_SMI_WR_CLAMP_EN_PORT(4),172 },173 },174 [MT8365_POWER_DOMAIN_DSP] = {175 .name = "dsp",176 .sta_mask = BIT(17),177 .ctl_offs = 0x037C,178 .pwr_sta_offs = 0x0180,179 .pwr_sta2nd_offs = 0x0184,180 .sram_pdn_bits = GENMASK(11, 8),181 .sram_pdn_ack_bits = GENMASK(15, 12),182 .bp_cfg = {183 MT8365_BUS_PROT_INFRA_WR_TOPAXI_1(184 MT8365_INFRA_TOPAXI_PROTECTEN_1_PWRDNREQ_INFRA_GALS_ADB |185 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_M |186 MT8365_INFRA_TOPAXI_PROTECTEN_1_AUDIO_BUS_DSP_S),187 },188 .caps = MTK_SCPD_ACTIVE_WAKEUP,189 },190};191 192static const struct scpsys_soc_data mt8365_scpsys_data = {193 .domains_data = scpsys_domain_data_mt8365,194 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8365),195};196 197#endif /* __SOC_MEDIATEK_MT8365_PM_DOMAINS_H */198