123 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2 3#ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H4#define __SOC_MEDIATEK_MTK_PM_DOMAINS_H5 6#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)7#define MTK_SCPD_FWAIT_SRAM BIT(1)8#define MTK_SCPD_SRAM_ISO BIT(2)9#define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3)10#define MTK_SCPD_DOMAIN_SUPPLY BIT(4)11/* can't set MTK_SCPD_KEEP_DEFAULT_OFF at the same time */12#define MTK_SCPD_ALWAYS_ON BIT(5)13#define MTK_SCPD_EXT_BUCK_ISO BIT(6)14#define MTK_SCPD_HAS_INFRA_NAO BIT(7)15#define MTK_SCPD_STRICT_BUS_PROTECTION BIT(8)16#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))17 18#define SPM_VDE_PWR_CON 0x021019#define SPM_MFG_PWR_CON 0x021420#define SPM_VEN_PWR_CON 0x023021#define SPM_ISP_PWR_CON 0x023822#define SPM_DIS_PWR_CON 0x023c23#define SPM_CONN_PWR_CON 0x028024#define SPM_VEN2_PWR_CON 0x029825#define SPM_AUDIO_PWR_CON 0x029c26#define SPM_MFG_2D_PWR_CON 0x02c027#define SPM_MFG_ASYNC_PWR_CON 0x02c428#define SPM_USB_PWR_CON 0x02cc29 30#define SPM_PWR_STATUS 0x060c31#define SPM_PWR_STATUS_2ND 0x061032 33#define PWR_STATUS_CONN BIT(1)34#define PWR_STATUS_DISP BIT(3)35#define PWR_STATUS_MFG BIT(4)36#define PWR_STATUS_ISP BIT(5)37#define PWR_STATUS_VDEC BIT(7)38#define PWR_STATUS_VENC_LT BIT(20)39#define PWR_STATUS_VENC BIT(21)40#define PWR_STATUS_MFG_2D BIT(22)41#define PWR_STATUS_MFG_ASYNC BIT(23)42#define PWR_STATUS_AUDIO BIT(24)43#define PWR_STATUS_USB BIT(25)44 45#define SPM_MAX_BUS_PROT_DATA 646 47enum scpsys_bus_prot_flags {48 BUS_PROT_REG_UPDATE = BIT(1),49 BUS_PROT_IGNORE_CLR_ACK = BIT(2),50 BUS_PROT_INVERTED = BIT(3),51 BUS_PROT_COMPONENT_INFRA = BIT(4),52 BUS_PROT_COMPONENT_SMI = BIT(5),53 BUS_PROT_STA_COMPONENT_INFRA_NAO = BIT(6),54};55 56#define _BUS_PROT(_set_clr_mask, _set, _clr, _sta_mask, _sta, _flags) { \57 .bus_prot_set_clr_mask = (_set_clr_mask), \58 .bus_prot_set = _set, \59 .bus_prot_clr = _clr, \60 .bus_prot_sta_mask = (_sta_mask), \61 .bus_prot_sta = _sta, \62 .flags = _flags \63 }64 65#define BUS_PROT_WR(_hwip, _mask, _set, _clr, _sta) \66 _BUS_PROT(_mask, _set, _clr, _mask, _sta, BUS_PROT_COMPONENT_##_hwip)67 68#define BUS_PROT_WR_IGN(_hwip, _mask, _set, _clr, _sta) \69 _BUS_PROT(_mask, _set, _clr, _mask, _sta, \70 BUS_PROT_COMPONENT_##_hwip | BUS_PROT_IGNORE_CLR_ACK)71 72#define BUS_PROT_UPDATE(_hwip, _mask, _set, _clr, _sta) \73 _BUS_PROT(_mask, _set, _clr, _mask, _sta, \74 BUS_PROT_COMPONENT_##_hwip | BUS_PROT_REG_UPDATE)75 76#define BUS_PROT_INFRA_UPDATE_TOPAXI(_mask) \77 BUS_PROT_UPDATE(INFRA, _mask, \78 INFRA_TOPAXI_PROTECTEN, \79 INFRA_TOPAXI_PROTECTEN, \80 INFRA_TOPAXI_PROTECTSTA1)81 82struct scpsys_bus_prot_data {83 u32 bus_prot_set_clr_mask;84 u32 bus_prot_set;85 u32 bus_prot_clr;86 u32 bus_prot_sta_mask;87 u32 bus_prot_sta;88 u8 flags;89};90 91/**92 * struct scpsys_domain_data - scp domain data for power on/off flow93 * @name: The name of the power domain.94 * @sta_mask: The mask for power on/off status bit.95 * @ctl_offs: The offset for main power control register.96 * @sram_pdn_bits: The mask for sram power control bits.97 * @sram_pdn_ack_bits: The mask for sram power control acked bits.98 * @ext_buck_iso_offs: The offset for external buck isolation99 * @ext_buck_iso_mask: The mask for external buck isolation100 * @caps: The flag for active wake-up action.101 * @bp_cfg: bus protection configuration for any subsystem102 */103struct scpsys_domain_data {104 const char *name;105 u32 sta_mask;106 int ctl_offs;107 u32 sram_pdn_bits;108 u32 sram_pdn_ack_bits;109 int ext_buck_iso_offs;110 u32 ext_buck_iso_mask;111 u16 caps;112 const struct scpsys_bus_prot_data bp_cfg[SPM_MAX_BUS_PROT_DATA];113 int pwr_sta_offs;114 int pwr_sta2nd_offs;115};116 117struct scpsys_soc_data {118 const struct scpsys_domain_data *domains_data;119 int num_domains;120};121 122#endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */123