115 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * PTP hardware clock driver for the IDT 82P33XXX family of clocks.4 *5 * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.6 */7#ifndef PTP_IDT82P33_H8#define PTP_IDT82P33_H9 10#include <linux/ktime.h>11#include <linux/mfd/idt82p33_reg.h>12#include <linux/regmap.h>13 14#define FW_FILENAME "idt82p33xxx.bin"15#define MAX_PHC_PLL (2)16#define MAX_TRIG_CLK (3)17#define MAX_PER_OUT (11)18#define TOD_BYTE_COUNT (10)19#define DCO_MAX_PPB (92000)20#define MAX_MEASURMENT_COUNT (5)21#define SNAP_THRESHOLD_NS (10000)22#define IMMEDIATE_SNAP_THRESHOLD_NS (50000)23#define DDCO_THRESHOLD_NS (5)24#define IDT82P33_MAX_WRITE_COUNT (512)25 26#define PLLMASK_ADDR_HI 0xFF27#define PLLMASK_ADDR_LO 0xA528 29#define PLL0_OUTMASK_ADDR_HI 0xFF30#define PLL0_OUTMASK_ADDR_LO 0xB031 32#define PLL1_OUTMASK_ADDR_HI 0xFF33#define PLL1_OUTMASK_ADDR_LO 0xB234 35#define PLL2_OUTMASK_ADDR_HI 0xFF36#define PLL2_OUTMASK_ADDR_LO 0xB437 38#define PLL3_OUTMASK_ADDR_HI 0xFF39#define PLL3_OUTMASK_ADDR_LO 0xB640 41#define DEFAULT_PLL_MASK (0x01)42#define DEFAULT_OUTPUT_MASK_PLL0 (0xc0)43#define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL044 45/**46 * @brief Maximum absolute value for write phase offset in nanoseconds47 */48#define WRITE_PHASE_OFFSET_LIMIT (20000l)49 50/** @brief Phase offset resolution51 *52 * DPLL phase offset = 10^15 fs / ( System Clock * 2^13)53 * = 10^15 fs / ( 1638400000 * 2^23)54 * = 74.5058059692382 fs55 */56#define IDT_T0DPLL_PHASE_RESOL 7450657 58/* PTP Hardware Clock interface */59struct idt82p33_channel {60 struct ptp_clock_info caps;61 struct ptp_clock *ptp_clock;62 struct idt82p33 *idt82p33;63 enum pll_mode pll_mode;64 /* Workaround for TOD-to-output alignment issue */65 struct delayed_work adjtime_work;66 s32 current_freq;67 /* double dco mode */68 bool ddco;69 u8 output_mask;70 /* last input trigger for extts */71 u8 tod_trigger;72 bool discard_next_extts;73 u8 plln;74 /* remember last tod_sts for extts */75 u8 extts_tod_sts[TOD_BYTE_COUNT];76 u16 dpll_tod_cnfg;77 u16 dpll_tod_trigger;78 u16 dpll_tod_sts;79 u16 dpll_mode_cnfg;80 u16 dpll_freq_cnfg;81 u16 dpll_phase_cnfg;82 u16 dpll_sync_cnfg;83 u16 dpll_input_mode_cnfg;84};85 86struct idt82p33 {87 struct idt82p33_channel channel[MAX_PHC_PLL];88 struct device *dev;89 u8 pll_mask;90 /* Polls for external time stamps */91 u8 extts_mask;92 bool extts_single_shot;93 struct delayed_work extts_work;94 /* Remember the ptp channel to report extts */95 struct idt82p33_channel *event_channel[MAX_PHC_PLL];96 /* Mutex to protect operations from being interrupted */97 struct mutex *lock;98 struct regmap *regmap;99 struct device *mfd;100 /* Overhead calculation for adjtime */101 ktime_t start_time;102 int calculate_overhead_flag;103 s64 tod_write_overhead_ns;104};105 106/* firmware interface */107struct idt82p33_fwrc {108 u8 hiaddr;109 u8 loaddr;110 u8 value;111 u8 reserved;112} __packed;113 114#endif /* PTP_IDT82P33_H */115