4903 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/* Copyright (c) 2020 Facebook */3 4#include <linux/bits.h>5#include <linux/err.h>6#include <linux/kernel.h>7#include <linux/module.h>8#include <linux/debugfs.h>9#include <linux/init.h>10#include <linux/pci.h>11#include <linux/serial_8250.h>12#include <linux/clkdev.h>13#include <linux/clk-provider.h>14#include <linux/platform_device.h>15#include <linux/platform_data/i2c-xiic.h>16#include <linux/platform_data/i2c-ocores.h>17#include <linux/ptp_clock_kernel.h>18#include <linux/spi/spi.h>19#include <linux/spi/xilinx_spi.h>20#include <linux/spi/altera.h>21#include <net/devlink.h>22#include <linux/i2c.h>23#include <linux/mtd/mtd.h>24#include <linux/nvmem-consumer.h>25#include <linux/crc16.h>26#include <linux/dpll.h>27 28#define PCI_VENDOR_ID_FACEBOOK 0x1d9b29#define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x040030 31#define PCI_VENDOR_ID_CELESTICA 0x18d432#define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x100833 34#define PCI_VENDOR_ID_OROLIA 0x1ad735#define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa00036 37#define PCI_VENDOR_ID_ADVA 0xad5a38#define PCI_DEVICE_ID_ADVA_TIMECARD 0x040039 40static struct class timecard_class = {41 .name = "timecard",42};43 44struct ocp_reg {45 u32 ctrl;46 u32 status;47 u32 select;48 u32 version;49 u32 time_ns;50 u32 time_sec;51 u32 __pad0[2];52 u32 adjust_ns;53 u32 adjust_sec;54 u32 __pad1[2];55 u32 offset_ns;56 u32 offset_window_ns;57 u32 __pad2[2];58 u32 drift_ns;59 u32 drift_window_ns;60 u32 __pad3[6];61 u32 servo_offset_p;62 u32 servo_offset_i;63 u32 servo_drift_p;64 u32 servo_drift_i;65 u32 status_offset;66 u32 status_drift;67};68 69struct ptp_ocp_servo_conf {70 u32 servo_offset_p;71 u32 servo_offset_i;72 u32 servo_drift_p;73 u32 servo_drift_i;74};75 76#define OCP_CTRL_ENABLE BIT(0)77#define OCP_CTRL_ADJUST_TIME BIT(1)78#define OCP_CTRL_ADJUST_OFFSET BIT(2)79#define OCP_CTRL_ADJUST_DRIFT BIT(3)80#define OCP_CTRL_ADJUST_SERVO BIT(8)81#define OCP_CTRL_READ_TIME_REQ BIT(30)82#define OCP_CTRL_READ_TIME_DONE BIT(31)83 84#define OCP_STATUS_IN_SYNC BIT(0)85#define OCP_STATUS_IN_HOLDOVER BIT(1)86 87#define OCP_SELECT_CLK_NONE 088#define OCP_SELECT_CLK_REG 0xfe89 90struct tod_reg {91 u32 ctrl;92 u32 status;93 u32 uart_polarity;94 u32 version;95 u32 adj_sec;96 u32 __pad0[3];97 u32 uart_baud;98 u32 __pad1[3];99 u32 utc_status;100 u32 leap;101};102 103#define TOD_CTRL_PROTOCOL BIT(28)104#define TOD_CTRL_DISABLE_FMT_A BIT(17)105#define TOD_CTRL_DISABLE_FMT_B BIT(16)106#define TOD_CTRL_ENABLE BIT(0)107#define TOD_CTRL_GNSS_MASK GENMASK(3, 0)108#define TOD_CTRL_GNSS_SHIFT 24109 110#define TOD_STATUS_UTC_MASK GENMASK(7, 0)111#define TOD_STATUS_UTC_VALID BIT(8)112#define TOD_STATUS_LEAP_ANNOUNCE BIT(12)113#define TOD_STATUS_LEAP_VALID BIT(16)114 115struct ts_reg {116 u32 enable;117 u32 error;118 u32 polarity;119 u32 version;120 u32 __pad0[4];121 u32 cable_delay;122 u32 __pad1[3];123 u32 intr;124 u32 intr_mask;125 u32 event_count;126 u32 __pad2[1];127 u32 ts_count;128 u32 time_ns;129 u32 time_sec;130 u32 data_width;131 u32 data;132};133 134struct pps_reg {135 u32 ctrl;136 u32 status;137 u32 __pad0[6];138 u32 cable_delay;139};140 141#define PPS_STATUS_FILTER_ERR BIT(0)142#define PPS_STATUS_SUPERV_ERR BIT(1)143 144struct img_reg {145 u32 version;146};147 148struct gpio_reg {149 u32 gpio1;150 u32 __pad0;151 u32 gpio2;152 u32 __pad1;153};154 155struct irig_master_reg {156 u32 ctrl;157 u32 status;158 u32 __pad0;159 u32 version;160 u32 adj_sec;161 u32 mode_ctrl;162};163 164#define IRIG_M_CTRL_ENABLE BIT(0)165 166struct irig_slave_reg {167 u32 ctrl;168 u32 status;169 u32 __pad0;170 u32 version;171 u32 adj_sec;172 u32 mode_ctrl;173};174 175#define IRIG_S_CTRL_ENABLE BIT(0)176 177struct dcf_master_reg {178 u32 ctrl;179 u32 status;180 u32 __pad0;181 u32 version;182 u32 adj_sec;183};184 185#define DCF_M_CTRL_ENABLE BIT(0)186 187struct dcf_slave_reg {188 u32 ctrl;189 u32 status;190 u32 __pad0;191 u32 version;192 u32 adj_sec;193};194 195#define DCF_S_CTRL_ENABLE BIT(0)196 197struct signal_reg {198 u32 enable;199 u32 status;200 u32 polarity;201 u32 version;202 u32 __pad0[4];203 u32 cable_delay;204 u32 __pad1[3];205 u32 intr;206 u32 intr_mask;207 u32 __pad2[2];208 u32 start_ns;209 u32 start_sec;210 u32 pulse_ns;211 u32 pulse_sec;212 u32 period_ns;213 u32 period_sec;214 u32 repeat_count;215};216 217struct frequency_reg {218 u32 ctrl;219 u32 status;220};221 222struct board_config_reg {223 u32 mro50_serial_activate;224};225 226#define FREQ_STATUS_VALID BIT(31)227#define FREQ_STATUS_ERROR BIT(30)228#define FREQ_STATUS_OVERRUN BIT(29)229#define FREQ_STATUS_MASK GENMASK(23, 0)230 231struct ptp_ocp_flash_info {232 const char *name;233 int pci_offset;234 int data_size;235 void *data;236};237 238struct ptp_ocp_firmware_header {239 char magic[4];240 __be16 pci_vendor_id;241 __be16 pci_device_id;242 __be32 image_size;243 __be16 hw_revision;244 __be16 crc;245};246 247#define OCP_FIRMWARE_MAGIC_HEADER "OCPC"248 249struct ptp_ocp_i2c_info {250 const char *name;251 unsigned long fixed_rate;252 size_t data_size;253 void *data;254};255 256struct ptp_ocp_ext_info {257 int index;258 irqreturn_t (*irq_fcn)(int irq, void *priv);259 int (*enable)(void *priv, u32 req, bool enable);260};261 262struct ptp_ocp_ext_src {263 void __iomem *mem;264 struct ptp_ocp *bp;265 struct ptp_ocp_ext_info *info;266 int irq_vec;267};268 269enum ptp_ocp_sma_mode {270 SMA_MODE_IN,271 SMA_MODE_OUT,272};273 274static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {275 DPLL_PIN_FREQUENCY_1PPS,276 DPLL_PIN_FREQUENCY_10MHZ,277 DPLL_PIN_FREQUENCY_IRIG_B,278 DPLL_PIN_FREQUENCY_DCF77,279};280 281struct ptp_ocp_sma_connector {282 enum ptp_ocp_sma_mode mode;283 bool fixed_fcn;284 bool fixed_dir;285 bool disabled;286 u8 default_fcn;287 struct dpll_pin *dpll_pin;288 struct dpll_pin_properties dpll_prop;289};290 291struct ocp_attr_group {292 u64 cap;293 const struct attribute_group *group;294};295 296#define OCP_CAP_BASIC BIT(0)297#define OCP_CAP_SIGNAL BIT(1)298#define OCP_CAP_FREQ BIT(2)299 300struct ptp_ocp_signal {301 ktime_t period;302 ktime_t pulse;303 ktime_t phase;304 ktime_t start;305 int duty;306 bool polarity;307 bool running;308};309 310struct ptp_ocp_serial_port {311 int line;312 int baud;313};314 315#define OCP_BOARD_ID_LEN 13316#define OCP_SERIAL_LEN 6317#define OCP_SMA_NUM 4318 319enum {320 PORT_GNSS,321 PORT_GNSS2,322 PORT_MAC, /* miniature atomic clock */323 PORT_NMEA,324 325 __PORT_COUNT,326};327 328struct ptp_ocp {329 struct pci_dev *pdev;330 struct device dev;331 spinlock_t lock;332 struct ocp_reg __iomem *reg;333 struct tod_reg __iomem *tod;334 struct pps_reg __iomem *pps_to_ext;335 struct pps_reg __iomem *pps_to_clk;336 struct board_config_reg __iomem *board_config;337 struct gpio_reg __iomem *pps_select;338 struct gpio_reg __iomem *sma_map1;339 struct gpio_reg __iomem *sma_map2;340 struct irig_master_reg __iomem *irig_out;341 struct irig_slave_reg __iomem *irig_in;342 struct dcf_master_reg __iomem *dcf_out;343 struct dcf_slave_reg __iomem *dcf_in;344 struct tod_reg __iomem *nmea_out;345 struct frequency_reg __iomem *freq_in[4];346 struct ptp_ocp_ext_src *signal_out[4];347 struct ptp_ocp_ext_src *pps;348 struct ptp_ocp_ext_src *ts0;349 struct ptp_ocp_ext_src *ts1;350 struct ptp_ocp_ext_src *ts2;351 struct ptp_ocp_ext_src *ts3;352 struct ptp_ocp_ext_src *ts4;353 struct ocp_art_gpio_reg __iomem *art_sma;354 struct img_reg __iomem *image;355 struct ptp_clock *ptp;356 struct ptp_clock_info ptp_info;357 struct platform_device *i2c_ctrl;358 struct platform_device *spi_flash;359 struct clk_hw *i2c_clk;360 struct timer_list watchdog;361 const struct attribute_group **attr_group;362 const struct ptp_ocp_eeprom_map *eeprom_map;363 struct dentry *debug_root;364 bool sync;365 time64_t gnss_lost;366 struct delayed_work sync_work;367 int id;368 int n_irqs;369 struct ptp_ocp_serial_port port[__PORT_COUNT];370 bool fw_loader;371 u8 fw_tag;372 u16 fw_version;373 u8 board_id[OCP_BOARD_ID_LEN];374 u8 serial[OCP_SERIAL_LEN];375 bool has_eeprom_data;376 u32 pps_req_map;377 int flash_start;378 u32 utc_tai_offset;379 u32 ts_window_adjust;380 u64 fw_cap;381 struct ptp_ocp_signal signal[4];382 struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];383 const struct ocp_sma_op *sma_op;384 struct dpll_device *dpll;385};386 387#define OCP_REQ_TIMESTAMP BIT(0)388#define OCP_REQ_PPS BIT(1)389 390struct ocp_resource {391 unsigned long offset;392 int size;393 int irq_vec;394 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);395 void *extra;396 unsigned long bp_offset;397 const char * const name;398};399 400static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);401static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);402static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);403static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);404static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);405static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);406static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);407static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);408static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);409static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,410 struct ptp_perout_request *req);411static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);412static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);413 414static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);415 416static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r);417 418static const struct ocp_attr_group fb_timecard_groups[];419 420static const struct ocp_attr_group art_timecard_groups[];421 422static const struct ocp_attr_group adva_timecard_groups[];423 424struct ptp_ocp_eeprom_map {425 u16 off;426 u16 len;427 u32 bp_offset;428 const void * const tag;429};430 431#define EEPROM_ENTRY(addr, member) \432 .off = addr, \433 .len = sizeof_field(struct ptp_ocp, member), \434 .bp_offset = offsetof(struct ptp_ocp, member)435 436#define BP_MAP_ENTRY_ADDR(bp, map) ({ \437 (void *)((uintptr_t)(bp) + (map)->bp_offset); \438})439 440static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {441 { EEPROM_ENTRY(0x43, board_id) },442 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },443 { }444};445 446static struct ptp_ocp_eeprom_map art_eeprom_map[] = {447 { EEPROM_ENTRY(0x200 + 0x43, board_id) },448 { EEPROM_ENTRY(0x200 + 0x63, serial) },449 { }450};451 452#define bp_assign_entry(bp, res, val) ({ \453 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \454 *(typeof(val) *)addr = val; \455})456 457#define OCP_RES_LOCATION(member) \458 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)459 460#define OCP_MEM_RESOURCE(member) \461 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem462 463#define OCP_SERIAL_RESOURCE(member) \464 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial465 466#define OCP_I2C_RESOURCE(member) \467 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c468 469#define OCP_SPI_RESOURCE(member) \470 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi471 472#define OCP_EXT_RESOURCE(member) \473 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext474 475/* This is the MSI vector mapping used.476 * 0: PPS (TS5)477 * 1: TS0478 * 2: TS1479 * 3: GNSS1480 * 4: GNSS2481 * 5: MAC482 * 6: TS2483 * 7: I2C controller484 * 8: HWICAP (notused)485 * 9: SPI Flash486 * 10: NMEA487 * 11: Signal Generator 1488 * 12: Signal Generator 2489 * 13: Signal Generator 3490 * 14: Signal Generator 4491 * 15: TS3492 * 16: TS4493 --494 * 8: Orolia TS1495 * 10: Orolia TS2496 * 11: Orolia TS0 (GNSS)497 * 12: Orolia PPS498 * 14: Orolia TS3499 * 15: Orolia TS4500 */501 502static struct ocp_resource ocp_fb_resource[] = {503 {504 OCP_MEM_RESOURCE(reg),505 .offset = 0x01000000, .size = 0x10000,506 },507 {508 OCP_EXT_RESOURCE(ts0),509 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,510 .extra = &(struct ptp_ocp_ext_info) {511 .index = 0,512 .irq_fcn = ptp_ocp_ts_irq,513 .enable = ptp_ocp_ts_enable,514 },515 },516 {517 OCP_EXT_RESOURCE(ts1),518 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,519 .extra = &(struct ptp_ocp_ext_info) {520 .index = 1,521 .irq_fcn = ptp_ocp_ts_irq,522 .enable = ptp_ocp_ts_enable,523 },524 },525 {526 OCP_EXT_RESOURCE(ts2),527 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,528 .extra = &(struct ptp_ocp_ext_info) {529 .index = 2,530 .irq_fcn = ptp_ocp_ts_irq,531 .enable = ptp_ocp_ts_enable,532 },533 },534 {535 OCP_EXT_RESOURCE(ts3),536 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,537 .extra = &(struct ptp_ocp_ext_info) {538 .index = 3,539 .irq_fcn = ptp_ocp_ts_irq,540 .enable = ptp_ocp_ts_enable,541 },542 },543 {544 OCP_EXT_RESOURCE(ts4),545 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,546 .extra = &(struct ptp_ocp_ext_info) {547 .index = 4,548 .irq_fcn = ptp_ocp_ts_irq,549 .enable = ptp_ocp_ts_enable,550 },551 },552 /* Timestamp for PHC and/or PPS generator */553 {554 OCP_EXT_RESOURCE(pps),555 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,556 .extra = &(struct ptp_ocp_ext_info) {557 .index = 5,558 .irq_fcn = ptp_ocp_ts_irq,559 .enable = ptp_ocp_ts_enable,560 },561 },562 {563 OCP_EXT_RESOURCE(signal_out[0]),564 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,565 .extra = &(struct ptp_ocp_ext_info) {566 .index = 1,567 .irq_fcn = ptp_ocp_signal_irq,568 .enable = ptp_ocp_signal_enable,569 },570 },571 {572 OCP_EXT_RESOURCE(signal_out[1]),573 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,574 .extra = &(struct ptp_ocp_ext_info) {575 .index = 2,576 .irq_fcn = ptp_ocp_signal_irq,577 .enable = ptp_ocp_signal_enable,578 },579 },580 {581 OCP_EXT_RESOURCE(signal_out[2]),582 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,583 .extra = &(struct ptp_ocp_ext_info) {584 .index = 3,585 .irq_fcn = ptp_ocp_signal_irq,586 .enable = ptp_ocp_signal_enable,587 },588 },589 {590 OCP_EXT_RESOURCE(signal_out[3]),591 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,592 .extra = &(struct ptp_ocp_ext_info) {593 .index = 4,594 .irq_fcn = ptp_ocp_signal_irq,595 .enable = ptp_ocp_signal_enable,596 },597 },598 {599 OCP_MEM_RESOURCE(pps_to_ext),600 .offset = 0x01030000, .size = 0x10000,601 },602 {603 OCP_MEM_RESOURCE(pps_to_clk),604 .offset = 0x01040000, .size = 0x10000,605 },606 {607 OCP_MEM_RESOURCE(tod),608 .offset = 0x01050000, .size = 0x10000,609 },610 {611 OCP_MEM_RESOURCE(irig_in),612 .offset = 0x01070000, .size = 0x10000,613 },614 {615 OCP_MEM_RESOURCE(irig_out),616 .offset = 0x01080000, .size = 0x10000,617 },618 {619 OCP_MEM_RESOURCE(dcf_in),620 .offset = 0x01090000, .size = 0x10000,621 },622 {623 OCP_MEM_RESOURCE(dcf_out),624 .offset = 0x010A0000, .size = 0x10000,625 },626 {627 OCP_MEM_RESOURCE(nmea_out),628 .offset = 0x010B0000, .size = 0x10000,629 },630 {631 OCP_MEM_RESOURCE(image),632 .offset = 0x00020000, .size = 0x1000,633 },634 {635 OCP_MEM_RESOURCE(pps_select),636 .offset = 0x00130000, .size = 0x1000,637 },638 {639 OCP_MEM_RESOURCE(sma_map1),640 .offset = 0x00140000, .size = 0x1000,641 },642 {643 OCP_MEM_RESOURCE(sma_map2),644 .offset = 0x00220000, .size = 0x1000,645 },646 {647 OCP_I2C_RESOURCE(i2c_ctrl),648 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,649 .extra = &(struct ptp_ocp_i2c_info) {650 .name = "xiic-i2c",651 .fixed_rate = 50000000,652 .data_size = sizeof(struct xiic_i2c_platform_data),653 .data = &(struct xiic_i2c_platform_data) {654 .num_devices = 2,655 .devices = (struct i2c_board_info[]) {656 { I2C_BOARD_INFO("24c02", 0x50) },657 { I2C_BOARD_INFO("24mac402", 0x58),658 .platform_data = "mac" },659 },660 },661 },662 },663 {664 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),665 .offset = 0x00160000 + 0x1000, .irq_vec = 3,666 .extra = &(struct ptp_ocp_serial_port) {667 .baud = 115200,668 },669 },670 {671 OCP_SERIAL_RESOURCE(port[PORT_GNSS2]),672 .offset = 0x00170000 + 0x1000, .irq_vec = 4,673 .extra = &(struct ptp_ocp_serial_port) {674 .baud = 115200,675 },676 },677 {678 OCP_SERIAL_RESOURCE(port[PORT_MAC]),679 .offset = 0x00180000 + 0x1000, .irq_vec = 5,680 .extra = &(struct ptp_ocp_serial_port) {681 .baud = 57600,682 },683 },684 {685 OCP_SERIAL_RESOURCE(port[PORT_NMEA]),686 .offset = 0x00190000 + 0x1000, .irq_vec = 10,687 },688 {689 OCP_SPI_RESOURCE(spi_flash),690 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,691 .extra = &(struct ptp_ocp_flash_info) {692 .name = "xilinx_spi", .pci_offset = 0,693 .data_size = sizeof(struct xspi_platform_data),694 .data = &(struct xspi_platform_data) {695 .num_chipselect = 1,696 .bits_per_word = 8,697 .num_devices = 1,698 .force_irq = true,699 .devices = &(struct spi_board_info) {700 .modalias = "spi-nor",701 },702 },703 },704 },705 {706 OCP_MEM_RESOURCE(freq_in[0]),707 .offset = 0x01200000, .size = 0x10000,708 },709 {710 OCP_MEM_RESOURCE(freq_in[1]),711 .offset = 0x01210000, .size = 0x10000,712 },713 {714 OCP_MEM_RESOURCE(freq_in[2]),715 .offset = 0x01220000, .size = 0x10000,716 },717 {718 OCP_MEM_RESOURCE(freq_in[3]),719 .offset = 0x01230000, .size = 0x10000,720 },721 {722 .setup = ptp_ocp_fb_board_init,723 .extra = &(struct ptp_ocp_servo_conf) {724 .servo_offset_p = 0x2000,725 .servo_offset_i = 0x1000,726 .servo_drift_p = 0,727 .servo_drift_i = 0,728 },729 },730 { }731};732 733#define OCP_ART_CONFIG_SIZE 144734#define OCP_ART_TEMP_TABLE_SIZE 368735 736struct ocp_art_gpio_reg {737 struct {738 u32 gpio;739 u32 __pad[3];740 } map[4];741};742 743static struct ocp_resource ocp_art_resource[] = {744 {745 OCP_MEM_RESOURCE(reg),746 .offset = 0x01000000, .size = 0x10000,747 },748 {749 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),750 .offset = 0x00160000 + 0x1000, .irq_vec = 3,751 .extra = &(struct ptp_ocp_serial_port) {752 .baud = 115200,753 },754 },755 {756 OCP_MEM_RESOURCE(art_sma),757 .offset = 0x003C0000, .size = 0x1000,758 },759 /* Timestamp associated with GNSS1 receiver PPS */760 {761 OCP_EXT_RESOURCE(ts0),762 .offset = 0x360000, .size = 0x20, .irq_vec = 12,763 .extra = &(struct ptp_ocp_ext_info) {764 .index = 0,765 .irq_fcn = ptp_ocp_ts_irq,766 .enable = ptp_ocp_ts_enable,767 },768 },769 {770 OCP_EXT_RESOURCE(ts1),771 .offset = 0x380000, .size = 0x20, .irq_vec = 8,772 .extra = &(struct ptp_ocp_ext_info) {773 .index = 1,774 .irq_fcn = ptp_ocp_ts_irq,775 .enable = ptp_ocp_ts_enable,776 },777 },778 {779 OCP_EXT_RESOURCE(ts2),780 .offset = 0x390000, .size = 0x20, .irq_vec = 10,781 .extra = &(struct ptp_ocp_ext_info) {782 .index = 2,783 .irq_fcn = ptp_ocp_ts_irq,784 .enable = ptp_ocp_ts_enable,785 },786 },787 {788 OCP_EXT_RESOURCE(ts3),789 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,790 .extra = &(struct ptp_ocp_ext_info) {791 .index = 3,792 .irq_fcn = ptp_ocp_ts_irq,793 .enable = ptp_ocp_ts_enable,794 },795 },796 {797 OCP_EXT_RESOURCE(ts4),798 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,799 .extra = &(struct ptp_ocp_ext_info) {800 .index = 4,801 .irq_fcn = ptp_ocp_ts_irq,802 .enable = ptp_ocp_ts_enable,803 },804 },805 /* Timestamp associated with Internal PPS of the card */806 {807 OCP_EXT_RESOURCE(pps),808 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,809 .extra = &(struct ptp_ocp_ext_info) {810 .index = 5,811 .irq_fcn = ptp_ocp_ts_irq,812 .enable = ptp_ocp_ts_enable,813 },814 },815 {816 OCP_SPI_RESOURCE(spi_flash),817 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,818 .extra = &(struct ptp_ocp_flash_info) {819 .name = "spi_altera", .pci_offset = 0,820 .data_size = sizeof(struct altera_spi_platform_data),821 .data = &(struct altera_spi_platform_data) {822 .num_chipselect = 1,823 .num_devices = 1,824 .devices = &(struct spi_board_info) {825 .modalias = "spi-nor",826 },827 },828 },829 },830 {831 OCP_I2C_RESOURCE(i2c_ctrl),832 .offset = 0x350000, .size = 0x100, .irq_vec = 4,833 .extra = &(struct ptp_ocp_i2c_info) {834 .name = "ocores-i2c",835 .fixed_rate = 400000,836 .data_size = sizeof(struct ocores_i2c_platform_data),837 .data = &(struct ocores_i2c_platform_data) {838 .clock_khz = 125000,839 .bus_khz = 400,840 .num_devices = 1,841 .devices = &(struct i2c_board_info) {842 I2C_BOARD_INFO("24c08", 0x50),843 },844 },845 },846 },847 {848 OCP_SERIAL_RESOURCE(port[PORT_MAC]),849 .offset = 0x00190000, .irq_vec = 7,850 .extra = &(struct ptp_ocp_serial_port) {851 .baud = 9600,852 },853 },854 {855 OCP_MEM_RESOURCE(board_config),856 .offset = 0x210000, .size = 0x1000,857 },858 {859 .setup = ptp_ocp_art_board_init,860 .extra = &(struct ptp_ocp_servo_conf) {861 .servo_offset_p = 0x2000,862 .servo_offset_i = 0x1000,863 .servo_drift_p = 0,864 .servo_drift_i = 0,865 },866 },867 { }868};869 870static struct ocp_resource ocp_adva_resource[] = {871 {872 OCP_MEM_RESOURCE(reg),873 .offset = 0x01000000, .size = 0x10000,874 },875 {876 OCP_EXT_RESOURCE(ts0),877 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,878 .extra = &(struct ptp_ocp_ext_info) {879 .index = 0,880 .irq_fcn = ptp_ocp_ts_irq,881 .enable = ptp_ocp_ts_enable,882 },883 },884 {885 OCP_EXT_RESOURCE(ts1),886 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,887 .extra = &(struct ptp_ocp_ext_info) {888 .index = 1,889 .irq_fcn = ptp_ocp_ts_irq,890 .enable = ptp_ocp_ts_enable,891 },892 },893 {894 OCP_EXT_RESOURCE(ts2),895 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,896 .extra = &(struct ptp_ocp_ext_info) {897 .index = 2,898 .irq_fcn = ptp_ocp_ts_irq,899 .enable = ptp_ocp_ts_enable,900 },901 },902 /* Timestamp for PHC and/or PPS generator */903 {904 OCP_EXT_RESOURCE(pps),905 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,906 .extra = &(struct ptp_ocp_ext_info) {907 .index = 5,908 .irq_fcn = ptp_ocp_ts_irq,909 .enable = ptp_ocp_ts_enable,910 },911 },912 {913 OCP_EXT_RESOURCE(signal_out[0]),914 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,915 .extra = &(struct ptp_ocp_ext_info) {916 .index = 1,917 .irq_fcn = ptp_ocp_signal_irq,918 .enable = ptp_ocp_signal_enable,919 },920 },921 {922 OCP_EXT_RESOURCE(signal_out[1]),923 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,924 .extra = &(struct ptp_ocp_ext_info) {925 .index = 2,926 .irq_fcn = ptp_ocp_signal_irq,927 .enable = ptp_ocp_signal_enable,928 },929 },930 {931 OCP_MEM_RESOURCE(pps_to_ext),932 .offset = 0x01030000, .size = 0x10000,933 },934 {935 OCP_MEM_RESOURCE(pps_to_clk),936 .offset = 0x01040000, .size = 0x10000,937 },938 {939 OCP_MEM_RESOURCE(tod),940 .offset = 0x01050000, .size = 0x10000,941 },942 {943 OCP_MEM_RESOURCE(image),944 .offset = 0x00020000, .size = 0x1000,945 },946 {947 OCP_MEM_RESOURCE(pps_select),948 .offset = 0x00130000, .size = 0x1000,949 },950 {951 OCP_MEM_RESOURCE(sma_map1),952 .offset = 0x00140000, .size = 0x1000,953 },954 {955 OCP_MEM_RESOURCE(sma_map2),956 .offset = 0x00220000, .size = 0x1000,957 },958 {959 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),960 .offset = 0x00160000 + 0x1000, .irq_vec = 3,961 .extra = &(struct ptp_ocp_serial_port) {962 .baud = 9600,963 },964 },965 {966 OCP_SERIAL_RESOURCE(port[PORT_MAC]),967 .offset = 0x00180000 + 0x1000, .irq_vec = 5,968 .extra = &(struct ptp_ocp_serial_port) {969 .baud = 115200,970 },971 },972 {973 OCP_MEM_RESOURCE(freq_in[0]),974 .offset = 0x01200000, .size = 0x10000,975 },976 {977 OCP_MEM_RESOURCE(freq_in[1]),978 .offset = 0x01210000, .size = 0x10000,979 },980 {981 OCP_SPI_RESOURCE(spi_flash),982 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9,983 .extra = &(struct ptp_ocp_flash_info) {984 .name = "spi_altera", .pci_offset = 0,985 .data_size = sizeof(struct altera_spi_platform_data),986 .data = &(struct altera_spi_platform_data) {987 .num_chipselect = 1,988 .num_devices = 1,989 .devices = &(struct spi_board_info) {990 .modalias = "spi-nor",991 },992 },993 },994 },995 {996 OCP_I2C_RESOURCE(i2c_ctrl),997 .offset = 0x150000, .size = 0x100, .irq_vec = 7,998 .extra = &(struct ptp_ocp_i2c_info) {999 .name = "ocores-i2c",1000 .fixed_rate = 50000000,1001 .data_size = sizeof(struct ocores_i2c_platform_data),1002 .data = &(struct ocores_i2c_platform_data) {1003 .clock_khz = 50000,1004 .bus_khz = 100,1005 .reg_io_width = 4, // 32-bit/4-byte1006 .reg_shift = 2, // 32-bit addressing1007 .num_devices = 2,1008 .devices = (struct i2c_board_info[]) {1009 { I2C_BOARD_INFO("24c02", 0x50) },1010 { I2C_BOARD_INFO("24mac402", 0x58),1011 .platform_data = "mac" },1012 },1013 },1014 },1015 },1016 {1017 .setup = ptp_ocp_adva_board_init,1018 .extra = &(struct ptp_ocp_servo_conf) {1019 .servo_offset_p = 0xc000,1020 .servo_offset_i = 0x1000,1021 .servo_drift_p = 0,1022 .servo_drift_i = 0,1023 },1024 },1025 { }1026};1027 1028static const struct pci_device_id ptp_ocp_pcidev_id[] = {1029 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },1030 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },1031 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },1032 { PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) },1033 { }1034};1035MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);1036 1037static DEFINE_MUTEX(ptp_ocp_lock);1038static DEFINE_IDR(ptp_ocp_idr);1039 1040struct ocp_selector {1041 const char *name;1042 int value;1043 u64 frequency;1044};1045 1046static const struct ocp_selector ptp_ocp_clock[] = {1047 { .name = "NONE", .value = 0 },1048 { .name = "TOD", .value = 1 },1049 { .name = "IRIG", .value = 2 },1050 { .name = "PPS", .value = 3 },1051 { .name = "PTP", .value = 4 },1052 { .name = "RTC", .value = 5 },1053 { .name = "DCF", .value = 6 },1054 { .name = "REGS", .value = 0xfe },1055 { .name = "EXT", .value = 0xff },1056 { }1057};1058 1059#define SMA_DISABLE BIT(16)1060#define SMA_ENABLE BIT(15)1061#define SMA_SELECT_MASK GENMASK(14, 0)1062 1063static const struct ocp_selector ptp_ocp_sma_in[] = {1064 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },1065 { .name = "PPS1", .value = 0x0001, .frequency = 1 },1066 { .name = "PPS2", .value = 0x0002, .frequency = 1 },1067 { .name = "TS1", .value = 0x0004, .frequency = 0 },1068 { .name = "TS2", .value = 0x0008, .frequency = 0 },1069 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },1070 { .name = "DCF", .value = 0x0020, .frequency = 77500 },1071 { .name = "TS3", .value = 0x0040, .frequency = 0 },1072 { .name = "TS4", .value = 0x0080, .frequency = 0 },1073 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },1074 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },1075 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },1076 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },1077 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },1078 { }1079};1080 1081static const struct ocp_selector ptp_ocp_sma_out[] = {1082 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },1083 { .name = "PHC", .value = 0x0001, .frequency = 1 },1084 { .name = "MAC", .value = 0x0002, .frequency = 1 },1085 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },1086 { .name = "GNSS2", .value = 0x0008, .frequency = 1 },1087 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },1088 { .name = "DCF", .value = 0x0020, .frequency = 77000 },1089 { .name = "GEN1", .value = 0x0040 },1090 { .name = "GEN2", .value = 0x0080 },1091 { .name = "GEN3", .value = 0x0100 },1092 { .name = "GEN4", .value = 0x0200 },1093 { .name = "GND", .value = 0x2000 },1094 { .name = "VCC", .value = 0x4000 },1095 { }1096};1097 1098static const struct ocp_selector ptp_ocp_art_sma_in[] = {1099 { .name = "PPS1", .value = 0x0001, .frequency = 1 },1100 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },1101 { }1102};1103 1104static const struct ocp_selector ptp_ocp_art_sma_out[] = {1105 { .name = "PHC", .value = 0x0002, .frequency = 1 },1106 { .name = "GNSS", .value = 0x0004, .frequency = 1 },1107 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },1108 { }1109};1110 1111static const struct ocp_selector ptp_ocp_adva_sma_in[] = {1112 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},1113 { .name = "PPS1", .value = 0x0001, .frequency = 1 },1114 { .name = "PPS2", .value = 0x0002, .frequency = 1 },1115 { .name = "TS1", .value = 0x0004, .frequency = 0 },1116 { .name = "TS2", .value = 0x0008, .frequency = 0 },1117 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },1118 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },1119 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },1120 { }1121};1122 1123static const struct ocp_selector ptp_ocp_adva_sma_out[] = {1124 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},1125 { .name = "PHC", .value = 0x0001, .frequency = 1 },1126 { .name = "MAC", .value = 0x0002, .frequency = 1 },1127 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },1128 { .name = "GEN1", .value = 0x0040 },1129 { .name = "GEN2", .value = 0x0080 },1130 { .name = "GND", .value = 0x2000 },1131 { .name = "VCC", .value = 0x4000 },1132 { }1133};1134 1135struct ocp_sma_op {1136 const struct ocp_selector *tbl[2];1137 void (*init)(struct ptp_ocp *bp);1138 u32 (*get)(struct ptp_ocp *bp, int sma_nr);1139 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);1140 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);1141};1142 1143static void1144ptp_ocp_sma_init(struct ptp_ocp *bp)1145{1146 return bp->sma_op->init(bp);1147}1148 1149static u321150ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)1151{1152 return bp->sma_op->get(bp, sma_nr);1153}1154 1155static int1156ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)1157{1158 return bp->sma_op->set_inputs(bp, sma_nr, val);1159}1160 1161static int1162ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)1163{1164 return bp->sma_op->set_output(bp, sma_nr, val);1165}1166 1167static const char *1168ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)1169{1170 int i;1171 1172 for (i = 0; tbl[i].name; i++)1173 if (tbl[i].value == val)1174 return tbl[i].name;1175 return NULL;1176}1177 1178static int1179ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)1180{1181 const char *select;1182 int i;1183 1184 for (i = 0; tbl[i].name; i++) {1185 select = tbl[i].name;1186 if (!strncasecmp(name, select, strlen(select)))1187 return tbl[i].value;1188 }1189 return -EINVAL;1190}1191 1192static ssize_t1193ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)1194{1195 ssize_t count;1196 int i;1197 1198 count = 0;1199 for (i = 0; tbl[i].name; i++)1200 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);1201 if (count)1202 count--;1203 count += sysfs_emit_at(buf, count, "\n");1204 return count;1205}1206 1207static int1208__ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,1209 struct ptp_system_timestamp *sts)1210{1211 u32 ctrl, time_sec, time_ns;1212 int i;1213 1214 ptp_read_system_prets(sts);1215 1216 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;1217 iowrite32(ctrl, &bp->reg->ctrl);1218 1219 for (i = 0; i < 100; i++) {1220 ctrl = ioread32(&bp->reg->ctrl);1221 if (ctrl & OCP_CTRL_READ_TIME_DONE)1222 break;1223 }1224 ptp_read_system_postts(sts);1225 1226 if (sts && bp->ts_window_adjust) {1227 s64 ns = timespec64_to_ns(&sts->post_ts);1228 1229 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);1230 }1231 1232 time_ns = ioread32(&bp->reg->time_ns);1233 time_sec = ioread32(&bp->reg->time_sec);1234 1235 ts->tv_sec = time_sec;1236 ts->tv_nsec = time_ns;1237 1238 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;1239}1240 1241static int1242ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,1243 struct ptp_system_timestamp *sts)1244{1245 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);1246 unsigned long flags;1247 int err;1248 1249 spin_lock_irqsave(&bp->lock, flags);1250 err = __ptp_ocp_gettime_locked(bp, ts, sts);1251 spin_unlock_irqrestore(&bp->lock, flags);1252 1253 return err;1254}1255 1256static void1257__ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)1258{1259 u32 ctrl, time_sec, time_ns;1260 u32 select;1261 1262 time_ns = ts->tv_nsec;1263 time_sec = ts->tv_sec;1264 1265 select = ioread32(&bp->reg->select);1266 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);1267 1268 iowrite32(time_ns, &bp->reg->adjust_ns);1269 iowrite32(time_sec, &bp->reg->adjust_sec);1270 1271 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;1272 iowrite32(ctrl, &bp->reg->ctrl);1273 1274 /* restore clock selection */1275 iowrite32(select >> 16, &bp->reg->select);1276}1277 1278static int1279ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)1280{1281 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);1282 unsigned long flags;1283 1284 spin_lock_irqsave(&bp->lock, flags);1285 __ptp_ocp_settime_locked(bp, ts);1286 spin_unlock_irqrestore(&bp->lock, flags);1287 1288 return 0;1289}1290 1291static void1292__ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)1293{1294 u32 select, ctrl;1295 1296 select = ioread32(&bp->reg->select);1297 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);1298 1299 iowrite32(adj_val, &bp->reg->offset_ns);1300 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);1301 1302 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;1303 iowrite32(ctrl, &bp->reg->ctrl);1304 1305 /* restore clock selection */1306 iowrite32(select >> 16, &bp->reg->select);1307}1308 1309static void1310ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)1311{1312 struct timespec64 ts;1313 unsigned long flags;1314 int err;1315 1316 spin_lock_irqsave(&bp->lock, flags);1317 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);1318 if (likely(!err)) {1319 set_normalized_timespec64(&ts, ts.tv_sec,1320 ts.tv_nsec + delta_ns);1321 __ptp_ocp_settime_locked(bp, &ts);1322 }1323 spin_unlock_irqrestore(&bp->lock, flags);1324}1325 1326static int1327ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)1328{1329 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);1330 unsigned long flags;1331 u32 adj_ns, sign;1332 1333 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {1334 ptp_ocp_adjtime_coarse(bp, delta_ns);1335 return 0;1336 }1337 1338 sign = delta_ns < 0 ? BIT(31) : 0;1339 adj_ns = sign ? -delta_ns : delta_ns;1340 1341 spin_lock_irqsave(&bp->lock, flags);1342 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);1343 spin_unlock_irqrestore(&bp->lock, flags);1344 1345 return 0;1346}1347 1348static int1349ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)1350{1351 if (scaled_ppm == 0)1352 return 0;1353 1354 return -EOPNOTSUPP;1355}1356 1357static s321358ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)1359{1360 return 0;1361}1362 1363static int1364ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)1365{1366 return -EOPNOTSUPP;1367}1368 1369static int1370ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,1371 int on)1372{1373 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);1374 struct ptp_ocp_ext_src *ext = NULL;1375 u32 req;1376 int err;1377 1378 switch (rq->type) {1379 case PTP_CLK_REQ_EXTTS:1380 req = OCP_REQ_TIMESTAMP;1381 switch (rq->extts.index) {1382 case 0:1383 ext = bp->ts0;1384 break;1385 case 1:1386 ext = bp->ts1;1387 break;1388 case 2:1389 ext = bp->ts2;1390 break;1391 case 3:1392 ext = bp->ts3;1393 break;1394 case 4:1395 ext = bp->ts4;1396 break;1397 case 5:1398 ext = bp->pps;1399 break;1400 }1401 break;1402 case PTP_CLK_REQ_PPS:1403 req = OCP_REQ_PPS;1404 ext = bp->pps;1405 break;1406 case PTP_CLK_REQ_PEROUT:1407 switch (rq->perout.index) {1408 case 0:1409 /* This is a request for 1PPS on an output SMA.1410 * Allow, but assume manual configuration.1411 */1412 if (on && (rq->perout.period.sec != 1 ||1413 rq->perout.period.nsec != 0))1414 return -EINVAL;1415 return 0;1416 case 1:1417 case 2:1418 case 3:1419 case 4:1420 req = rq->perout.index - 1;1421 ext = bp->signal_out[req];1422 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);1423 if (err)1424 return err;1425 break;1426 }1427 break;1428 default:1429 return -EOPNOTSUPP;1430 }1431 1432 err = -ENXIO;1433 if (ext)1434 err = ext->info->enable(ext, req, on);1435 1436 return err;1437}1438 1439static int1440ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,1441 enum ptp_pin_function func, unsigned chan)1442{1443 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);1444 char buf[16];1445 1446 switch (func) {1447 case PTP_PF_NONE:1448 snprintf(buf, sizeof(buf), "IN: None");1449 break;1450 case PTP_PF_EXTTS:1451 /* Allow timestamps, but require sysfs configuration. */1452 return 0;1453 case PTP_PF_PEROUT:1454 /* channel 0 is 1PPS from PHC.1455 * channels 1..4 are the frequency generators.1456 */1457 if (chan)1458 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);1459 else1460 snprintf(buf, sizeof(buf), "OUT: PHC");1461 break;1462 default:1463 return -EOPNOTSUPP;1464 }1465 1466 return ptp_ocp_sma_store(bp, buf, pin + 1);1467}1468 1469static const struct ptp_clock_info ptp_ocp_clock_info = {1470 .owner = THIS_MODULE,1471 .name = KBUILD_MODNAME,1472 .max_adj = 100000000,1473 .gettimex64 = ptp_ocp_gettimex,1474 .settime64 = ptp_ocp_settime,1475 .adjtime = ptp_ocp_adjtime,1476 .adjfine = ptp_ocp_null_adjfine,1477 .adjphase = ptp_ocp_null_adjphase,1478 .getmaxphase = ptp_ocp_null_getmaxphase,1479 .enable = ptp_ocp_enable,1480 .verify = ptp_ocp_verify,1481 .pps = true,1482 .n_ext_ts = 6,1483 .n_per_out = 5,1484};1485 1486static void1487__ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)1488{1489 u32 ctrl, select;1490 1491 select = ioread32(&bp->reg->select);1492 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);1493 1494 iowrite32(0, &bp->reg->drift_ns);1495 1496 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;1497 iowrite32(ctrl, &bp->reg->ctrl);1498 1499 /* restore clock selection */1500 iowrite32(select >> 16, &bp->reg->select);1501}1502 1503static void1504ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)1505{1506 unsigned long flags;1507 1508 spin_lock_irqsave(&bp->lock, flags);1509 1510 bp->utc_tai_offset = val;1511 1512 if (bp->irig_out)1513 iowrite32(val, &bp->irig_out->adj_sec);1514 if (bp->dcf_out)1515 iowrite32(val, &bp->dcf_out->adj_sec);1516 if (bp->nmea_out)1517 iowrite32(val, &bp->nmea_out->adj_sec);1518 1519 spin_unlock_irqrestore(&bp->lock, flags);1520}1521 1522static void1523ptp_ocp_watchdog(struct timer_list *t)1524{1525 struct ptp_ocp *bp = from_timer(bp, t, watchdog);1526 unsigned long flags;1527 u32 status, utc_offset;1528 1529 status = ioread32(&bp->pps_to_clk->status);1530 1531 if (status & PPS_STATUS_SUPERV_ERR) {1532 iowrite32(status, &bp->pps_to_clk->status);1533 if (!bp->gnss_lost) {1534 spin_lock_irqsave(&bp->lock, flags);1535 __ptp_ocp_clear_drift_locked(bp);1536 spin_unlock_irqrestore(&bp->lock, flags);1537 bp->gnss_lost = ktime_get_real_seconds();1538 }1539 1540 } else if (bp->gnss_lost) {1541 bp->gnss_lost = 0;1542 }1543 1544 /* if GNSS provides correct data we can rely on1545 * it to get leap second information1546 */1547 if (bp->tod) {1548 status = ioread32(&bp->tod->utc_status);1549 utc_offset = status & TOD_STATUS_UTC_MASK;1550 if (status & TOD_STATUS_UTC_VALID &&1551 utc_offset != bp->utc_tai_offset)1552 ptp_ocp_utc_distribute(bp, utc_offset);1553 }1554 1555 mod_timer(&bp->watchdog, jiffies + HZ);1556}1557 1558static void1559ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)1560{1561 ktime_t start, end, delay = U64_MAX;1562 u32 ctrl;1563 int i;1564 1565 for (i = 0; i < 3; i++) {1566 ctrl = ioread32(&bp->reg->ctrl);1567 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;1568 1569 iowrite32(ctrl, &bp->reg->ctrl);1570 1571 start = ktime_get_raw_ns();1572 1573 ctrl = ioread32(&bp->reg->ctrl);1574 1575 end = ktime_get_raw_ns();1576 1577 delay = min(delay, end - start);1578 }1579 bp->ts_window_adjust = (delay >> 5) * 3;1580}1581 1582static int1583ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf)1584{1585 struct timespec64 ts;1586 u32 ctrl;1587 1588 ctrl = OCP_CTRL_ENABLE;1589 iowrite32(ctrl, &bp->reg->ctrl);1590 1591 /* servo configuration */1592 iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p);1593 iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i);1594 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p);1595 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i);1596 1597 /* latch servo values */1598 ctrl |= OCP_CTRL_ADJUST_SERVO;1599 iowrite32(ctrl, &bp->reg->ctrl);1600 1601 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {1602 dev_err(&bp->pdev->dev, "clock not enabled\n");1603 return -ENODEV;1604 }1605 1606 ptp_ocp_estimate_pci_timing(bp);1607 1608 bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;1609 if (!bp->sync) {1610 ktime_get_clocktai_ts64(&ts);1611 ptp_ocp_settime(&bp->ptp_info, &ts);1612 }1613 1614 /* If there is a clock supervisor, then enable the watchdog */1615 if (bp->pps_to_clk) {1616 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);1617 mod_timer(&bp->watchdog, jiffies + HZ);1618 }1619 1620 return 0;1621}1622 1623static void1624ptp_ocp_tod_init(struct ptp_ocp *bp)1625{1626 u32 ctrl, reg;1627 1628 ctrl = ioread32(&bp->tod->ctrl);1629 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;1630 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);1631 iowrite32(ctrl, &bp->tod->ctrl);1632 1633 reg = ioread32(&bp->tod->utc_status);1634 if (reg & TOD_STATUS_UTC_VALID)1635 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);1636}1637 1638static const char *1639ptp_ocp_tod_proto_name(const int idx)1640{1641 static const char * const proto_name[] = {1642 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",1643 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"1644 };1645 return proto_name[idx];1646}1647 1648static const char *1649ptp_ocp_tod_gnss_name(int idx)1650{1651 static const char * const gnss_name[] = {1652 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",1653 "Unknown"1654 };1655 if (idx >= ARRAY_SIZE(gnss_name))1656 idx = ARRAY_SIZE(gnss_name) - 1;1657 return gnss_name[idx];1658}1659 1660static const char *1661ptp_ocp_tty_port_name(int idx)1662{1663 static const char * const tty_name[] = {1664 "GNSS", "GNSS2", "MAC", "NMEA"1665 };1666 return tty_name[idx];1667}1668 1669struct ptp_ocp_nvmem_match_info {1670 struct ptp_ocp *bp;1671 const void * const tag;1672};1673 1674static int1675ptp_ocp_nvmem_match(struct device *dev, const void *data)1676{1677 const struct ptp_ocp_nvmem_match_info *info = data;1678 1679 dev = dev->parent;1680 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)1681 return 0;1682 1683 while ((dev = dev->parent))1684 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))1685 return info->bp == dev_get_drvdata(dev);1686 return 0;1687}1688 1689static inline struct nvmem_device *1690ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)1691{1692 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };1693 1694 return nvmem_device_find(&info, ptp_ocp_nvmem_match);1695}1696 1697static inline void1698ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)1699{1700 if (!IS_ERR_OR_NULL(*nvmemp))1701 nvmem_device_put(*nvmemp);1702 *nvmemp = NULL;1703}1704 1705static void1706ptp_ocp_read_eeprom(struct ptp_ocp *bp)1707{1708 const struct ptp_ocp_eeprom_map *map;1709 struct nvmem_device *nvmem;1710 const void *tag;1711 int ret;1712 1713 if (!bp->i2c_ctrl)1714 return;1715 1716 tag = NULL;1717 nvmem = NULL;1718 1719 for (map = bp->eeprom_map; map->len; map++) {1720 if (map->tag != tag) {1721 tag = map->tag;1722 ptp_ocp_nvmem_device_put(&nvmem);1723 }1724 if (!nvmem) {1725 nvmem = ptp_ocp_nvmem_device_get(bp, tag);1726 if (IS_ERR(nvmem)) {1727 ret = PTR_ERR(nvmem);1728 goto fail;1729 }1730 }1731 ret = nvmem_device_read(nvmem, map->off, map->len,1732 BP_MAP_ENTRY_ADDR(bp, map));1733 if (ret != map->len)1734 goto fail;1735 }1736 1737 bp->has_eeprom_data = true;1738 1739out:1740 ptp_ocp_nvmem_device_put(&nvmem);1741 return;1742 1743fail:1744 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);1745 goto out;1746}1747 1748static struct device *1749ptp_ocp_find_flash(struct ptp_ocp *bp)1750{1751 struct device *dev, *last;1752 1753 last = NULL;1754 dev = &bp->spi_flash->dev;1755 1756 while ((dev = device_find_any_child(dev))) {1757 if (!strcmp("mtd", dev_bus_name(dev)))1758 break;1759 put_device(last);1760 last = dev;1761 }1762 put_device(last);1763 1764 return dev;1765}1766 1767static int1768ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,1769 const u8 **data, size_t *size)1770{1771 struct ptp_ocp *bp = devlink_priv(devlink);1772 const struct ptp_ocp_firmware_header *hdr;1773 size_t offset, length;1774 u16 crc;1775 1776 hdr = (const struct ptp_ocp_firmware_header *)fw->data;1777 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {1778 devlink_flash_update_status_notify(devlink,1779 "No firmware header found, cancel firmware upgrade",1780 NULL, 0, 0);1781 return -EINVAL;1782 }1783 1784 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||1785 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {1786 devlink_flash_update_status_notify(devlink,1787 "Firmware image compatibility check failed",1788 NULL, 0, 0);1789 return -EINVAL;1790 }1791 1792 offset = sizeof(*hdr);1793 length = be32_to_cpu(hdr->image_size);1794 if (length != (fw->size - offset)) {1795 devlink_flash_update_status_notify(devlink,1796 "Firmware image size check failed",1797 NULL, 0, 0);1798 return -EINVAL;1799 }1800 1801 crc = crc16(0xffff, &fw->data[offset], length);1802 if (be16_to_cpu(hdr->crc) != crc) {1803 devlink_flash_update_status_notify(devlink,1804 "Firmware image CRC check failed",1805 NULL, 0, 0);1806 return -EINVAL;1807 }1808 1809 *data = &fw->data[offset];1810 *size = length;1811 1812 return 0;1813}1814 1815static int1816ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,1817 const struct firmware *fw)1818{1819 struct mtd_info *mtd = dev_get_drvdata(dev);1820 struct ptp_ocp *bp = devlink_priv(devlink);1821 size_t off, len, size, resid, wrote;1822 struct erase_info erase;1823 size_t base, blksz;1824 const u8 *data;1825 int err;1826 1827 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);1828 if (err)1829 goto out;1830 1831 off = 0;1832 base = bp->flash_start;1833 blksz = 4096;1834 resid = size;1835 1836 while (resid) {1837 devlink_flash_update_status_notify(devlink, "Flashing",1838 NULL, off, size);1839 1840 len = min_t(size_t, resid, blksz);1841 erase.addr = base + off;1842 erase.len = blksz;1843 1844 err = mtd_erase(mtd, &erase);1845 if (err)1846 goto out;1847 1848 err = mtd_write(mtd, base + off, len, &wrote, data + off);1849 if (err)1850 goto out;1851 1852 off += blksz;1853 resid -= len;1854 }1855out:1856 return err;1857}1858 1859static int1860ptp_ocp_devlink_flash_update(struct devlink *devlink,1861 struct devlink_flash_update_params *params,1862 struct netlink_ext_ack *extack)1863{1864 struct ptp_ocp *bp = devlink_priv(devlink);1865 struct device *dev;1866 const char *msg;1867 int err;1868 1869 dev = ptp_ocp_find_flash(bp);1870 if (!dev) {1871 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");1872 return -ENODEV;1873 }1874 1875 devlink_flash_update_status_notify(devlink, "Preparing to flash",1876 NULL, 0, 0);1877 1878 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);1879 1880 msg = err ? "Flash error" : "Flash complete";1881 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);1882 1883 put_device(dev);1884 return err;1885}1886 1887static int1888ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,1889 struct netlink_ext_ack *extack)1890{1891 struct ptp_ocp *bp = devlink_priv(devlink);1892 const char *fw_image;1893 char buf[32];1894 int err;1895 1896 fw_image = bp->fw_loader ? "loader" : "fw";1897 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);1898 err = devlink_info_version_running_put(req, fw_image, buf);1899 if (err)1900 return err;1901 1902 if (!bp->has_eeprom_data) {1903 ptp_ocp_read_eeprom(bp);1904 if (!bp->has_eeprom_data)1905 return 0;1906 }1907 1908 sprintf(buf, "%pM", bp->serial);1909 err = devlink_info_serial_number_put(req, buf);1910 if (err)1911 return err;1912 1913 err = devlink_info_version_fixed_put(req,1914 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,1915 bp->board_id);1916 if (err)1917 return err;1918 1919 return 0;1920}1921 1922static const struct devlink_ops ptp_ocp_devlink_ops = {1923 .flash_update = ptp_ocp_devlink_flash_update,1924 .info_get = ptp_ocp_devlink_info_get,1925};1926 1927static void __iomem *1928__ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)1929{1930 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");1931 1932 return devm_ioremap_resource(&bp->pdev->dev, &res);1933}1934 1935static void __iomem *1936ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)1937{1938 resource_size_t start;1939 1940 start = pci_resource_start(bp->pdev, 0) + r->offset;1941 return __ptp_ocp_get_mem(bp, start, r->size);1942}1943 1944static int1945ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)1946{1947 struct ptp_ocp_flash_info *info;1948 struct pci_dev *pdev = bp->pdev;1949 struct platform_device *p;1950 struct resource res[2];1951 resource_size_t start;1952 int id;1953 1954 start = pci_resource_start(pdev, 0) + r->offset;1955 res[0] = DEFINE_RES_MEM(start, r->size);1956 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));1957 1958 info = r->extra;1959 id = pci_dev_id(pdev) << 1;1960 id += info->pci_offset;1961 1962 p = platform_device_register_resndata(&pdev->dev, info->name, id,1963 res, ARRAY_SIZE(res), info->data,1964 info->data_size);1965 if (IS_ERR(p))1966 return PTR_ERR(p);1967 1968 bp_assign_entry(bp, r, p);1969 1970 return 0;1971}1972 1973static struct platform_device *1974ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)1975{1976 struct ptp_ocp_i2c_info *info;1977 struct resource res[2];1978 resource_size_t start;1979 1980 info = r->extra;1981 start = pci_resource_start(pdev, 0) + r->offset;1982 res[0] = DEFINE_RES_MEM(start, r->size);1983 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));1984 1985 return platform_device_register_resndata(&pdev->dev, info->name,1986 id, res, ARRAY_SIZE(res),1987 info->data, info->data_size);1988}1989 1990static int1991ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)1992{1993 struct pci_dev *pdev = bp->pdev;1994 struct ptp_ocp_i2c_info *info;1995 struct platform_device *p;1996 struct clk_hw *clk;1997 char buf[32];1998 int id;1999 2000 info = r->extra;2001 id = pci_dev_id(bp->pdev);2002 2003 sprintf(buf, "AXI.%d", id);2004 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,2005 info->fixed_rate);2006 if (IS_ERR(clk))2007 return PTR_ERR(clk);2008 bp->i2c_clk = clk;2009 2010 sprintf(buf, "%s.%d", info->name, id);2011 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);2012 p = ptp_ocp_i2c_bus(bp->pdev, r, id);2013 if (IS_ERR(p))2014 return PTR_ERR(p);2015 2016 bp_assign_entry(bp, r, p);2017 2018 return 0;2019}2020 2021/* The expectation is that this is triggered only on error. */2022static irqreturn_t2023ptp_ocp_signal_irq(int irq, void *priv)2024{2025 struct ptp_ocp_ext_src *ext = priv;2026 struct signal_reg __iomem *reg = ext->mem;2027 struct ptp_ocp *bp = ext->bp;2028 u32 enable, status;2029 int gen;2030 2031 gen = ext->info->index - 1;2032 2033 enable = ioread32(®->enable);2034 status = ioread32(®->status);2035 2036 /* disable generator on error */2037 if (status || !enable) {2038 iowrite32(0, ®->intr_mask);2039 iowrite32(0, ®->enable);2040 bp->signal[gen].running = false;2041 }2042 2043 iowrite32(0, ®->intr); /* ack interrupt */2044 2045 return IRQ_HANDLED;2046}2047 2048static int2049ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)2050{2051 struct ptp_system_timestamp sts;2052 struct timespec64 ts;2053 ktime_t start_ns;2054 int err;2055 2056 if (!s->period)2057 return 0;2058 2059 if (!s->pulse)2060 s->pulse = ktime_divns(s->period * s->duty, 100);2061 2062 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);2063 if (err)2064 return err;2065 2066 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;2067 if (!s->start) {2068 /* roundup() does not work on 32-bit systems */2069 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);2070 s->start = ktime_add(s->start, s->phase);2071 }2072 2073 if (s->duty < 1 || s->duty > 99)2074 return -EINVAL;2075 2076 if (s->pulse < 1 || s->pulse > s->period)2077 return -EINVAL;2078 2079 if (s->start < start_ns)2080 return -EINVAL;2081 2082 bp->signal[gen] = *s;2083 2084 return 0;2085}2086 2087static int2088ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,2089 struct ptp_perout_request *req)2090{2091 struct ptp_ocp_signal s = { };2092 2093 s.polarity = bp->signal[gen].polarity;2094 s.period = ktime_set(req->period.sec, req->period.nsec);2095 if (!s.period)2096 return 0;2097 2098 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {2099 s.pulse = ktime_set(req->on.sec, req->on.nsec);2100 s.duty = ktime_divns(s.pulse * 100, s.period);2101 }2102 2103 if (req->flags & PTP_PEROUT_PHASE)2104 s.phase = ktime_set(req->phase.sec, req->phase.nsec);2105 else2106 s.start = ktime_set(req->start.sec, req->start.nsec);2107 2108 return ptp_ocp_signal_set(bp, gen, &s);2109}2110 2111static int2112ptp_ocp_signal_enable(void *priv, u32 req, bool enable)2113{2114 struct ptp_ocp_ext_src *ext = priv;2115 struct signal_reg __iomem *reg = ext->mem;2116 struct ptp_ocp *bp = ext->bp;2117 struct timespec64 ts;2118 int gen;2119 2120 gen = ext->info->index - 1;2121 2122 iowrite32(0, ®->intr_mask);2123 iowrite32(0, ®->enable);2124 bp->signal[gen].running = false;2125 if (!enable)2126 return 0;2127 2128 ts = ktime_to_timespec64(bp->signal[gen].start);2129 iowrite32(ts.tv_sec, ®->start_sec);2130 iowrite32(ts.tv_nsec, ®->start_ns);2131 2132 ts = ktime_to_timespec64(bp->signal[gen].period);2133 iowrite32(ts.tv_sec, ®->period_sec);2134 iowrite32(ts.tv_nsec, ®->period_ns);2135 2136 ts = ktime_to_timespec64(bp->signal[gen].pulse);2137 iowrite32(ts.tv_sec, ®->pulse_sec);2138 iowrite32(ts.tv_nsec, ®->pulse_ns);2139 2140 iowrite32(bp->signal[gen].polarity, ®->polarity);2141 iowrite32(0, ®->repeat_count);2142 2143 iowrite32(0, ®->intr); /* clear interrupt state */2144 iowrite32(1, ®->intr_mask); /* enable interrupt */2145 iowrite32(3, ®->enable); /* valid & enable */2146 2147 bp->signal[gen].running = true;2148 2149 return 0;2150}2151 2152static irqreturn_t2153ptp_ocp_ts_irq(int irq, void *priv)2154{2155 struct ptp_ocp_ext_src *ext = priv;2156 struct ts_reg __iomem *reg = ext->mem;2157 struct ptp_clock_event ev;2158 u32 sec, nsec;2159 2160 if (ext == ext->bp->pps) {2161 if (ext->bp->pps_req_map & OCP_REQ_PPS) {2162 ev.type = PTP_CLOCK_PPS;2163 ptp_clock_event(ext->bp->ptp, &ev);2164 }2165 2166 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)2167 goto out;2168 }2169 2170 /* XXX should fix API - this converts s/ns -> ts -> s/ns */2171 sec = ioread32(®->time_sec);2172 nsec = ioread32(®->time_ns);2173 2174 ev.type = PTP_CLOCK_EXTTS;2175 ev.index = ext->info->index;2176 ev.timestamp = sec * NSEC_PER_SEC + nsec;2177 2178 ptp_clock_event(ext->bp->ptp, &ev);2179 2180out:2181 iowrite32(1, ®->intr); /* write 1 to ack */2182 2183 return IRQ_HANDLED;2184}2185 2186static int2187ptp_ocp_ts_enable(void *priv, u32 req, bool enable)2188{2189 struct ptp_ocp_ext_src *ext = priv;2190 struct ts_reg __iomem *reg = ext->mem;2191 struct ptp_ocp *bp = ext->bp;2192 2193 if (ext == bp->pps) {2194 u32 old_map = bp->pps_req_map;2195 2196 if (enable)2197 bp->pps_req_map |= req;2198 else2199 bp->pps_req_map &= ~req;2200 2201 /* if no state change, just return */2202 if ((!!old_map ^ !!bp->pps_req_map) == 0)2203 return 0;2204 }2205 2206 if (enable) {2207 iowrite32(1, ®->enable);2208 iowrite32(1, ®->intr_mask);2209 iowrite32(1, ®->intr);2210 } else {2211 iowrite32(0, ®->intr_mask);2212 iowrite32(0, ®->enable);2213 }2214 2215 return 0;2216}2217 2218static void2219ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)2220{2221 ext->info->enable(ext, ~0, false);2222 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);2223 kfree(ext);2224}2225 2226static int2227ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)2228{2229 struct pci_dev *pdev = bp->pdev;2230 struct ptp_ocp_ext_src *ext;2231 int err;2232 2233 ext = kzalloc(sizeof(*ext), GFP_KERNEL);2234 if (!ext)2235 return -ENOMEM;2236 2237 ext->mem = ptp_ocp_get_mem(bp, r);2238 if (IS_ERR(ext->mem)) {2239 err = PTR_ERR(ext->mem);2240 goto out;2241 }2242 2243 ext->bp = bp;2244 ext->info = r->extra;2245 ext->irq_vec = r->irq_vec;2246 2247 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,2248 ext, "ocp%d.%s", bp->id, r->name);2249 if (err) {2250 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);2251 goto out;2252 }2253 2254 bp_assign_entry(bp, r, ext);2255 2256 return 0;2257 2258out:2259 kfree(ext);2260 return err;2261}2262 2263static int2264ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)2265{2266 struct pci_dev *pdev = bp->pdev;2267 struct uart_8250_port uart;2268 2269 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets2270 * the serial port device claim and release the pci resource.2271 */2272 memset(&uart, 0, sizeof(uart));2273 uart.port.dev = &pdev->dev;2274 uart.port.iotype = UPIO_MEM;2275 uart.port.regshift = 2;2276 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;2277 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);2278 uart.port.uartclk = 50000000;2279 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;2280 uart.port.type = PORT_16550A;2281 2282 return serial8250_register_8250_port(&uart);2283}2284 2285static int2286ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)2287{2288 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;2289 struct ptp_ocp_serial_port port = {};2290 2291 port.line = ptp_ocp_serial_line(bp, r);2292 if (port.line < 0)2293 return port.line;2294 2295 if (p)2296 port.baud = p->baud;2297 2298 bp_assign_entry(bp, r, port);2299 2300 return 0;2301}2302 2303static int2304ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)2305{2306 void __iomem *mem;2307 2308 mem = ptp_ocp_get_mem(bp, r);2309 if (IS_ERR(mem))2310 return PTR_ERR(mem);2311 2312 bp_assign_entry(bp, r, mem);2313 2314 return 0;2315}2316 2317static void2318ptp_ocp_nmea_out_init(struct ptp_ocp *bp)2319{2320 if (!bp->nmea_out)2321 return;2322 2323 iowrite32(0, &bp->nmea_out->ctrl); /* disable */2324 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */2325 iowrite32(1, &bp->nmea_out->ctrl); /* enable */2326}2327 2328static void2329_ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)2330{2331 u32 val;2332 2333 iowrite32(0, ®->enable); /* disable */2334 2335 val = ioread32(®->polarity);2336 s->polarity = val ? true : false;2337 s->duty = 50;2338}2339 2340static void2341ptp_ocp_signal_init(struct ptp_ocp *bp)2342{2343 int i;2344 2345 for (i = 0; i < 4; i++)2346 if (bp->signal_out[i])2347 _ptp_ocp_signal_init(&bp->signal[i],2348 bp->signal_out[i]->mem);2349}2350 2351static void2352ptp_ocp_attr_group_del(struct ptp_ocp *bp)2353{2354 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);2355 kfree(bp->attr_group);2356}2357 2358static int2359ptp_ocp_attr_group_add(struct ptp_ocp *bp,2360 const struct ocp_attr_group *attr_tbl)2361{2362 int count, i;2363 int err;2364 2365 count = 0;2366 for (i = 0; attr_tbl[i].cap; i++)2367 if (attr_tbl[i].cap & bp->fw_cap)2368 count++;2369 2370 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),2371 GFP_KERNEL);2372 if (!bp->attr_group)2373 return -ENOMEM;2374 2375 count = 0;2376 for (i = 0; attr_tbl[i].cap; i++)2377 if (attr_tbl[i].cap & bp->fw_cap)2378 bp->attr_group[count++] = attr_tbl[i].group;2379 2380 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);2381 if (err)2382 bp->attr_group[0] = NULL;2383 2384 return err;2385}2386 2387static void2388ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)2389{2390 u32 ctrl;2391 bool on;2392 2393 ctrl = ioread32(reg);2394 on = ctrl & bit;2395 if (on ^ enable) {2396 ctrl &= ~bit;2397 ctrl |= enable ? bit : 0;2398 iowrite32(ctrl, reg);2399 }2400}2401 2402static void2403ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)2404{2405 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,2406 IRIG_M_CTRL_ENABLE, enable);2407}2408 2409static void2410ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)2411{2412 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,2413 IRIG_S_CTRL_ENABLE, enable);2414}2415 2416static void2417ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)2418{2419 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,2420 DCF_M_CTRL_ENABLE, enable);2421}2422 2423static void2424ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)2425{2426 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,2427 DCF_S_CTRL_ENABLE, enable);2428}2429 2430static void2431__handle_signal_outputs(struct ptp_ocp *bp, u32 val)2432{2433 ptp_ocp_irig_out(bp, val & 0x00100010);2434 ptp_ocp_dcf_out(bp, val & 0x00200020);2435}2436 2437static void2438__handle_signal_inputs(struct ptp_ocp *bp, u32 val)2439{2440 ptp_ocp_irig_in(bp, val & 0x00100010);2441 ptp_ocp_dcf_in(bp, val & 0x00200020);2442}2443 2444static u322445ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)2446{2447 u32 __iomem *gpio;2448 u32 shift;2449 2450 if (bp->sma[sma_nr - 1].fixed_fcn)2451 return (sma_nr - 1) & 1;2452 2453 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)2454 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;2455 else2456 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;2457 shift = sma_nr & 1 ? 0 : 16;2458 2459 return (ioread32(gpio) >> shift) & 0xffff;2460}2461 2462static int2463ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)2464{2465 u32 reg, mask, shift;2466 unsigned long flags;2467 u32 __iomem *gpio;2468 2469 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;2470 shift = sma_nr & 1 ? 0 : 16;2471 2472 mask = 0xffff << (16 - shift);2473 2474 spin_lock_irqsave(&bp->lock, flags);2475 2476 reg = ioread32(gpio);2477 reg = (reg & mask) | (val << shift);2478 2479 __handle_signal_outputs(bp, reg);2480 2481 iowrite32(reg, gpio);2482 2483 spin_unlock_irqrestore(&bp->lock, flags);2484 2485 return 0;2486}2487 2488static int2489ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)2490{2491 u32 reg, mask, shift;2492 unsigned long flags;2493 u32 __iomem *gpio;2494 2495 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;2496 shift = sma_nr & 1 ? 0 : 16;2497 2498 mask = 0xffff << (16 - shift);2499 2500 spin_lock_irqsave(&bp->lock, flags);2501 2502 reg = ioread32(gpio);2503 reg = (reg & mask) | (val << shift);2504 2505 __handle_signal_inputs(bp, reg);2506 2507 iowrite32(reg, gpio);2508 2509 spin_unlock_irqrestore(&bp->lock, flags);2510 2511 return 0;2512}2513 2514static void2515ptp_ocp_sma_fb_init(struct ptp_ocp *bp)2516{2517 struct dpll_pin_properties prop = {2518 .board_label = NULL,2519 .type = DPLL_PIN_TYPE_EXT,2520 .capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,2521 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),2522 .freq_supported = ptp_ocp_sma_freq,2523 2524 };2525 u32 reg;2526 int i;2527 2528 /* defaults */2529 for (i = 0; i < OCP_SMA_NUM; i++) {2530 bp->sma[i].default_fcn = i & 1;2531 bp->sma[i].dpll_prop = prop;2532 bp->sma[i].dpll_prop.board_label =2533 bp->ptp_info.pin_config[i].name;2534 }2535 bp->sma[0].mode = SMA_MODE_IN;2536 bp->sma[1].mode = SMA_MODE_IN;2537 bp->sma[2].mode = SMA_MODE_OUT;2538 bp->sma[3].mode = SMA_MODE_OUT;2539 /* If no SMA1 map, the pin functions and directions are fixed. */2540 if (!bp->sma_map1) {2541 for (i = 0; i < OCP_SMA_NUM; i++) {2542 bp->sma[i].fixed_fcn = true;2543 bp->sma[i].fixed_dir = true;2544 bp->sma[1].dpll_prop.capabilities &=2545 ~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;2546 }2547 return;2548 }2549 2550 /* If SMA2 GPIO output map is all 1, it is not present.2551 * This indicates the firmware has fixed direction SMA pins.2552 */2553 reg = ioread32(&bp->sma_map2->gpio2);2554 if (reg == 0xffffffff) {2555 for (i = 0; i < OCP_SMA_NUM; i++)2556 bp->sma[i].fixed_dir = true;2557 } else {2558 reg = ioread32(&bp->sma_map1->gpio1);2559 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;2560 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;2561 2562 reg = ioread32(&bp->sma_map1->gpio2);2563 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;2564 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;2565 }2566}2567 2568static const struct ocp_sma_op ocp_fb_sma_op = {2569 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },2570 .init = ptp_ocp_sma_fb_init,2571 .get = ptp_ocp_sma_fb_get,2572 .set_inputs = ptp_ocp_sma_fb_set_inputs,2573 .set_output = ptp_ocp_sma_fb_set_output,2574};2575 2576static const struct ocp_sma_op ocp_adva_sma_op = {2577 .tbl = { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out },2578 .init = ptp_ocp_sma_fb_init,2579 .get = ptp_ocp_sma_fb_get,2580 .set_inputs = ptp_ocp_sma_fb_set_inputs,2581 .set_output = ptp_ocp_sma_fb_set_output,2582};2583 2584static int2585ptp_ocp_set_pins(struct ptp_ocp *bp)2586{2587 struct ptp_pin_desc *config;2588 int i;2589 2590 config = kcalloc(4, sizeof(*config), GFP_KERNEL);2591 if (!config)2592 return -ENOMEM;2593 2594 for (i = 0; i < 4; i++) {2595 sprintf(config[i].name, "sma%d", i + 1);2596 config[i].index = i;2597 }2598 2599 bp->ptp_info.n_pins = 4;2600 bp->ptp_info.pin_config = config;2601 2602 return 0;2603}2604 2605static void2606ptp_ocp_fb_set_version(struct ptp_ocp *bp)2607{2608 u64 cap = OCP_CAP_BASIC;2609 u32 version;2610 2611 version = ioread32(&bp->image->version);2612 2613 /* if lower 16 bits are empty, this is the fw loader. */2614 if ((version & 0xffff) == 0) {2615 version = version >> 16;2616 bp->fw_loader = true;2617 }2618 2619 bp->fw_tag = version >> 15;2620 bp->fw_version = version & 0x7fff;2621 2622 if (bp->fw_tag) {2623 /* FPGA firmware */2624 if (version >= 5)2625 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;2626 } else {2627 /* SOM firmware */2628 if (version >= 19)2629 cap |= OCP_CAP_SIGNAL;2630 if (version >= 20)2631 cap |= OCP_CAP_FREQ;2632 }2633 2634 bp->fw_cap = cap;2635}2636 2637/* FB specific board initializers; last "resource" registered. */2638static int2639ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)2640{2641 int err;2642 2643 bp->flash_start = 1024 * 4096;2644 bp->eeprom_map = fb_eeprom_map;2645 bp->fw_version = ioread32(&bp->image->version);2646 bp->sma_op = &ocp_fb_sma_op;2647 2648 ptp_ocp_fb_set_version(bp);2649 2650 ptp_ocp_tod_init(bp);2651 ptp_ocp_nmea_out_init(bp);2652 ptp_ocp_signal_init(bp);2653 2654 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);2655 if (err)2656 return err;2657 2658 err = ptp_ocp_set_pins(bp);2659 if (err)2660 return err;2661 ptp_ocp_sma_init(bp);2662 2663 return ptp_ocp_init_clock(bp, r->extra);2664}2665 2666static bool2667ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)2668{2669 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;2670 2671 if (!allow)2672 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",2673 r->irq_vec, r->name);2674 return allow;2675}2676 2677static int2678ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)2679{2680 struct ocp_resource *r, *table;2681 int err = 0;2682 2683 table = (struct ocp_resource *)driver_data;2684 for (r = table; r->setup; r++) {2685 if (!ptp_ocp_allow_irq(bp, r))2686 continue;2687 err = r->setup(bp, r);2688 if (err) {2689 dev_err(&bp->pdev->dev,2690 "Could not register %s: err %d\n",2691 r->name, err);2692 break;2693 }2694 }2695 return err;2696}2697 2698static void2699ptp_ocp_art_sma_init(struct ptp_ocp *bp)2700{2701 struct dpll_pin_properties prop = {2702 .board_label = NULL,2703 .type = DPLL_PIN_TYPE_EXT,2704 .capabilities = 0,2705 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),2706 .freq_supported = ptp_ocp_sma_freq,2707 2708 };2709 u32 reg;2710 int i;2711 2712 /* defaults */2713 bp->sma[0].mode = SMA_MODE_IN;2714 bp->sma[1].mode = SMA_MODE_IN;2715 bp->sma[2].mode = SMA_MODE_OUT;2716 bp->sma[3].mode = SMA_MODE_OUT;2717 2718 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */2719 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */2720 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */2721 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */2722 2723 for (i = 0; i < OCP_SMA_NUM; i++) {2724 /* If no SMA map, the pin functions and directions are fixed. */2725 bp->sma[i].dpll_prop = prop;2726 bp->sma[i].dpll_prop.board_label =2727 bp->ptp_info.pin_config[i].name;2728 if (!bp->art_sma) {2729 bp->sma[i].fixed_fcn = true;2730 bp->sma[i].fixed_dir = true;2731 continue;2732 }2733 reg = ioread32(&bp->art_sma->map[i].gpio);2734 2735 switch (reg & 0xff) {2736 case 0:2737 bp->sma[i].fixed_fcn = true;2738 bp->sma[i].fixed_dir = true;2739 break;2740 case 1:2741 case 8:2742 bp->sma[i].mode = SMA_MODE_IN;2743 bp->sma[i].dpll_prop.capabilities =2744 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;2745 break;2746 default:2747 bp->sma[i].mode = SMA_MODE_OUT;2748 bp->sma[i].dpll_prop.capabilities =2749 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;2750 break;2751 }2752 }2753}2754 2755static u322756ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)2757{2758 if (bp->sma[sma_nr - 1].fixed_fcn)2759 return bp->sma[sma_nr - 1].default_fcn;2760 2761 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;2762}2763 2764/* note: store 0 is considered invalid. */2765static int2766ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)2767{2768 unsigned long flags;2769 u32 __iomem *gpio;2770 int err = 0;2771 u32 reg;2772 2773 val &= SMA_SELECT_MASK;2774 if (hweight32(val) > 1)2775 return -EINVAL;2776 2777 gpio = &bp->art_sma->map[sma_nr - 1].gpio;2778 2779 spin_lock_irqsave(&bp->lock, flags);2780 reg = ioread32(gpio);2781 if (((reg >> 16) & val) == 0) {2782 err = -EOPNOTSUPP;2783 } else {2784 reg = (reg & 0xff00) | (val & 0xff);2785 iowrite32(reg, gpio);2786 }2787 spin_unlock_irqrestore(&bp->lock, flags);2788 2789 return err;2790}2791 2792static const struct ocp_sma_op ocp_art_sma_op = {2793 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },2794 .init = ptp_ocp_art_sma_init,2795 .get = ptp_ocp_art_sma_get,2796 .set_inputs = ptp_ocp_art_sma_set,2797 .set_output = ptp_ocp_art_sma_set,2798};2799 2800/* ART specific board initializers; last "resource" registered. */2801static int2802ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)2803{2804 int err;2805 2806 bp->flash_start = 0x1000000;2807 bp->eeprom_map = art_eeprom_map;2808 bp->fw_cap = OCP_CAP_BASIC;2809 bp->fw_version = ioread32(&bp->reg->version);2810 bp->fw_tag = 2;2811 bp->sma_op = &ocp_art_sma_op;2812 2813 /* Enable MAC serial port during initialisation */2814 iowrite32(1, &bp->board_config->mro50_serial_activate);2815 2816 err = ptp_ocp_set_pins(bp);2817 if (err)2818 return err;2819 ptp_ocp_sma_init(bp);2820 2821 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);2822 if (err)2823 return err;2824 2825 return ptp_ocp_init_clock(bp, r->extra);2826}2827 2828/* ADVA specific board initializers; last "resource" registered. */2829static int2830ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r)2831{2832 int err;2833 u32 version;2834 2835 bp->flash_start = 0xA00000;2836 bp->eeprom_map = fb_eeprom_map;2837 bp->sma_op = &ocp_adva_sma_op;2838 2839 version = ioread32(&bp->image->version);2840 /* if lower 16 bits are empty, this is the fw loader. */2841 if ((version & 0xffff) == 0) {2842 version = version >> 16;2843 bp->fw_loader = true;2844 }2845 bp->fw_tag = 3;2846 bp->fw_version = version & 0xffff;2847 bp->fw_cap = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ;2848 2849 ptp_ocp_tod_init(bp);2850 ptp_ocp_nmea_out_init(bp);2851 ptp_ocp_signal_init(bp);2852 2853 err = ptp_ocp_attr_group_add(bp, adva_timecard_groups);2854 if (err)2855 return err;2856 2857 err = ptp_ocp_set_pins(bp);2858 if (err)2859 return err;2860 ptp_ocp_sma_init(bp);2861 2862 return ptp_ocp_init_clock(bp, r->extra);2863}2864 2865static ssize_t2866ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,2867 int def_val)2868{2869 const char *name;2870 ssize_t count;2871 2872 count = sysfs_emit(buf, "OUT: ");2873 name = ptp_ocp_select_name_from_val(tbl, val);2874 if (!name)2875 name = ptp_ocp_select_name_from_val(tbl, def_val);2876 count += sysfs_emit_at(buf, count, "%s\n", name);2877 return count;2878}2879 2880static ssize_t2881ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,2882 int def_val)2883{2884 const char *name;2885 ssize_t count;2886 int i;2887 2888 count = sysfs_emit(buf, "IN: ");2889 for (i = 0; tbl[i].name; i++) {2890 if (val & tbl[i].value) {2891 name = tbl[i].name;2892 count += sysfs_emit_at(buf, count, "%s ", name);2893 }2894 }2895 if (!val && def_val >= 0) {2896 name = ptp_ocp_select_name_from_val(tbl, def_val);2897 count += sysfs_emit_at(buf, count, "%s ", name);2898 }2899 if (count)2900 count--;2901 count += sysfs_emit_at(buf, count, "\n");2902 return count;2903}2904 2905static int2906sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,2907 enum ptp_ocp_sma_mode *mode)2908{2909 int idx, count, dir;2910 char **argv;2911 int ret;2912 2913 argv = argv_split(GFP_KERNEL, buf, &count);2914 if (!argv)2915 return -ENOMEM;2916 2917 ret = -EINVAL;2918 if (!count)2919 goto out;2920 2921 idx = 0;2922 dir = *mode == SMA_MODE_IN ? 0 : 1;2923 if (!strcasecmp("IN:", argv[0])) {2924 dir = 0;2925 idx++;2926 }2927 if (!strcasecmp("OUT:", argv[0])) {2928 dir = 1;2929 idx++;2930 }2931 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;2932 2933 ret = 0;2934 for (; idx < count; idx++)2935 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);2936 if (ret < 0)2937 ret = -EINVAL;2938 2939out:2940 argv_free(argv);2941 return ret;2942}2943 2944static ssize_t2945ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,2946 int default_in_val, int default_out_val)2947{2948 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];2949 const struct ocp_selector * const *tbl;2950 u32 val;2951 2952 tbl = bp->sma_op->tbl;2953 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;2954 2955 if (sma->mode == SMA_MODE_IN) {2956 if (sma->disabled)2957 val = SMA_DISABLE;2958 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);2959 }2960 2961 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);2962}2963 2964static ssize_t2965sma1_show(struct device *dev, struct device_attribute *attr, char *buf)2966{2967 struct ptp_ocp *bp = dev_get_drvdata(dev);2968 2969 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);2970}2971 2972static ssize_t2973sma2_show(struct device *dev, struct device_attribute *attr, char *buf)2974{2975 struct ptp_ocp *bp = dev_get_drvdata(dev);2976 2977 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);2978}2979 2980static ssize_t2981sma3_show(struct device *dev, struct device_attribute *attr, char *buf)2982{2983 struct ptp_ocp *bp = dev_get_drvdata(dev);2984 2985 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);2986}2987 2988static ssize_t2989sma4_show(struct device *dev, struct device_attribute *attr, char *buf)2990{2991 struct ptp_ocp *bp = dev_get_drvdata(dev);2992 2993 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);2994}2995 2996static int2997ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)2998{2999 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];3000 3001 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))3002 return -EOPNOTSUPP;3003 3004 if (sma->fixed_fcn) {3005 if (val != sma->default_fcn)3006 return -EOPNOTSUPP;3007 return 0;3008 }3009 3010 sma->disabled = !!(val & SMA_DISABLE);3011 3012 if (mode != sma->mode) {3013 if (mode == SMA_MODE_IN)3014 ptp_ocp_sma_set_output(bp, sma_nr, 0);3015 else3016 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);3017 sma->mode = mode;3018 }3019 3020 if (!sma->fixed_dir)3021 val |= SMA_ENABLE; /* add enable bit */3022 3023 if (sma->disabled)3024 val = 0;3025 3026 if (mode == SMA_MODE_IN)3027 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);3028 else3029 val = ptp_ocp_sma_set_output(bp, sma_nr, val);3030 3031 return val;3032}3033 3034static int3035ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)3036{3037 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];3038 enum ptp_ocp_sma_mode mode;3039 int val;3040 3041 mode = sma->mode;3042 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);3043 if (val < 0)3044 return val;3045 return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);3046}3047 3048static ssize_t3049sma1_store(struct device *dev, struct device_attribute *attr,3050 const char *buf, size_t count)3051{3052 struct ptp_ocp *bp = dev_get_drvdata(dev);3053 int err;3054 3055 err = ptp_ocp_sma_store(bp, buf, 1);3056 return err ? err : count;3057}3058 3059static ssize_t3060sma2_store(struct device *dev, struct device_attribute *attr,3061 const char *buf, size_t count)3062{3063 struct ptp_ocp *bp = dev_get_drvdata(dev);3064 int err;3065 3066 err = ptp_ocp_sma_store(bp, buf, 2);3067 return err ? err : count;3068}3069 3070static ssize_t3071sma3_store(struct device *dev, struct device_attribute *attr,3072 const char *buf, size_t count)3073{3074 struct ptp_ocp *bp = dev_get_drvdata(dev);3075 int err;3076 3077 err = ptp_ocp_sma_store(bp, buf, 3);3078 return err ? err : count;3079}3080 3081static ssize_t3082sma4_store(struct device *dev, struct device_attribute *attr,3083 const char *buf, size_t count)3084{3085 struct ptp_ocp *bp = dev_get_drvdata(dev);3086 int err;3087 3088 err = ptp_ocp_sma_store(bp, buf, 4);3089 return err ? err : count;3090}3091static DEVICE_ATTR_RW(sma1);3092static DEVICE_ATTR_RW(sma2);3093static DEVICE_ATTR_RW(sma3);3094static DEVICE_ATTR_RW(sma4);3095 3096static ssize_t3097available_sma_inputs_show(struct device *dev,3098 struct device_attribute *attr, char *buf)3099{3100 struct ptp_ocp *bp = dev_get_drvdata(dev);3101 3102 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);3103}3104static DEVICE_ATTR_RO(available_sma_inputs);3105 3106static ssize_t3107available_sma_outputs_show(struct device *dev,3108 struct device_attribute *attr, char *buf)3109{3110 struct ptp_ocp *bp = dev_get_drvdata(dev);3111 3112 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);3113}3114static DEVICE_ATTR_RO(available_sma_outputs);3115 3116#define EXT_ATTR_RO(_group, _name, _val) \3117 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \3118 { __ATTR_RO(_name), (void *)_val }3119#define EXT_ATTR_RW(_group, _name, _val) \3120 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \3121 { __ATTR_RW(_name), (void *)_val }3122#define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)3123 3124/* period [duty [phase [polarity]]] */3125static ssize_t3126signal_store(struct device *dev, struct device_attribute *attr,3127 const char *buf, size_t count)3128{3129 struct dev_ext_attribute *ea = to_ext_attr(attr);3130 struct ptp_ocp *bp = dev_get_drvdata(dev);3131 struct ptp_ocp_signal s = { };3132 int gen = (uintptr_t)ea->var;3133 int argc, err;3134 char **argv;3135 3136 argv = argv_split(GFP_KERNEL, buf, &argc);3137 if (!argv)3138 return -ENOMEM;3139 3140 err = -EINVAL;3141 s.duty = bp->signal[gen].duty;3142 s.phase = bp->signal[gen].phase;3143 s.period = bp->signal[gen].period;3144 s.polarity = bp->signal[gen].polarity;3145 3146 switch (argc) {3147 case 4:3148 argc--;3149 err = kstrtobool(argv[argc], &s.polarity);3150 if (err)3151 goto out;3152 fallthrough;3153 case 3:3154 argc--;3155 err = kstrtou64(argv[argc], 0, &s.phase);3156 if (err)3157 goto out;3158 fallthrough;3159 case 2:3160 argc--;3161 err = kstrtoint(argv[argc], 0, &s.duty);3162 if (err)3163 goto out;3164 fallthrough;3165 case 1:3166 argc--;3167 err = kstrtou64(argv[argc], 0, &s.period);3168 if (err)3169 goto out;3170 break;3171 default:3172 goto out;3173 }3174 3175 err = ptp_ocp_signal_set(bp, gen, &s);3176 if (err)3177 goto out;3178 3179 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);3180 3181out:3182 argv_free(argv);3183 return err ? err : count;3184}3185 3186static ssize_t3187signal_show(struct device *dev, struct device_attribute *attr, char *buf)3188{3189 struct dev_ext_attribute *ea = to_ext_attr(attr);3190 struct ptp_ocp *bp = dev_get_drvdata(dev);3191 struct ptp_ocp_signal *signal;3192 struct timespec64 ts;3193 ssize_t count;3194 int i;3195 3196 i = (uintptr_t)ea->var;3197 signal = &bp->signal[i];3198 3199 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,3200 signal->duty, signal->phase, signal->polarity);3201 3202 ts = ktime_to_timespec64(signal->start);3203 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);3204 3205 return count;3206}3207static EXT_ATTR_RW(signal, signal, 0);3208static EXT_ATTR_RW(signal, signal, 1);3209static EXT_ATTR_RW(signal, signal, 2);3210static EXT_ATTR_RW(signal, signal, 3);3211 3212static ssize_t3213duty_show(struct device *dev, struct device_attribute *attr, char *buf)3214{3215 struct dev_ext_attribute *ea = to_ext_attr(attr);3216 struct ptp_ocp *bp = dev_get_drvdata(dev);3217 int i = (uintptr_t)ea->var;3218 3219 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);3220}3221static EXT_ATTR_RO(signal, duty, 0);3222static EXT_ATTR_RO(signal, duty, 1);3223static EXT_ATTR_RO(signal, duty, 2);3224static EXT_ATTR_RO(signal, duty, 3);3225 3226static ssize_t3227period_show(struct device *dev, struct device_attribute *attr, char *buf)3228{3229 struct dev_ext_attribute *ea = to_ext_attr(attr);3230 struct ptp_ocp *bp = dev_get_drvdata(dev);3231 int i = (uintptr_t)ea->var;3232 3233 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);3234}3235static EXT_ATTR_RO(signal, period, 0);3236static EXT_ATTR_RO(signal, period, 1);3237static EXT_ATTR_RO(signal, period, 2);3238static EXT_ATTR_RO(signal, period, 3);3239 3240static ssize_t3241phase_show(struct device *dev, struct device_attribute *attr, char *buf)3242{3243 struct dev_ext_attribute *ea = to_ext_attr(attr);3244 struct ptp_ocp *bp = dev_get_drvdata(dev);3245 int i = (uintptr_t)ea->var;3246 3247 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);3248}3249static EXT_ATTR_RO(signal, phase, 0);3250static EXT_ATTR_RO(signal, phase, 1);3251static EXT_ATTR_RO(signal, phase, 2);3252static EXT_ATTR_RO(signal, phase, 3);3253 3254static ssize_t3255polarity_show(struct device *dev, struct device_attribute *attr,3256 char *buf)3257{3258 struct dev_ext_attribute *ea = to_ext_attr(attr);3259 struct ptp_ocp *bp = dev_get_drvdata(dev);3260 int i = (uintptr_t)ea->var;3261 3262 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);3263}3264static EXT_ATTR_RO(signal, polarity, 0);3265static EXT_ATTR_RO(signal, polarity, 1);3266static EXT_ATTR_RO(signal, polarity, 2);3267static EXT_ATTR_RO(signal, polarity, 3);3268 3269static ssize_t3270running_show(struct device *dev, struct device_attribute *attr, char *buf)3271{3272 struct dev_ext_attribute *ea = to_ext_attr(attr);3273 struct ptp_ocp *bp = dev_get_drvdata(dev);3274 int i = (uintptr_t)ea->var;3275 3276 return sysfs_emit(buf, "%d\n", bp->signal[i].running);3277}3278static EXT_ATTR_RO(signal, running, 0);3279static EXT_ATTR_RO(signal, running, 1);3280static EXT_ATTR_RO(signal, running, 2);3281static EXT_ATTR_RO(signal, running, 3);3282 3283static ssize_t3284start_show(struct device *dev, struct device_attribute *attr, char *buf)3285{3286 struct dev_ext_attribute *ea = to_ext_attr(attr);3287 struct ptp_ocp *bp = dev_get_drvdata(dev);3288 int i = (uintptr_t)ea->var;3289 struct timespec64 ts;3290 3291 ts = ktime_to_timespec64(bp->signal[i].start);3292 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);3293}3294static EXT_ATTR_RO(signal, start, 0);3295static EXT_ATTR_RO(signal, start, 1);3296static EXT_ATTR_RO(signal, start, 2);3297static EXT_ATTR_RO(signal, start, 3);3298 3299static ssize_t3300seconds_store(struct device *dev, struct device_attribute *attr,3301 const char *buf, size_t count)3302{3303 struct dev_ext_attribute *ea = to_ext_attr(attr);3304 struct ptp_ocp *bp = dev_get_drvdata(dev);3305 int idx = (uintptr_t)ea->var;3306 u32 val;3307 int err;3308 3309 err = kstrtou32(buf, 0, &val);3310 if (err)3311 return err;3312 if (val > 0xff)3313 return -EINVAL;3314 3315 if (val)3316 val = (val << 8) | 0x1;3317 3318 iowrite32(val, &bp->freq_in[idx]->ctrl);3319 3320 return count;3321}3322 3323static ssize_t3324seconds_show(struct device *dev, struct device_attribute *attr, char *buf)3325{3326 struct dev_ext_attribute *ea = to_ext_attr(attr);3327 struct ptp_ocp *bp = dev_get_drvdata(dev);3328 int idx = (uintptr_t)ea->var;3329 u32 val;3330 3331 val = ioread32(&bp->freq_in[idx]->ctrl);3332 if (val & 1)3333 val = (val >> 8) & 0xff;3334 else3335 val = 0;3336 3337 return sysfs_emit(buf, "%u\n", val);3338}3339static EXT_ATTR_RW(freq, seconds, 0);3340static EXT_ATTR_RW(freq, seconds, 1);3341static EXT_ATTR_RW(freq, seconds, 2);3342static EXT_ATTR_RW(freq, seconds, 3);3343 3344static ssize_t3345frequency_show(struct device *dev, struct device_attribute *attr, char *buf)3346{3347 struct dev_ext_attribute *ea = to_ext_attr(attr);3348 struct ptp_ocp *bp = dev_get_drvdata(dev);3349 int idx = (uintptr_t)ea->var;3350 u32 val;3351 3352 val = ioread32(&bp->freq_in[idx]->status);3353 if (val & FREQ_STATUS_ERROR)3354 return sysfs_emit(buf, "error\n");3355 if (val & FREQ_STATUS_OVERRUN)3356 return sysfs_emit(buf, "overrun\n");3357 if (val & FREQ_STATUS_VALID)3358 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);3359 return 0;3360}3361static EXT_ATTR_RO(freq, frequency, 0);3362static EXT_ATTR_RO(freq, frequency, 1);3363static EXT_ATTR_RO(freq, frequency, 2);3364static EXT_ATTR_RO(freq, frequency, 3);3365 3366static ssize_t3367ptp_ocp_tty_show(struct device *dev, struct device_attribute *attr, char *buf)3368{3369 struct dev_ext_attribute *ea = to_ext_attr(attr);3370 struct ptp_ocp *bp = dev_get_drvdata(dev);3371 3372 return sysfs_emit(buf, "ttyS%d", bp->port[(uintptr_t)ea->var].line);3373}3374 3375static umode_t3376ptp_ocp_timecard_tty_is_visible(struct kobject *kobj, struct attribute *attr, int n)3377{3378 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));3379 struct ptp_ocp_serial_port *port;3380 struct device_attribute *dattr;3381 struct dev_ext_attribute *ea;3382 3383 if (strncmp(attr->name, "tty", 3))3384 return attr->mode;3385 3386 dattr = container_of(attr, struct device_attribute, attr);3387 ea = container_of(dattr, struct dev_ext_attribute, attr);3388 port = &bp->port[(uintptr_t)ea->var];3389 return port->line == -1 ? 0 : 0444;3390}3391 3392#define EXT_TTY_ATTR_RO(_name, _val) \3393 struct dev_ext_attribute dev_attr_tty##_name = \3394 { __ATTR(tty##_name, 0444, ptp_ocp_tty_show, NULL), (void *)_val }3395 3396static EXT_TTY_ATTR_RO(GNSS, PORT_GNSS);3397static EXT_TTY_ATTR_RO(GNSS2, PORT_GNSS2);3398static EXT_TTY_ATTR_RO(MAC, PORT_MAC);3399static EXT_TTY_ATTR_RO(NMEA, PORT_NMEA);3400static struct attribute *ptp_ocp_timecard_tty_attrs[] = {3401 &dev_attr_ttyGNSS.attr.attr,3402 &dev_attr_ttyGNSS2.attr.attr,3403 &dev_attr_ttyMAC.attr.attr,3404 &dev_attr_ttyNMEA.attr.attr,3405 NULL,3406};3407 3408static const struct attribute_group ptp_ocp_timecard_tty_group = {3409 .name = "tty",3410 .attrs = ptp_ocp_timecard_tty_attrs,3411 .is_visible = ptp_ocp_timecard_tty_is_visible,3412};3413 3414static ssize_t3415serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)3416{3417 struct ptp_ocp *bp = dev_get_drvdata(dev);3418 3419 if (!bp->has_eeprom_data)3420 ptp_ocp_read_eeprom(bp);3421 3422 return sysfs_emit(buf, "%pM\n", bp->serial);3423}3424static DEVICE_ATTR_RO(serialnum);3425 3426static ssize_t3427gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)3428{3429 struct ptp_ocp *bp = dev_get_drvdata(dev);3430 ssize_t ret;3431 3432 if (bp->gnss_lost)3433 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);3434 else3435 ret = sysfs_emit(buf, "SYNC\n");3436 3437 return ret;3438}3439static DEVICE_ATTR_RO(gnss_sync);3440 3441static ssize_t3442utc_tai_offset_show(struct device *dev,3443 struct device_attribute *attr, char *buf)3444{3445 struct ptp_ocp *bp = dev_get_drvdata(dev);3446 3447 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);3448}3449 3450static ssize_t3451utc_tai_offset_store(struct device *dev,3452 struct device_attribute *attr,3453 const char *buf, size_t count)3454{3455 struct ptp_ocp *bp = dev_get_drvdata(dev);3456 int err;3457 u32 val;3458 3459 err = kstrtou32(buf, 0, &val);3460 if (err)3461 return err;3462 3463 ptp_ocp_utc_distribute(bp, val);3464 3465 return count;3466}3467static DEVICE_ATTR_RW(utc_tai_offset);3468 3469static ssize_t3470ts_window_adjust_show(struct device *dev,3471 struct device_attribute *attr, char *buf)3472{3473 struct ptp_ocp *bp = dev_get_drvdata(dev);3474 3475 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);3476}3477 3478static ssize_t3479ts_window_adjust_store(struct device *dev,3480 struct device_attribute *attr,3481 const char *buf, size_t count)3482{3483 struct ptp_ocp *bp = dev_get_drvdata(dev);3484 int err;3485 u32 val;3486 3487 err = kstrtou32(buf, 0, &val);3488 if (err)3489 return err;3490 3491 bp->ts_window_adjust = val;3492 3493 return count;3494}3495static DEVICE_ATTR_RW(ts_window_adjust);3496 3497static ssize_t3498irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)3499{3500 struct ptp_ocp *bp = dev_get_drvdata(dev);3501 u32 val;3502 3503 val = ioread32(&bp->irig_out->ctrl);3504 val = (val >> 16) & 0x07;3505 return sysfs_emit(buf, "%d\n", val);3506}3507 3508static ssize_t3509irig_b_mode_store(struct device *dev,3510 struct device_attribute *attr,3511 const char *buf, size_t count)3512{3513 struct ptp_ocp *bp = dev_get_drvdata(dev);3514 unsigned long flags;3515 int err;3516 u32 reg;3517 u8 val;3518 3519 err = kstrtou8(buf, 0, &val);3520 if (err)3521 return err;3522 if (val > 7)3523 return -EINVAL;3524 3525 reg = ((val & 0x7) << 16);3526 3527 spin_lock_irqsave(&bp->lock, flags);3528 iowrite32(0, &bp->irig_out->ctrl); /* disable */3529 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */3530 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);3531 spin_unlock_irqrestore(&bp->lock, flags);3532 3533 return count;3534}3535static DEVICE_ATTR_RW(irig_b_mode);3536 3537static ssize_t3538clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)3539{3540 struct ptp_ocp *bp = dev_get_drvdata(dev);3541 const char *p;3542 u32 select;3543 3544 select = ioread32(&bp->reg->select);3545 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);3546 3547 return sysfs_emit(buf, "%s\n", p);3548}3549 3550static ssize_t3551clock_source_store(struct device *dev, struct device_attribute *attr,3552 const char *buf, size_t count)3553{3554 struct ptp_ocp *bp = dev_get_drvdata(dev);3555 unsigned long flags;3556 int val;3557 3558 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);3559 if (val < 0)3560 return val;3561 3562 spin_lock_irqsave(&bp->lock, flags);3563 iowrite32(val, &bp->reg->select);3564 spin_unlock_irqrestore(&bp->lock, flags);3565 3566 return count;3567}3568static DEVICE_ATTR_RW(clock_source);3569 3570static ssize_t3571available_clock_sources_show(struct device *dev,3572 struct device_attribute *attr, char *buf)3573{3574 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);3575}3576static DEVICE_ATTR_RO(available_clock_sources);3577 3578static ssize_t3579clock_status_drift_show(struct device *dev,3580 struct device_attribute *attr, char *buf)3581{3582 struct ptp_ocp *bp = dev_get_drvdata(dev);3583 u32 val;3584 int res;3585 3586 val = ioread32(&bp->reg->status_drift);3587 res = (val & ~INT_MAX) ? -1 : 1;3588 res *= (val & INT_MAX);3589 return sysfs_emit(buf, "%d\n", res);3590}3591static DEVICE_ATTR_RO(clock_status_drift);3592 3593static ssize_t3594clock_status_offset_show(struct device *dev,3595 struct device_attribute *attr, char *buf)3596{3597 struct ptp_ocp *bp = dev_get_drvdata(dev);3598 u32 val;3599 int res;3600 3601 val = ioread32(&bp->reg->status_offset);3602 res = (val & ~INT_MAX) ? -1 : 1;3603 res *= (val & INT_MAX);3604 return sysfs_emit(buf, "%d\n", res);3605}3606static DEVICE_ATTR_RO(clock_status_offset);3607 3608static ssize_t3609tod_correction_show(struct device *dev,3610 struct device_attribute *attr, char *buf)3611{3612 struct ptp_ocp *bp = dev_get_drvdata(dev);3613 u32 val;3614 int res;3615 3616 val = ioread32(&bp->tod->adj_sec);3617 res = (val & ~INT_MAX) ? -1 : 1;3618 res *= (val & INT_MAX);3619 return sysfs_emit(buf, "%d\n", res);3620}3621 3622static ssize_t3623tod_correction_store(struct device *dev, struct device_attribute *attr,3624 const char *buf, size_t count)3625{3626 struct ptp_ocp *bp = dev_get_drvdata(dev);3627 unsigned long flags;3628 int err, res;3629 u32 val = 0;3630 3631 err = kstrtos32(buf, 0, &res);3632 if (err)3633 return err;3634 if (res < 0) {3635 res *= -1;3636 val |= BIT(31);3637 }3638 val |= res;3639 3640 spin_lock_irqsave(&bp->lock, flags);3641 iowrite32(val, &bp->tod->adj_sec);3642 spin_unlock_irqrestore(&bp->lock, flags);3643 3644 return count;3645}3646static DEVICE_ATTR_RW(tod_correction);3647 3648#define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \3649 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \3650 &dev_attr_signal##_nr##_signal.attr.attr, \3651 &dev_attr_signal##_nr##_duty.attr.attr, \3652 &dev_attr_signal##_nr##_phase.attr.attr, \3653 &dev_attr_signal##_nr##_period.attr.attr, \3654 &dev_attr_signal##_nr##_polarity.attr.attr, \3655 &dev_attr_signal##_nr##_running.attr.attr, \3656 &dev_attr_signal##_nr##_start.attr.attr, \3657 NULL, \3658 }3659 3660#define DEVICE_SIGNAL_GROUP(_name, _nr) \3661 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \3662 static const struct attribute_group \3663 fb_timecard_signal##_nr##_group = { \3664 .name = #_name, \3665 .attrs = fb_timecard_signal##_nr##_attrs, \3666}3667 3668DEVICE_SIGNAL_GROUP(gen1, 0);3669DEVICE_SIGNAL_GROUP(gen2, 1);3670DEVICE_SIGNAL_GROUP(gen3, 2);3671DEVICE_SIGNAL_GROUP(gen4, 3);3672 3673#define _DEVICE_FREQ_GROUP_ATTRS(_nr) \3674 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \3675 &dev_attr_freq##_nr##_seconds.attr.attr, \3676 &dev_attr_freq##_nr##_frequency.attr.attr, \3677 NULL, \3678 }3679 3680#define DEVICE_FREQ_GROUP(_name, _nr) \3681 _DEVICE_FREQ_GROUP_ATTRS(_nr); \3682 static const struct attribute_group \3683 fb_timecard_freq##_nr##_group = { \3684 .name = #_name, \3685 .attrs = fb_timecard_freq##_nr##_attrs, \3686}3687 3688DEVICE_FREQ_GROUP(freq1, 0);3689DEVICE_FREQ_GROUP(freq2, 1);3690DEVICE_FREQ_GROUP(freq3, 2);3691DEVICE_FREQ_GROUP(freq4, 3);3692 3693static ssize_t3694disciplining_config_read(struct file *filp, struct kobject *kobj,3695 struct bin_attribute *bin_attr, char *buf,3696 loff_t off, size_t count)3697{3698 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));3699 size_t size = OCP_ART_CONFIG_SIZE;3700 struct nvmem_device *nvmem;3701 ssize_t err;3702 3703 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);3704 if (IS_ERR(nvmem))3705 return PTR_ERR(nvmem);3706 3707 if (off > size) {3708 err = 0;3709 goto out;3710 }3711 3712 if (off + count > size)3713 count = size - off;3714 3715 // the configuration is in the very beginning of the EEPROM3716 err = nvmem_device_read(nvmem, off, count, buf);3717 if (err != count) {3718 err = -EFAULT;3719 goto out;3720 }3721 3722out:3723 ptp_ocp_nvmem_device_put(&nvmem);3724 3725 return err;3726}3727 3728static ssize_t3729disciplining_config_write(struct file *filp, struct kobject *kobj,3730 struct bin_attribute *bin_attr, char *buf,3731 loff_t off, size_t count)3732{3733 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));3734 struct nvmem_device *nvmem;3735 ssize_t err;3736 3737 /* Allow write of the whole area only */3738 if (off || count != OCP_ART_CONFIG_SIZE)3739 return -EFAULT;3740 3741 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);3742 if (IS_ERR(nvmem))3743 return PTR_ERR(nvmem);3744 3745 err = nvmem_device_write(nvmem, 0x00, count, buf);3746 if (err != count)3747 err = -EFAULT;3748 3749 ptp_ocp_nvmem_device_put(&nvmem);3750 3751 return err;3752}3753static BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);3754 3755static ssize_t3756temperature_table_read(struct file *filp, struct kobject *kobj,3757 struct bin_attribute *bin_attr, char *buf,3758 loff_t off, size_t count)3759{3760 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));3761 size_t size = OCP_ART_TEMP_TABLE_SIZE;3762 struct nvmem_device *nvmem;3763 ssize_t err;3764 3765 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);3766 if (IS_ERR(nvmem))3767 return PTR_ERR(nvmem);3768 3769 if (off > size) {3770 err = 0;3771 goto out;3772 }3773 3774 if (off + count > size)3775 count = size - off;3776 3777 // the configuration is in the very beginning of the EEPROM3778 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);3779 if (err != count) {3780 err = -EFAULT;3781 goto out;3782 }3783 3784out:3785 ptp_ocp_nvmem_device_put(&nvmem);3786 3787 return err;3788}3789 3790static ssize_t3791temperature_table_write(struct file *filp, struct kobject *kobj,3792 struct bin_attribute *bin_attr, char *buf,3793 loff_t off, size_t count)3794{3795 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));3796 struct nvmem_device *nvmem;3797 ssize_t err;3798 3799 /* Allow write of the whole area only */3800 if (off || count != OCP_ART_TEMP_TABLE_SIZE)3801 return -EFAULT;3802 3803 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);3804 if (IS_ERR(nvmem))3805 return PTR_ERR(nvmem);3806 3807 err = nvmem_device_write(nvmem, 0x90, count, buf);3808 if (err != count)3809 err = -EFAULT;3810 3811 ptp_ocp_nvmem_device_put(&nvmem);3812 3813 return err;3814}3815static BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);3816 3817static struct attribute *fb_timecard_attrs[] = {3818 &dev_attr_serialnum.attr,3819 &dev_attr_gnss_sync.attr,3820 &dev_attr_clock_source.attr,3821 &dev_attr_available_clock_sources.attr,3822 &dev_attr_sma1.attr,3823 &dev_attr_sma2.attr,3824 &dev_attr_sma3.attr,3825 &dev_attr_sma4.attr,3826 &dev_attr_available_sma_inputs.attr,3827 &dev_attr_available_sma_outputs.attr,3828 &dev_attr_clock_status_drift.attr,3829 &dev_attr_clock_status_offset.attr,3830 &dev_attr_irig_b_mode.attr,3831 &dev_attr_utc_tai_offset.attr,3832 &dev_attr_ts_window_adjust.attr,3833 &dev_attr_tod_correction.attr,3834 NULL,3835};3836 3837static const struct attribute_group fb_timecard_group = {3838 .attrs = fb_timecard_attrs,3839};3840 3841static const struct ocp_attr_group fb_timecard_groups[] = {3842 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },3843 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },3844 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },3845 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },3846 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },3847 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },3848 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },3849 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },3850 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },3851 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },3852 { },3853};3854 3855static struct attribute *art_timecard_attrs[] = {3856 &dev_attr_serialnum.attr,3857 &dev_attr_clock_source.attr,3858 &dev_attr_available_clock_sources.attr,3859 &dev_attr_utc_tai_offset.attr,3860 &dev_attr_ts_window_adjust.attr,3861 &dev_attr_sma1.attr,3862 &dev_attr_sma2.attr,3863 &dev_attr_sma3.attr,3864 &dev_attr_sma4.attr,3865 &dev_attr_available_sma_inputs.attr,3866 &dev_attr_available_sma_outputs.attr,3867 NULL,3868};3869 3870static struct bin_attribute *bin_art_timecard_attrs[] = {3871 &bin_attr_disciplining_config,3872 &bin_attr_temperature_table,3873 NULL,3874};3875 3876static const struct attribute_group art_timecard_group = {3877 .attrs = art_timecard_attrs,3878 .bin_attrs = bin_art_timecard_attrs,3879};3880 3881static const struct ocp_attr_group art_timecard_groups[] = {3882 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },3883 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },3884 { },3885};3886 3887static struct attribute *adva_timecard_attrs[] = {3888 &dev_attr_serialnum.attr,3889 &dev_attr_gnss_sync.attr,3890 &dev_attr_clock_source.attr,3891 &dev_attr_available_clock_sources.attr,3892 &dev_attr_sma1.attr,3893 &dev_attr_sma2.attr,3894 &dev_attr_sma3.attr,3895 &dev_attr_sma4.attr,3896 &dev_attr_available_sma_inputs.attr,3897 &dev_attr_available_sma_outputs.attr,3898 &dev_attr_clock_status_drift.attr,3899 &dev_attr_clock_status_offset.attr,3900 &dev_attr_ts_window_adjust.attr,3901 &dev_attr_tod_correction.attr,3902 NULL,3903};3904 3905static const struct attribute_group adva_timecard_group = {3906 .attrs = adva_timecard_attrs,3907};3908 3909static const struct ocp_attr_group adva_timecard_groups[] = {3910 { .cap = OCP_CAP_BASIC, .group = &adva_timecard_group },3911 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },3912 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },3913 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },3914 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },3915 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },3916 { },3917};3918 3919static void3920gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,3921 const char *def)3922{3923 int i;3924 3925 for (i = 0; i < 4; i++) {3926 if (bp->sma[i].mode != SMA_MODE_IN)3927 continue;3928 if (map[i][0] & (1 << bit)) {3929 sprintf(buf, "sma%d", i + 1);3930 return;3931 }3932 }3933 if (!def)3934 def = "----";3935 strcpy(buf, def);3936}3937 3938static void3939gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)3940{3941 char *ans = buf;3942 int i;3943 3944 strcpy(ans, "----");3945 for (i = 0; i < 4; i++) {3946 if (bp->sma[i].mode != SMA_MODE_OUT)3947 continue;3948 if (map[i][1] & (1 << bit))3949 ans += sprintf(ans, "sma%d ", i + 1);3950 }3951}3952 3953static void3954_signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)3955{3956 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;3957 struct ptp_ocp_signal *signal = &bp->signal[nr];3958 char label[8];3959 bool on;3960 u32 val;3961 3962 if (!signal)3963 return;3964 3965 on = signal->running;3966 sprintf(label, "GEN%d", nr + 1);3967 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",3968 label, on ? " ON" : "OFF",3969 signal->period, signal->duty, signal->phase,3970 signal->polarity);3971 3972 val = ioread32(®->enable);3973 seq_printf(s, " [%x", val);3974 val = ioread32(®->status);3975 seq_printf(s, " %x]", val);3976 3977 seq_printf(s, " start:%llu\n", signal->start);3978}3979 3980static void3981_frequency_summary_show(struct seq_file *s, int nr,3982 struct frequency_reg __iomem *reg)3983{3984 char label[8];3985 bool on;3986 u32 val;3987 3988 if (!reg)3989 return;3990 3991 sprintf(label, "FREQ%d", nr + 1);3992 val = ioread32(®->ctrl);3993 on = val & 1;3994 val = (val >> 8) & 0xff;3995 seq_printf(s, "%7s: %s, sec:%u",3996 label,3997 on ? " ON" : "OFF",3998 val);3999 4000 val = ioread32(®->status);4001 if (val & FREQ_STATUS_ERROR)4002 seq_printf(s, ", error");4003 if (val & FREQ_STATUS_OVERRUN)4004 seq_printf(s, ", overrun");4005 if (val & FREQ_STATUS_VALID)4006 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);4007 seq_printf(s, " reg:%x\n", val);4008}4009 4010static int4011ptp_ocp_summary_show(struct seq_file *s, void *data)4012{4013 struct device *dev = s->private;4014 struct ptp_system_timestamp sts;4015 struct ts_reg __iomem *ts_reg;4016 char *buf, *src, *mac_src;4017 struct timespec64 ts;4018 struct ptp_ocp *bp;4019 u16 sma_val[4][2];4020 u32 ctrl, val;4021 bool on, map;4022 int i;4023 4024 buf = (char *)__get_free_page(GFP_KERNEL);4025 if (!buf)4026 return -ENOMEM;4027 4028 bp = dev_get_drvdata(dev);4029 4030 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));4031 for (i = 0; i < __PORT_COUNT; i++) {4032 if (bp->port[i].line != -1)4033 seq_printf(s, "%7s: /dev/ttyS%d\n", ptp_ocp_tty_port_name(i),4034 bp->port[i].line);4035 }4036 4037 memset(sma_val, 0xff, sizeof(sma_val));4038 if (bp->sma_map1) {4039 u32 reg;4040 4041 reg = ioread32(&bp->sma_map1->gpio1);4042 sma_val[0][0] = reg & 0xffff;4043 sma_val[1][0] = reg >> 16;4044 4045 reg = ioread32(&bp->sma_map1->gpio2);4046 sma_val[2][1] = reg & 0xffff;4047 sma_val[3][1] = reg >> 16;4048 4049 reg = ioread32(&bp->sma_map2->gpio1);4050 sma_val[2][0] = reg & 0xffff;4051 sma_val[3][0] = reg >> 16;4052 4053 reg = ioread32(&bp->sma_map2->gpio2);4054 sma_val[0][1] = reg & 0xffff;4055 sma_val[1][1] = reg >> 16;4056 }4057 4058 sma1_show(dev, NULL, buf);4059 seq_printf(s, " sma1: %04x,%04x %s",4060 sma_val[0][0], sma_val[0][1], buf);4061 4062 sma2_show(dev, NULL, buf);4063 seq_printf(s, " sma2: %04x,%04x %s",4064 sma_val[1][0], sma_val[1][1], buf);4065 4066 sma3_show(dev, NULL, buf);4067 seq_printf(s, " sma3: %04x,%04x %s",4068 sma_val[2][0], sma_val[2][1], buf);4069 4070 sma4_show(dev, NULL, buf);4071 seq_printf(s, " sma4: %04x,%04x %s",4072 sma_val[3][0], sma_val[3][1], buf);4073 4074 if (bp->ts0) {4075 ts_reg = bp->ts0->mem;4076 on = ioread32(&ts_reg->enable);4077 src = "GNSS1";4078 seq_printf(s, "%7s: %s, src: %s\n", "TS0",4079 on ? " ON" : "OFF", src);4080 }4081 4082 if (bp->ts1) {4083 ts_reg = bp->ts1->mem;4084 on = ioread32(&ts_reg->enable);4085 gpio_input_map(buf, bp, sma_val, 2, NULL);4086 seq_printf(s, "%7s: %s, src: %s\n", "TS1",4087 on ? " ON" : "OFF", buf);4088 }4089 4090 if (bp->ts2) {4091 ts_reg = bp->ts2->mem;4092 on = ioread32(&ts_reg->enable);4093 gpio_input_map(buf, bp, sma_val, 3, NULL);4094 seq_printf(s, "%7s: %s, src: %s\n", "TS2",4095 on ? " ON" : "OFF", buf);4096 }4097 4098 if (bp->ts3) {4099 ts_reg = bp->ts3->mem;4100 on = ioread32(&ts_reg->enable);4101 gpio_input_map(buf, bp, sma_val, 6, NULL);4102 seq_printf(s, "%7s: %s, src: %s\n", "TS3",4103 on ? " ON" : "OFF", buf);4104 }4105 4106 if (bp->ts4) {4107 ts_reg = bp->ts4->mem;4108 on = ioread32(&ts_reg->enable);4109 gpio_input_map(buf, bp, sma_val, 7, NULL);4110 seq_printf(s, "%7s: %s, src: %s\n", "TS4",4111 on ? " ON" : "OFF", buf);4112 }4113 4114 if (bp->pps) {4115 ts_reg = bp->pps->mem;4116 src = "PHC";4117 on = ioread32(&ts_reg->enable);4118 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);4119 seq_printf(s, "%7s: %s, src: %s\n", "TS5",4120 on && map ? " ON" : "OFF", src);4121 4122 map = !!(bp->pps_req_map & OCP_REQ_PPS);4123 seq_printf(s, "%7s: %s, src: %s\n", "PPS",4124 on && map ? " ON" : "OFF", src);4125 }4126 4127 if (bp->fw_cap & OCP_CAP_SIGNAL)4128 for (i = 0; i < 4; i++)4129 _signal_summary_show(s, bp, i);4130 4131 if (bp->fw_cap & OCP_CAP_FREQ)4132 for (i = 0; i < 4; i++)4133 _frequency_summary_show(s, i, bp->freq_in[i]);4134 4135 if (bp->irig_out) {4136 ctrl = ioread32(&bp->irig_out->ctrl);4137 on = ctrl & IRIG_M_CTRL_ENABLE;4138 val = ioread32(&bp->irig_out->status);4139 gpio_output_map(buf, bp, sma_val, 4);4140 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",4141 on ? " ON" : "OFF", val, (ctrl >> 16), buf);4142 }4143 4144 if (bp->irig_in) {4145 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;4146 val = ioread32(&bp->irig_in->status);4147 gpio_input_map(buf, bp, sma_val, 4, NULL);4148 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",4149 on ? " ON" : "OFF", val, buf);4150 }4151 4152 if (bp->dcf_out) {4153 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;4154 val = ioread32(&bp->dcf_out->status);4155 gpio_output_map(buf, bp, sma_val, 5);4156 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",4157 on ? " ON" : "OFF", val, buf);4158 }4159 4160 if (bp->dcf_in) {4161 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;4162 val = ioread32(&bp->dcf_in->status);4163 gpio_input_map(buf, bp, sma_val, 5, NULL);4164 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",4165 on ? " ON" : "OFF", val, buf);4166 }4167 4168 if (bp->nmea_out) {4169 on = ioread32(&bp->nmea_out->ctrl) & 1;4170 val = ioread32(&bp->nmea_out->status);4171 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",4172 on ? " ON" : "OFF", val);4173 }4174 4175 /* compute src for PPS1, used below. */4176 if (bp->pps_select) {4177 val = ioread32(&bp->pps_select->gpio1);4178 src = &buf[80];4179 mac_src = "GNSS1";4180 if (val & 0x01) {4181 gpio_input_map(src, bp, sma_val, 0, NULL);4182 mac_src = src;4183 } else if (val & 0x02) {4184 src = "MAC";4185 } else if (val & 0x04) {4186 src = "GNSS1";4187 } else {4188 src = "----";4189 mac_src = src;4190 }4191 } else {4192 src = "?";4193 mac_src = src;4194 }4195 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);4196 4197 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");4198 seq_printf(s, "MAC PPS2 src: %s\n", buf);4199 4200 /* assumes automatic switchover/selection */4201 val = ioread32(&bp->reg->select);4202 switch (val >> 16) {4203 case 0:4204 sprintf(buf, "----");4205 break;4206 case 2:4207 sprintf(buf, "IRIG");4208 break;4209 case 3:4210 sprintf(buf, "%s via PPS1", src);4211 break;4212 case 6:4213 sprintf(buf, "DCF");4214 break;4215 default:4216 strcpy(buf, "unknown");4217 break;4218 }4219 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,4220 bp->sync ? "sync" : "unsynced");4221 4222 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {4223 struct timespec64 sys_ts;4224 s64 pre_ns, post_ns, ns;4225 4226 pre_ns = timespec64_to_ns(&sts.pre_ts);4227 post_ns = timespec64_to_ns(&sts.post_ts);4228 ns = (pre_ns + post_ns) / 2;4229 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;4230 sys_ts = ns_to_timespec64(ns);4231 4232 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",4233 ts.tv_sec, ts.tv_nsec, &ts);4234 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",4235 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,4236 bp->utc_tai_offset);4237 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",4238 timespec64_to_ns(&ts) - ns,4239 post_ns - pre_ns);4240 }4241 4242 free_page((unsigned long)buf);4243 return 0;4244}4245DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);4246 4247static int4248ptp_ocp_tod_status_show(struct seq_file *s, void *data)4249{4250 struct device *dev = s->private;4251 struct ptp_ocp *bp;4252 u32 val;4253 int idx;4254 4255 bp = dev_get_drvdata(dev);4256 4257 val = ioread32(&bp->tod->ctrl);4258 if (!(val & TOD_CTRL_ENABLE)) {4259 seq_printf(s, "TOD Slave disabled\n");4260 return 0;4261 }4262 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);4263 4264 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;4265 idx += (val >> 16) & 3;4266 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));4267 4268 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;4269 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));4270 4271 val = ioread32(&bp->tod->version);4272 seq_printf(s, "TOD Version %d.%d.%d\n",4273 val >> 24, (val >> 16) & 0xff, val & 0xffff);4274 4275 val = ioread32(&bp->tod->status);4276 seq_printf(s, "Status register: 0x%08X\n", val);4277 4278 val = ioread32(&bp->tod->adj_sec);4279 idx = (val & ~INT_MAX) ? -1 : 1;4280 idx *= (val & INT_MAX);4281 seq_printf(s, "Correction seconds: %d\n", idx);4282 4283 val = ioread32(&bp->tod->utc_status);4284 seq_printf(s, "UTC status register: 0x%08X\n", val);4285 seq_printf(s, "UTC offset: %ld valid:%d\n",4286 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);4287 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",4288 val & TOD_STATUS_LEAP_VALID ? 1 : 0,4289 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);4290 4291 val = ioread32(&bp->tod->leap);4292 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);4293 4294 return 0;4295}4296DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);4297 4298static struct dentry *ptp_ocp_debugfs_root;4299 4300static void4301ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)4302{4303 struct dentry *d;4304 4305 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);4306 bp->debug_root = d;4307 debugfs_create_file("summary", 0444, bp->debug_root,4308 &bp->dev, &ptp_ocp_summary_fops);4309 if (bp->tod)4310 debugfs_create_file("tod_status", 0444, bp->debug_root,4311 &bp->dev, &ptp_ocp_tod_status_fops);4312}4313 4314static void4315ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)4316{4317 debugfs_remove_recursive(bp->debug_root);4318}4319 4320static void4321ptp_ocp_debugfs_init(void)4322{4323 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);4324}4325 4326static void4327ptp_ocp_debugfs_fini(void)4328{4329 debugfs_remove_recursive(ptp_ocp_debugfs_root);4330}4331 4332static void4333ptp_ocp_dev_release(struct device *dev)4334{4335 struct ptp_ocp *bp = dev_get_drvdata(dev);4336 4337 mutex_lock(&ptp_ocp_lock);4338 idr_remove(&ptp_ocp_idr, bp->id);4339 mutex_unlock(&ptp_ocp_lock);4340}4341 4342static int4343ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)4344{4345 int i, err;4346 4347 mutex_lock(&ptp_ocp_lock);4348 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);4349 mutex_unlock(&ptp_ocp_lock);4350 if (err < 0) {4351 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);4352 return err;4353 }4354 bp->id = err;4355 4356 bp->ptp_info = ptp_ocp_clock_info;4357 spin_lock_init(&bp->lock);4358 4359 for (i = 0; i < __PORT_COUNT; i++)4360 bp->port[i].line = -1;4361 4362 bp->pdev = pdev;4363 4364 device_initialize(&bp->dev);4365 dev_set_name(&bp->dev, "ocp%d", bp->id);4366 bp->dev.class = &timecard_class;4367 bp->dev.parent = &pdev->dev;4368 bp->dev.release = ptp_ocp_dev_release;4369 dev_set_drvdata(&bp->dev, bp);4370 4371 err = device_add(&bp->dev);4372 if (err) {4373 dev_err(&bp->dev, "device add failed: %d\n", err);4374 goto out;4375 }4376 4377 pci_set_drvdata(pdev, bp);4378 4379 return 0;4380 4381out:4382 put_device(&bp->dev);4383 return err;4384}4385 4386static void4387ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)4388{4389 struct device *dev = &bp->dev;4390 4391 if (sysfs_create_link(&dev->kobj, &child->kobj, link))4392 dev_err(dev, "%s symlink failed\n", link);4393}4394 4395static void4396ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)4397{4398 struct device *dev, *child;4399 4400 dev = &bp->pdev->dev;4401 4402 child = device_find_child_by_name(dev, name);4403 if (!child) {4404 dev_err(dev, "Could not find device %s\n", name);4405 return;4406 }4407 4408 ptp_ocp_symlink(bp, child, link);4409 put_device(child);4410}4411 4412static int4413ptp_ocp_complete(struct ptp_ocp *bp)4414{4415 struct pps_device *pps;4416 char buf[32];4417 4418 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));4419 ptp_ocp_link_child(bp, buf, "ptp");4420 4421 pps = pps_lookup_dev(bp->ptp);4422 if (pps)4423 ptp_ocp_symlink(bp, pps->dev, "pps");4424 4425 ptp_ocp_debugfs_add_device(bp);4426 4427 return 0;4428}4429 4430static void4431ptp_ocp_phc_info(struct ptp_ocp *bp)4432{4433 struct timespec64 ts;4434 u32 version, select;4435 4436 version = ioread32(&bp->reg->version);4437 select = ioread32(&bp->reg->select);4438 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",4439 version >> 24, (version >> 16) & 0xff, version & 0xffff,4440 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),4441 ptp_clock_index(bp->ptp));4442 4443 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))4444 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",4445 ts.tv_sec, ts.tv_nsec,4446 bp->sync ? "in-sync" : "UNSYNCED");4447}4448 4449static void4450ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)4451{4452 if (port != -1)4453 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);4454}4455 4456static void4457ptp_ocp_info(struct ptp_ocp *bp)4458{4459 static int nmea_baud[] = {4460 1200, 2400, 4800, 9600, 19200, 38400,4461 57600, 115200, 230400, 460800, 921600,4462 1000000, 20000004463 };4464 struct device *dev = &bp->pdev->dev;4465 u32 reg;4466 int i;4467 4468 ptp_ocp_phc_info(bp);4469 4470 for (i = 0; i < __PORT_COUNT; i++) {4471 if (i == PORT_NMEA && bp->nmea_out && bp->port[PORT_NMEA].line != -1) {4472 bp->port[PORT_NMEA].baud = -1;4473 4474 reg = ioread32(&bp->nmea_out->uart_baud);4475 if (reg < ARRAY_SIZE(nmea_baud))4476 bp->port[PORT_NMEA].baud = nmea_baud[reg];4477 }4478 ptp_ocp_serial_info(dev, ptp_ocp_tty_port_name(i), bp->port[i].line,4479 bp->port[i].baud);4480 }4481}4482 4483static void4484ptp_ocp_detach_sysfs(struct ptp_ocp *bp)4485{4486 struct device *dev = &bp->dev;4487 4488 sysfs_remove_link(&dev->kobj, "ptp");4489 sysfs_remove_link(&dev->kobj, "pps");4490}4491 4492static void4493ptp_ocp_detach(struct ptp_ocp *bp)4494{4495 int i;4496 4497 ptp_ocp_debugfs_remove_device(bp);4498 ptp_ocp_detach_sysfs(bp);4499 ptp_ocp_attr_group_del(bp);4500 if (timer_pending(&bp->watchdog))4501 del_timer_sync(&bp->watchdog);4502 if (bp->ts0)4503 ptp_ocp_unregister_ext(bp->ts0);4504 if (bp->ts1)4505 ptp_ocp_unregister_ext(bp->ts1);4506 if (bp->ts2)4507 ptp_ocp_unregister_ext(bp->ts2);4508 if (bp->ts3)4509 ptp_ocp_unregister_ext(bp->ts3);4510 if (bp->ts4)4511 ptp_ocp_unregister_ext(bp->ts4);4512 if (bp->pps)4513 ptp_ocp_unregister_ext(bp->pps);4514 for (i = 0; i < 4; i++)4515 if (bp->signal_out[i])4516 ptp_ocp_unregister_ext(bp->signal_out[i]);4517 for (i = 0; i < __PORT_COUNT; i++)4518 if (bp->port[i].line != -1)4519 serial8250_unregister_port(bp->port[i].line);4520 platform_device_unregister(bp->spi_flash);4521 platform_device_unregister(bp->i2c_ctrl);4522 if (bp->i2c_clk)4523 clk_hw_unregister_fixed_rate(bp->i2c_clk);4524 if (bp->n_irqs)4525 pci_free_irq_vectors(bp->pdev);4526 if (bp->ptp)4527 ptp_clock_unregister(bp->ptp);4528 kfree(bp->ptp_info.pin_config);4529 device_unregister(&bp->dev);4530}4531 4532static int4533ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,4534 enum dpll_lock_status *status,4535 enum dpll_lock_status_error *status_error,4536 struct netlink_ext_ack *extack)4537{4538 struct ptp_ocp *bp = priv;4539 4540 *status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;4541 4542 return 0;4543}4544 4545static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,4546 const struct dpll_device *dpll, void *priv,4547 enum dpll_pin_state *state,4548 struct netlink_ext_ack *extack)4549{4550 struct ptp_ocp *bp = priv;4551 int idx;4552 4553 if (bp->pps_select) {4554 idx = ioread32(&bp->pps_select->gpio1);4555 *state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :4556 DPLL_PIN_STATE_SELECTABLE;4557 return 0;4558 }4559 NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");4560 return -EINVAL;4561}4562 4563static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,4564 enum dpll_mode *mode, struct netlink_ext_ack *extack)4565{4566 *mode = DPLL_MODE_AUTOMATIC;4567 return 0;4568}4569 4570static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,4571 void *pin_priv,4572 const struct dpll_device *dpll,4573 void *priv,4574 enum dpll_pin_direction *direction,4575 struct netlink_ext_ack *extack)4576{4577 struct ptp_ocp_sma_connector *sma = pin_priv;4578 4579 *direction = sma->mode == SMA_MODE_IN ?4580 DPLL_PIN_DIRECTION_INPUT :4581 DPLL_PIN_DIRECTION_OUTPUT;4582 return 0;4583}4584 4585static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,4586 void *pin_priv,4587 const struct dpll_device *dpll,4588 void *dpll_priv,4589 enum dpll_pin_direction direction,4590 struct netlink_ext_ack *extack)4591{4592 struct ptp_ocp_sma_connector *sma = pin_priv;4593 struct ptp_ocp *bp = dpll_priv;4594 enum ptp_ocp_sma_mode mode;4595 int sma_nr = (sma - bp->sma);4596 4597 if (sma->fixed_dir)4598 return -EOPNOTSUPP;4599 mode = direction == DPLL_PIN_DIRECTION_INPUT ?4600 SMA_MODE_IN : SMA_MODE_OUT;4601 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1);4602}4603 4604static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,4605 void *pin_priv,4606 const struct dpll_device *dpll,4607 void *dpll_priv, u64 frequency,4608 struct netlink_ext_ack *extack)4609{4610 struct ptp_ocp_sma_connector *sma = pin_priv;4611 struct ptp_ocp *bp = dpll_priv;4612 const struct ocp_selector *tbl;4613 int sma_nr = (sma - bp->sma);4614 int i;4615 4616 if (sma->fixed_fcn)4617 return -EOPNOTSUPP;4618 4619 tbl = bp->sma_op->tbl[sma->mode];4620 for (i = 0; tbl[i].name; i++)4621 if (tbl[i].frequency == frequency)4622 return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr + 1);4623 return -EINVAL;4624}4625 4626static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,4627 void *pin_priv,4628 const struct dpll_device *dpll,4629 void *dpll_priv, u64 *frequency,4630 struct netlink_ext_ack *extack)4631{4632 struct ptp_ocp_sma_connector *sma = pin_priv;4633 struct ptp_ocp *bp = dpll_priv;4634 const struct ocp_selector *tbl;4635 int sma_nr = (sma - bp->sma);4636 u32 val;4637 int i;4638 4639 val = bp->sma_op->get(bp, sma_nr + 1);4640 tbl = bp->sma_op->tbl[sma->mode];4641 for (i = 0; tbl[i].name; i++)4642 if (val == tbl[i].value) {4643 *frequency = tbl[i].frequency;4644 return 0;4645 }4646 4647 return -EINVAL;4648}4649 4650static const struct dpll_device_ops dpll_ops = {4651 .lock_status_get = ptp_ocp_dpll_lock_status_get,4652 .mode_get = ptp_ocp_dpll_mode_get,4653};4654 4655static const struct dpll_pin_ops dpll_pins_ops = {4656 .frequency_get = ptp_ocp_dpll_frequency_get,4657 .frequency_set = ptp_ocp_dpll_frequency_set,4658 .direction_get = ptp_ocp_dpll_direction_get,4659 .direction_set = ptp_ocp_dpll_direction_set,4660 .state_on_dpll_get = ptp_ocp_dpll_state_get,4661};4662 4663static void4664ptp_ocp_sync_work(struct work_struct *work)4665{4666 struct ptp_ocp *bp;4667 bool sync;4668 4669 bp = container_of(work, struct ptp_ocp, sync_work.work);4670 sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);4671 4672 if (bp->sync != sync)4673 dpll_device_change_ntf(bp->dpll);4674 4675 bp->sync = sync;4676 4677 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);4678}4679 4680static int4681ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)4682{4683 struct devlink *devlink;4684 struct ptp_ocp *bp;4685 int err, i;4686 u64 clkid;4687 4688 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);4689 if (!devlink) {4690 dev_err(&pdev->dev, "devlink_alloc failed\n");4691 return -ENOMEM;4692 }4693 4694 err = pci_enable_device(pdev);4695 if (err) {4696 dev_err(&pdev->dev, "pci_enable_device\n");4697 goto out_free;4698 }4699 4700 bp = devlink_priv(devlink);4701 err = ptp_ocp_device_init(bp, pdev);4702 if (err)4703 goto out_disable;4704 4705 INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);4706 4707 /* compat mode.4708 * Older FPGA firmware only returns 2 irq's.4709 * allow this - if not all of the IRQ's are returned, skip the4710 * extra devices and just register the clock.4711 */4712 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);4713 if (err < 0) {4714 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);4715 goto out;4716 }4717 bp->n_irqs = err;4718 pci_set_master(pdev);4719 4720 err = ptp_ocp_register_resources(bp, id->driver_data);4721 if (err)4722 goto out;4723 4724 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);4725 if (IS_ERR(bp->ptp)) {4726 err = PTR_ERR(bp->ptp);4727 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);4728 bp->ptp = NULL;4729 goto out;4730 }4731 4732 err = ptp_ocp_complete(bp);4733 if (err)4734 goto out;4735 4736 ptp_ocp_info(bp);4737 devlink_register(devlink);4738 4739 clkid = pci_get_dsn(pdev);4740 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE);4741 if (IS_ERR(bp->dpll)) {4742 err = PTR_ERR(bp->dpll);4743 dev_err(&pdev->dev, "dpll_device_alloc failed\n");4744 goto out;4745 }4746 4747 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);4748 if (err)4749 goto out;4750 4751 for (i = 0; i < OCP_SMA_NUM; i++) {4752 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop);4753 if (IS_ERR(bp->sma[i].dpll_pin)) {4754 err = PTR_ERR(bp->sma[i].dpll_pin);4755 goto out_dpll;4756 }4757 4758 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,4759 &bp->sma[i]);4760 if (err) {4761 dpll_pin_put(bp->sma[i].dpll_pin);4762 goto out_dpll;4763 }4764 }4765 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);4766 4767 return 0;4768out_dpll:4769 while (i) {4770 --i;4771 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);4772 dpll_pin_put(bp->sma[i].dpll_pin);4773 }4774 dpll_device_put(bp->dpll);4775out:4776 ptp_ocp_detach(bp);4777out_disable:4778 pci_disable_device(pdev);4779out_free:4780 devlink_free(devlink);4781 return err;4782}4783 4784static void4785ptp_ocp_remove(struct pci_dev *pdev)4786{4787 struct ptp_ocp *bp = pci_get_drvdata(pdev);4788 struct devlink *devlink = priv_to_devlink(bp);4789 int i;4790 4791 cancel_delayed_work_sync(&bp->sync_work);4792 for (i = 0; i < OCP_SMA_NUM; i++) {4793 if (bp->sma[i].dpll_pin) {4794 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);4795 dpll_pin_put(bp->sma[i].dpll_pin);4796 }4797 }4798 dpll_device_unregister(bp->dpll, &dpll_ops, bp);4799 dpll_device_put(bp->dpll);4800 devlink_unregister(devlink);4801 ptp_ocp_detach(bp);4802 pci_disable_device(pdev);4803 4804 devlink_free(devlink);4805}4806 4807static struct pci_driver ptp_ocp_driver = {4808 .name = KBUILD_MODNAME,4809 .id_table = ptp_ocp_pcidev_id,4810 .probe = ptp_ocp_probe,4811 .remove = ptp_ocp_remove,4812};4813 4814static int4815ptp_ocp_i2c_notifier_call(struct notifier_block *nb,4816 unsigned long action, void *data)4817{4818 struct device *dev, *child = data;4819 struct ptp_ocp *bp;4820 bool add;4821 4822 switch (action) {4823 case BUS_NOTIFY_ADD_DEVICE:4824 case BUS_NOTIFY_DEL_DEVICE:4825 add = action == BUS_NOTIFY_ADD_DEVICE;4826 break;4827 default:4828 return 0;4829 }4830 4831 if (!i2c_verify_adapter(child))4832 return 0;4833 4834 dev = child;4835 while ((dev = dev->parent))4836 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))4837 goto found;4838 return 0;4839 4840found:4841 bp = dev_get_drvdata(dev);4842 if (add)4843 ptp_ocp_symlink(bp, child, "i2c");4844 else4845 sysfs_remove_link(&bp->dev.kobj, "i2c");4846 4847 return 0;4848}4849 4850static struct notifier_block ptp_ocp_i2c_notifier = {4851 .notifier_call = ptp_ocp_i2c_notifier_call,4852};4853 4854static int __init4855ptp_ocp_init(void)4856{4857 const char *what;4858 int err;4859 4860 ptp_ocp_debugfs_init();4861 4862 what = "timecard class";4863 err = class_register(&timecard_class);4864 if (err)4865 goto out;4866 4867 what = "i2c notifier";4868 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);4869 if (err)4870 goto out_notifier;4871 4872 what = "ptp_ocp driver";4873 err = pci_register_driver(&ptp_ocp_driver);4874 if (err)4875 goto out_register;4876 4877 return 0;4878 4879out_register:4880 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);4881out_notifier:4882 class_unregister(&timecard_class);4883out:4884 ptp_ocp_debugfs_fini();4885 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);4886 return err;4887}4888 4889static void __exit4890ptp_ocp_fini(void)4891{4892 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);4893 pci_unregister_driver(&ptp_ocp_driver);4894 class_unregister(&timecard_class);4895 ptp_ocp_debugfs_fini();4896}4897 4898module_init(ptp_ocp_init);4899module_exit(ptp_ocp_fini);4900 4901MODULE_DESCRIPTION("OpenCompute TimeCard driver");4902MODULE_LICENSE("GPL v2");4903