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1// SPDX-License-Identifier: GPL-2.02/*3 * Intel Keem Bay PWM driver4 *5 * Copyright (C) 2020 Intel Corporation6 * Authors: Lai Poey Seng <poey.seng.lai@intel.com>7 * Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>8 *9 * Limitations:10 * - Upon disabling a channel, the currently running11 * period will not be completed. However, upon12 * reconfiguration of the duty cycle/period, the13 * currently running period will be completed first.14 */15 16#include <linux/bitfield.h>17#include <linux/clk.h>18#include <linux/io.h>19#include <linux/mod_devicetable.h>20#include <linux/module.h>21#include <linux/platform_device.h>22#include <linux/pwm.h>23#include <linux/regmap.h>24 25#define KMB_TOTAL_PWM_CHANNELS 626#define KMB_PWM_COUNT_MAX U16_MAX27#define KMB_PWM_EN_BIT BIT(31)28 29/* Mask */30#define KMB_PWM_HIGH_MASK GENMASK(31, 16)31#define KMB_PWM_LOW_MASK GENMASK(15, 0)32#define KMB_PWM_LEADIN_MASK GENMASK(30, 0)33 34/* PWM Register offset */35#define KMB_PWM_LEADIN_OFFSET(ch) (0x00 + 4 * (ch))36#define KMB_PWM_HIGHLOW_OFFSET(ch) (0x20 + 4 * (ch))37 38struct keembay_pwm {39 struct device *dev;40 struct clk *clk;41 void __iomem *base;42};43 44static inline struct keembay_pwm *to_keembay_pwm_dev(struct pwm_chip *chip)45{46 return pwmchip_get_drvdata(chip);47}48 49static void keembay_clk_unprepare(void *data)50{51 clk_disable_unprepare(data);52}53 54static int keembay_clk_enable(struct device *dev, struct clk *clk)55{56 int ret;57 58 ret = clk_prepare_enable(clk);59 if (ret)60 return ret;61 62 return devm_add_action_or_reset(dev, keembay_clk_unprepare, clk);63}64 65/*66 * With gcc 10, CONFIG_CC_OPTIMIZE_FOR_SIZE and only "inline" instead of67 * "__always_inline" this fails to compile because the compiler doesn't notice68 * for all valid masks (e.g. KMB_PWM_LEADIN_MASK) that they are ok.69 */70static __always_inline void keembay_pwm_update_bits(struct keembay_pwm *priv, u32 mask,71 u32 val, u32 offset)72{73 u32 buff = readl(priv->base + offset);74 75 buff = u32_replace_bits(buff, val, mask);76 writel(buff, priv->base + offset);77}78 79static void keembay_pwm_enable(struct keembay_pwm *priv, int ch)80{81 keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 1,82 KMB_PWM_LEADIN_OFFSET(ch));83}84 85static void keembay_pwm_disable(struct keembay_pwm *priv, int ch)86{87 keembay_pwm_update_bits(priv, KMB_PWM_EN_BIT, 0,88 KMB_PWM_LEADIN_OFFSET(ch));89}90 91static int keembay_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,92 struct pwm_state *state)93{94 struct keembay_pwm *priv = to_keembay_pwm_dev(chip);95 unsigned long long high, low;96 unsigned long clk_rate;97 u32 highlow;98 99 clk_rate = clk_get_rate(priv->clk);100 101 /* Read channel enabled status */102 highlow = readl(priv->base + KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));103 if (highlow & KMB_PWM_EN_BIT)104 state->enabled = true;105 else106 state->enabled = false;107 108 /* Read period and duty cycle */109 highlow = readl(priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));110 low = FIELD_GET(KMB_PWM_LOW_MASK, highlow) * NSEC_PER_SEC;111 high = FIELD_GET(KMB_PWM_HIGH_MASK, highlow) * NSEC_PER_SEC;112 state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate);113 state->period = DIV_ROUND_UP_ULL(high + low, clk_rate);114 state->polarity = PWM_POLARITY_NORMAL;115 116 return 0;117}118 119static int keembay_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,120 const struct pwm_state *state)121{122 struct keembay_pwm *priv = to_keembay_pwm_dev(chip);123 struct pwm_state current_state;124 unsigned long long div;125 unsigned long clk_rate;126 u32 pwm_count = 0;127 u16 high, low;128 129 if (state->polarity != PWM_POLARITY_NORMAL)130 return -EINVAL;131 132 /*133 * Configure the pwm repeat count as infinite at (15:0) and leadin134 * low time as 0 at (30:16), which is in terms of clock cycles.135 */136 keembay_pwm_update_bits(priv, KMB_PWM_LEADIN_MASK, 0,137 KMB_PWM_LEADIN_OFFSET(pwm->hwpwm));138 139 keembay_pwm_get_state(chip, pwm, ¤t_state);140 141 if (!state->enabled) {142 if (current_state.enabled)143 keembay_pwm_disable(priv, pwm->hwpwm);144 return 0;145 }146 147 /*148 * The upper 16 bits and lower 16 bits of the KMB_PWM_HIGHLOW_OFFSET149 * register contain the high time and low time of waveform accordingly.150 * All the values are in terms of clock cycles.151 */152 153 clk_rate = clk_get_rate(priv->clk);154 div = clk_rate * state->duty_cycle;155 div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);156 if (div > KMB_PWM_COUNT_MAX)157 return -ERANGE;158 159 high = div;160 div = clk_rate * state->period;161 div = DIV_ROUND_DOWN_ULL(div, NSEC_PER_SEC);162 div = div - high;163 if (div > KMB_PWM_COUNT_MAX)164 return -ERANGE;165 166 low = div;167 168 pwm_count = FIELD_PREP(KMB_PWM_HIGH_MASK, high) |169 FIELD_PREP(KMB_PWM_LOW_MASK, low);170 171 writel(pwm_count, priv->base + KMB_PWM_HIGHLOW_OFFSET(pwm->hwpwm));172 173 if (state->enabled && !current_state.enabled)174 keembay_pwm_enable(priv, pwm->hwpwm);175 176 return 0;177}178 179static const struct pwm_ops keembay_pwm_ops = {180 .apply = keembay_pwm_apply,181 .get_state = keembay_pwm_get_state,182};183 184static int keembay_pwm_probe(struct platform_device *pdev)185{186 struct device *dev = &pdev->dev;187 struct pwm_chip *chip;188 struct keembay_pwm *priv;189 int ret;190 191 chip = devm_pwmchip_alloc(dev, KMB_TOTAL_PWM_CHANNELS, sizeof(*priv));192 if (IS_ERR(chip))193 return PTR_ERR(chip);194 priv = to_keembay_pwm_dev(chip);195 196 priv->clk = devm_clk_get(dev, NULL);197 if (IS_ERR(priv->clk))198 return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");199 200 priv->base = devm_platform_ioremap_resource(pdev, 0);201 if (IS_ERR(priv->base))202 return PTR_ERR(priv->base);203 204 ret = keembay_clk_enable(dev, priv->clk);205 if (ret)206 return ret;207 208 chip->ops = &keembay_pwm_ops;209 210 ret = devm_pwmchip_add(dev, chip);211 if (ret)212 return dev_err_probe(dev, ret, "Failed to add PWM chip\n");213 214 return 0;215}216 217static const struct of_device_id keembay_pwm_of_match[] = {218 { .compatible = "intel,keembay-pwm" },219 { }220};221MODULE_DEVICE_TABLE(of, keembay_pwm_of_match);222 223static struct platform_driver keembay_pwm_driver = {224 .probe = keembay_pwm_probe,225 .driver = {226 .name = "pwm-keembay",227 .of_match_table = keembay_pwm_of_match,228 },229};230module_platform_driver(keembay_pwm_driver);231 232MODULE_ALIAS("platform:pwm-keembay");233MODULE_DESCRIPTION("Intel Keem Bay PWM driver");234MODULE_LICENSE("GPL v2");235