1743 lines · c
1/*2 * AXP20x regulators driver.3 *4 * Copyright (C) 2013 Carlo Caione <carlo@caione.org>5 *6 * This file is subject to the terms and conditions of the GNU General7 * Public License. See the file "COPYING" in the main directory of this8 * archive for more details.9 *10 * This program is distributed in the hope that it will be useful,11 * but WITHOUT ANY WARRANTY; without even the implied warranty of12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the13 * GNU General Public License for more details.14 */15 16#include <linux/bitops.h>17#include <linux/delay.h>18#include <linux/err.h>19#include <linux/init.h>20#include <linux/mfd/axp20x.h>21#include <linux/module.h>22#include <linux/of.h>23#include <linux/platform_device.h>24#include <linux/regmap.h>25#include <linux/regulator/driver.h>26#include <linux/regulator/machine.h>27#include <linux/regulator/of_regulator.h>28 29#define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0)30#define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0)31 32#define AXP20X_IO_ENABLED 0x0333#define AXP20X_IO_DISABLED 0x0734 35#define AXP20X_WORKMODE_DCDC2_MASK BIT_MASK(2)36#define AXP20X_WORKMODE_DCDC3_MASK BIT_MASK(1)37 38#define AXP20X_FREQ_DCDC_MASK GENMASK(3, 0)39 40#define AXP20X_VBUS_IPSOUT_MGMT_MASK BIT_MASK(2)41 42#define AXP20X_DCDC2_V_OUT_MASK GENMASK(5, 0)43#define AXP20X_DCDC3_V_OUT_MASK GENMASK(7, 0)44#define AXP20X_LDO2_V_OUT_MASK GENMASK(7, 4)45#define AXP20X_LDO3_V_OUT_MASK GENMASK(6, 0)46#define AXP20X_LDO4_V_OUT_MASK GENMASK(3, 0)47#define AXP20X_LDO5_V_OUT_MASK GENMASK(7, 4)48 49#define AXP20X_PWR_OUT_EXTEN_MASK BIT_MASK(0)50#define AXP20X_PWR_OUT_DCDC3_MASK BIT_MASK(1)51#define AXP20X_PWR_OUT_LDO2_MASK BIT_MASK(2)52#define AXP20X_PWR_OUT_LDO4_MASK BIT_MASK(3)53#define AXP20X_PWR_OUT_DCDC2_MASK BIT_MASK(4)54#define AXP20X_PWR_OUT_LDO3_MASK BIT_MASK(6)55 56#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK BIT_MASK(0)57#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \58 ((x) << 0)59#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK BIT_MASK(1)60#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \61 ((x) << 1)62#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK BIT_MASK(2)63#define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN BIT(2)64#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK BIT_MASK(3)65#define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN BIT(3)66 67#define AXP20X_LDO4_V_OUT_1250mV_START 0x068#define AXP20X_LDO4_V_OUT_1250mV_STEPS 069#define AXP20X_LDO4_V_OUT_1250mV_END \70 (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)71#define AXP20X_LDO4_V_OUT_1300mV_START 0x172#define AXP20X_LDO4_V_OUT_1300mV_STEPS 773#define AXP20X_LDO4_V_OUT_1300mV_END \74 (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)75#define AXP20X_LDO4_V_OUT_2500mV_START 0x976#define AXP20X_LDO4_V_OUT_2500mV_STEPS 077#define AXP20X_LDO4_V_OUT_2500mV_END \78 (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)79#define AXP20X_LDO4_V_OUT_2700mV_START 0xa80#define AXP20X_LDO4_V_OUT_2700mV_STEPS 181#define AXP20X_LDO4_V_OUT_2700mV_END \82 (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)83#define AXP20X_LDO4_V_OUT_3000mV_START 0xc84#define AXP20X_LDO4_V_OUT_3000mV_STEPS 385#define AXP20X_LDO4_V_OUT_3000mV_END \86 (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)87#define AXP20X_LDO4_V_OUT_NUM_VOLTAGES 1688 89#define AXP22X_IO_ENABLED 0x0390#define AXP22X_IO_DISABLED 0x0491 92#define AXP22X_WORKMODE_DCDCX_MASK(x) BIT_MASK(x)93 94#define AXP22X_MISC_N_VBUSEN_FUNC BIT(4)95 96#define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0)97#define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0)98#define AXP22X_DCDC3_V_OUT_MASK GENMASK(5, 0)99#define AXP22X_DCDC4_V_OUT_MASK GENMASK(5, 0)100#define AXP22X_DCDC5_V_OUT_MASK GENMASK(4, 0)101#define AXP22X_DC5LDO_V_OUT_MASK GENMASK(2, 0)102#define AXP22X_ALDO1_V_OUT_MASK GENMASK(4, 0)103#define AXP22X_ALDO2_V_OUT_MASK GENMASK(4, 0)104#define AXP22X_ALDO3_V_OUT_MASK GENMASK(4, 0)105#define AXP22X_DLDO1_V_OUT_MASK GENMASK(4, 0)106#define AXP22X_DLDO2_V_OUT_MASK GENMASK(4, 0)107#define AXP22X_DLDO3_V_OUT_MASK GENMASK(4, 0)108#define AXP22X_DLDO4_V_OUT_MASK GENMASK(4, 0)109#define AXP22X_ELDO1_V_OUT_MASK GENMASK(4, 0)110#define AXP22X_ELDO2_V_OUT_MASK GENMASK(4, 0)111#define AXP22X_ELDO3_V_OUT_MASK GENMASK(4, 0)112#define AXP22X_LDO_IO0_V_OUT_MASK GENMASK(4, 0)113#define AXP22X_LDO_IO1_V_OUT_MASK GENMASK(4, 0)114 115#define AXP22X_PWR_OUT_DC5LDO_MASK BIT_MASK(0)116#define AXP22X_PWR_OUT_DCDC1_MASK BIT_MASK(1)117#define AXP22X_PWR_OUT_DCDC2_MASK BIT_MASK(2)118#define AXP22X_PWR_OUT_DCDC3_MASK BIT_MASK(3)119#define AXP22X_PWR_OUT_DCDC4_MASK BIT_MASK(4)120#define AXP22X_PWR_OUT_DCDC5_MASK BIT_MASK(5)121#define AXP22X_PWR_OUT_ALDO1_MASK BIT_MASK(6)122#define AXP22X_PWR_OUT_ALDO2_MASK BIT_MASK(7)123 124#define AXP22X_PWR_OUT_SW_MASK BIT_MASK(6)125#define AXP22X_PWR_OUT_DC1SW_MASK BIT_MASK(7)126 127#define AXP22X_PWR_OUT_ELDO1_MASK BIT_MASK(0)128#define AXP22X_PWR_OUT_ELDO2_MASK BIT_MASK(1)129#define AXP22X_PWR_OUT_ELDO3_MASK BIT_MASK(2)130#define AXP22X_PWR_OUT_DLDO1_MASK BIT_MASK(3)131#define AXP22X_PWR_OUT_DLDO2_MASK BIT_MASK(4)132#define AXP22X_PWR_OUT_DLDO3_MASK BIT_MASK(5)133#define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6)134#define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7)135 136#define AXP313A_DCDC1_NUM_VOLTAGES 107137#define AXP313A_DCDC23_NUM_VOLTAGES 88138#define AXP313A_DCDC_V_OUT_MASK GENMASK(6, 0)139#define AXP313A_LDO_V_OUT_MASK GENMASK(4, 0)140 141#define AXP717_DCDC1_NUM_VOLTAGES 88142#define AXP717_DCDC2_NUM_VOLTAGES 107143#define AXP717_DCDC3_NUM_VOLTAGES 103144#define AXP717_DCDC_V_OUT_MASK GENMASK(6, 0)145#define AXP717_LDO_V_OUT_MASK GENMASK(4, 0)146#define AXP717_BOOST_V_OUT_MASK GENMASK(7, 4)147 148#define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0)149#define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1)150#define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2)151#define AXP803_PWR_OUT_DCDC4_MASK BIT_MASK(3)152#define AXP803_PWR_OUT_DCDC5_MASK BIT_MASK(4)153#define AXP803_PWR_OUT_DCDC6_MASK BIT_MASK(5)154 155#define AXP803_PWR_OUT_FLDO1_MASK BIT_MASK(2)156#define AXP803_PWR_OUT_FLDO2_MASK BIT_MASK(3)157 158#define AXP803_DCDC1_V_OUT_MASK GENMASK(4, 0)159#define AXP803_DCDC2_V_OUT_MASK GENMASK(6, 0)160#define AXP803_DCDC3_V_OUT_MASK GENMASK(6, 0)161#define AXP803_DCDC4_V_OUT_MASK GENMASK(6, 0)162#define AXP803_DCDC5_V_OUT_MASK GENMASK(6, 0)163#define AXP803_DCDC6_V_OUT_MASK GENMASK(6, 0)164 165#define AXP803_FLDO1_V_OUT_MASK GENMASK(3, 0)166#define AXP803_FLDO2_V_OUT_MASK GENMASK(3, 0)167 168#define AXP803_DCDC23_POLYPHASE_DUAL BIT(6)169#define AXP803_DCDC56_POLYPHASE_DUAL BIT(5)170 171#define AXP803_DCDC234_500mV_START 0x00172#define AXP803_DCDC234_500mV_STEPS 70173#define AXP803_DCDC234_500mV_END \174 (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)175#define AXP803_DCDC234_1220mV_START 0x47176#define AXP803_DCDC234_1220mV_STEPS 4177#define AXP803_DCDC234_1220mV_END \178 (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)179#define AXP803_DCDC234_NUM_VOLTAGES 76180 181#define AXP803_DCDC5_800mV_START 0x00182#define AXP803_DCDC5_800mV_STEPS 32183#define AXP803_DCDC5_800mV_END \184 (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)185#define AXP803_DCDC5_1140mV_START 0x21186#define AXP803_DCDC5_1140mV_STEPS 35187#define AXP803_DCDC5_1140mV_END \188 (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)189#define AXP803_DCDC5_NUM_VOLTAGES 69190 191#define AXP803_DCDC6_600mV_START 0x00192#define AXP803_DCDC6_600mV_STEPS 50193#define AXP803_DCDC6_600mV_END \194 (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)195#define AXP803_DCDC6_1120mV_START 0x33196#define AXP803_DCDC6_1120mV_STEPS 20197#define AXP803_DCDC6_1120mV_END \198 (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)199#define AXP803_DCDC6_NUM_VOLTAGES 72200 201#define AXP803_DLDO2_700mV_START 0x00202#define AXP803_DLDO2_700mV_STEPS 26203#define AXP803_DLDO2_700mV_END \204 (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)205#define AXP803_DLDO2_3400mV_START 0x1b206#define AXP803_DLDO2_3400mV_STEPS 4207#define AXP803_DLDO2_3400mV_END \208 (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)209#define AXP803_DLDO2_NUM_VOLTAGES 32210 211#define AXP806_DCDCA_V_CTRL_MASK GENMASK(6, 0)212#define AXP806_DCDCB_V_CTRL_MASK GENMASK(4, 0)213#define AXP806_DCDCC_V_CTRL_MASK GENMASK(6, 0)214#define AXP806_DCDCD_V_CTRL_MASK GENMASK(5, 0)215#define AXP806_DCDCE_V_CTRL_MASK GENMASK(4, 0)216#define AXP806_ALDO1_V_CTRL_MASK GENMASK(4, 0)217#define AXP806_ALDO2_V_CTRL_MASK GENMASK(4, 0)218#define AXP806_ALDO3_V_CTRL_MASK GENMASK(4, 0)219#define AXP806_BLDO1_V_CTRL_MASK GENMASK(3, 0)220#define AXP806_BLDO2_V_CTRL_MASK GENMASK(3, 0)221#define AXP806_BLDO3_V_CTRL_MASK GENMASK(3, 0)222#define AXP806_BLDO4_V_CTRL_MASK GENMASK(3, 0)223#define AXP806_CLDO1_V_CTRL_MASK GENMASK(4, 0)224#define AXP806_CLDO2_V_CTRL_MASK GENMASK(4, 0)225#define AXP806_CLDO3_V_CTRL_MASK GENMASK(4, 0)226 227#define AXP806_PWR_OUT_DCDCA_MASK BIT_MASK(0)228#define AXP806_PWR_OUT_DCDCB_MASK BIT_MASK(1)229#define AXP806_PWR_OUT_DCDCC_MASK BIT_MASK(2)230#define AXP806_PWR_OUT_DCDCD_MASK BIT_MASK(3)231#define AXP806_PWR_OUT_DCDCE_MASK BIT_MASK(4)232#define AXP806_PWR_OUT_ALDO1_MASK BIT_MASK(5)233#define AXP806_PWR_OUT_ALDO2_MASK BIT_MASK(6)234#define AXP806_PWR_OUT_ALDO3_MASK BIT_MASK(7)235#define AXP806_PWR_OUT_BLDO1_MASK BIT_MASK(0)236#define AXP806_PWR_OUT_BLDO2_MASK BIT_MASK(1)237#define AXP806_PWR_OUT_BLDO3_MASK BIT_MASK(2)238#define AXP806_PWR_OUT_BLDO4_MASK BIT_MASK(3)239#define AXP806_PWR_OUT_CLDO1_MASK BIT_MASK(4)240#define AXP806_PWR_OUT_CLDO2_MASK BIT_MASK(5)241#define AXP806_PWR_OUT_CLDO3_MASK BIT_MASK(6)242#define AXP806_PWR_OUT_SW_MASK BIT_MASK(7)243 244#define AXP806_DCDCAB_POLYPHASE_DUAL 0x40245#define AXP806_DCDCABC_POLYPHASE_TRI 0x80246#define AXP806_DCDCABC_POLYPHASE_MASK GENMASK(7, 6)247 248#define AXP806_DCDCDE_POLYPHASE_DUAL BIT(5)249 250#define AXP806_DCDCA_600mV_START 0x00251#define AXP806_DCDCA_600mV_STEPS 50252#define AXP806_DCDCA_600mV_END \253 (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)254#define AXP806_DCDCA_1120mV_START 0x33255#define AXP806_DCDCA_1120mV_STEPS 20256#define AXP806_DCDCA_1120mV_END \257 (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)258#define AXP806_DCDCA_NUM_VOLTAGES 72259 260#define AXP806_DCDCD_600mV_START 0x00261#define AXP806_DCDCD_600mV_STEPS 45262#define AXP806_DCDCD_600mV_END \263 (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)264#define AXP806_DCDCD_1600mV_START 0x2e265#define AXP806_DCDCD_1600mV_STEPS 17266#define AXP806_DCDCD_1600mV_END \267 (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)268#define AXP806_DCDCD_NUM_VOLTAGES 64269 270#define AXP809_DCDC4_600mV_START 0x00271#define AXP809_DCDC4_600mV_STEPS 47272#define AXP809_DCDC4_600mV_END \273 (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)274#define AXP809_DCDC4_1800mV_START 0x30275#define AXP809_DCDC4_1800mV_STEPS 8276#define AXP809_DCDC4_1800mV_END \277 (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)278#define AXP809_DCDC4_NUM_VOLTAGES 57279 280#define AXP813_DCDC7_V_OUT_MASK GENMASK(6, 0)281 282#define AXP813_PWR_OUT_DCDC7_MASK BIT_MASK(6)283 284#define AXP15060_DCDC1_V_CTRL_MASK GENMASK(4, 0)285#define AXP15060_DCDC2_V_CTRL_MASK GENMASK(6, 0)286#define AXP15060_DCDC3_V_CTRL_MASK GENMASK(6, 0)287#define AXP15060_DCDC4_V_CTRL_MASK GENMASK(6, 0)288#define AXP15060_DCDC5_V_CTRL_MASK GENMASK(6, 0)289#define AXP15060_DCDC6_V_CTRL_MASK GENMASK(4, 0)290#define AXP15060_ALDO1_V_CTRL_MASK GENMASK(4, 0)291#define AXP15060_ALDO2_V_CTRL_MASK GENMASK(4, 0)292#define AXP15060_ALDO3_V_CTRL_MASK GENMASK(4, 0)293#define AXP15060_ALDO4_V_CTRL_MASK GENMASK(4, 0)294#define AXP15060_ALDO5_V_CTRL_MASK GENMASK(4, 0)295#define AXP15060_BLDO1_V_CTRL_MASK GENMASK(4, 0)296#define AXP15060_BLDO2_V_CTRL_MASK GENMASK(4, 0)297#define AXP15060_BLDO3_V_CTRL_MASK GENMASK(4, 0)298#define AXP15060_BLDO4_V_CTRL_MASK GENMASK(4, 0)299#define AXP15060_BLDO5_V_CTRL_MASK GENMASK(4, 0)300#define AXP15060_CLDO1_V_CTRL_MASK GENMASK(4, 0)301#define AXP15060_CLDO2_V_CTRL_MASK GENMASK(4, 0)302#define AXP15060_CLDO3_V_CTRL_MASK GENMASK(4, 0)303#define AXP15060_CLDO4_V_CTRL_MASK GENMASK(5, 0)304#define AXP15060_CPUSLDO_V_CTRL_MASK GENMASK(3, 0)305 306#define AXP15060_PWR_OUT_DCDC1_MASK BIT_MASK(0)307#define AXP15060_PWR_OUT_DCDC2_MASK BIT_MASK(1)308#define AXP15060_PWR_OUT_DCDC3_MASK BIT_MASK(2)309#define AXP15060_PWR_OUT_DCDC4_MASK BIT_MASK(3)310#define AXP15060_PWR_OUT_DCDC5_MASK BIT_MASK(4)311#define AXP15060_PWR_OUT_DCDC6_MASK BIT_MASK(5)312#define AXP15060_PWR_OUT_ALDO1_MASK BIT_MASK(0)313#define AXP15060_PWR_OUT_ALDO2_MASK BIT_MASK(1)314#define AXP15060_PWR_OUT_ALDO3_MASK BIT_MASK(2)315#define AXP15060_PWR_OUT_ALDO4_MASK BIT_MASK(3)316#define AXP15060_PWR_OUT_ALDO5_MASK BIT_MASK(4)317#define AXP15060_PWR_OUT_BLDO1_MASK BIT_MASK(5)318#define AXP15060_PWR_OUT_BLDO2_MASK BIT_MASK(6)319#define AXP15060_PWR_OUT_BLDO3_MASK BIT_MASK(7)320#define AXP15060_PWR_OUT_BLDO4_MASK BIT_MASK(0)321#define AXP15060_PWR_OUT_BLDO5_MASK BIT_MASK(1)322#define AXP15060_PWR_OUT_CLDO1_MASK BIT_MASK(2)323#define AXP15060_PWR_OUT_CLDO2_MASK BIT_MASK(3)324#define AXP15060_PWR_OUT_CLDO3_MASK BIT_MASK(4)325#define AXP15060_PWR_OUT_CLDO4_MASK BIT_MASK(5)326#define AXP15060_PWR_OUT_CPUSLDO_MASK BIT_MASK(6)327#define AXP15060_PWR_OUT_SW_MASK BIT_MASK(7)328 329#define AXP15060_DCDC23_POLYPHASE_DUAL_MASK BIT_MASK(6)330#define AXP15060_DCDC46_POLYPHASE_DUAL_MASK BIT_MASK(7)331 332#define AXP15060_DCDC234_500mV_START 0x00333#define AXP15060_DCDC234_500mV_STEPS 70334#define AXP15060_DCDC234_500mV_END \335 (AXP15060_DCDC234_500mV_START + AXP15060_DCDC234_500mV_STEPS)336#define AXP15060_DCDC234_1220mV_START 0x47337#define AXP15060_DCDC234_1220mV_STEPS 16338#define AXP15060_DCDC234_1220mV_END \339 (AXP15060_DCDC234_1220mV_START + AXP15060_DCDC234_1220mV_STEPS)340#define AXP15060_DCDC234_NUM_VOLTAGES 88341 342#define AXP15060_DCDC5_800mV_START 0x00343#define AXP15060_DCDC5_800mV_STEPS 32344#define AXP15060_DCDC5_800mV_END \345 (AXP15060_DCDC5_800mV_START + AXP15060_DCDC5_800mV_STEPS)346#define AXP15060_DCDC5_1140mV_START 0x21347#define AXP15060_DCDC5_1140mV_STEPS 35348#define AXP15060_DCDC5_1140mV_END \349 (AXP15060_DCDC5_1140mV_START + AXP15060_DCDC5_1140mV_STEPS)350#define AXP15060_DCDC5_NUM_VOLTAGES 69351 352#define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \353 _vmask, _ereg, _emask, _enable_val, _disable_val) \354 [_family##_##_id] = { \355 .name = (_match), \356 .supply_name = (_supply), \357 .of_match = of_match_ptr(_match), \358 .regulators_node = of_match_ptr("regulators"), \359 .type = REGULATOR_VOLTAGE, \360 .id = _family##_##_id, \361 .n_voltages = (((_max) - (_min)) / (_step) + 1), \362 .owner = THIS_MODULE, \363 .min_uV = (_min) * 1000, \364 .uV_step = (_step) * 1000, \365 .vsel_reg = (_vreg), \366 .vsel_mask = (_vmask), \367 .enable_reg = (_ereg), \368 .enable_mask = (_emask), \369 .enable_val = (_enable_val), \370 .disable_val = (_disable_val), \371 .ops = &axp20x_ops, \372 }373 374#define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \375 _vmask, _ereg, _emask) \376 [_family##_##_id] = { \377 .name = (_match), \378 .supply_name = (_supply), \379 .of_match = of_match_ptr(_match), \380 .regulators_node = of_match_ptr("regulators"), \381 .type = REGULATOR_VOLTAGE, \382 .id = _family##_##_id, \383 .n_voltages = (((_max) - (_min)) / (_step) + 1), \384 .owner = THIS_MODULE, \385 .min_uV = (_min) * 1000, \386 .uV_step = (_step) * 1000, \387 .vsel_reg = (_vreg), \388 .vsel_mask = (_vmask), \389 .enable_reg = (_ereg), \390 .enable_mask = (_emask), \391 .ops = &axp20x_ops, \392 }393 394#define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \395 [_family##_##_id] = { \396 .name = (_match), \397 .supply_name = (_supply), \398 .of_match = of_match_ptr(_match), \399 .regulators_node = of_match_ptr("regulators"), \400 .type = REGULATOR_VOLTAGE, \401 .id = _family##_##_id, \402 .owner = THIS_MODULE, \403 .enable_reg = (_ereg), \404 .enable_mask = (_emask), \405 .ops = &axp20x_ops_sw, \406 }407 408#define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \409 [_family##_##_id] = { \410 .name = (_match), \411 .supply_name = (_supply), \412 .of_match = of_match_ptr(_match), \413 .regulators_node = of_match_ptr("regulators"), \414 .type = REGULATOR_VOLTAGE, \415 .id = _family##_##_id, \416 .n_voltages = 1, \417 .owner = THIS_MODULE, \418 .min_uV = (_volt) * 1000, \419 .ops = &axp20x_ops_fixed \420 }421 422#define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \423 _vreg, _vmask, _ereg, _emask) \424 [_family##_##_id] = { \425 .name = (_match), \426 .supply_name = (_supply), \427 .of_match = of_match_ptr(_match), \428 .regulators_node = of_match_ptr("regulators"), \429 .type = REGULATOR_VOLTAGE, \430 .id = _family##_##_id, \431 .n_voltages = (_n_voltages), \432 .owner = THIS_MODULE, \433 .vsel_reg = (_vreg), \434 .vsel_mask = (_vmask), \435 .enable_reg = (_ereg), \436 .enable_mask = (_emask), \437 .linear_ranges = (_ranges), \438 .n_linear_ranges = ARRAY_SIZE(_ranges), \439 .ops = &axp20x_ops_range, \440 }441 442static const int axp209_dcdc2_ldo3_slew_rates[] = {443 1600,444 800,445};446 447static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)448{449 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);450 int id = rdev_get_id(rdev);451 u8 reg, mask, enable, cfg = 0xff;452 const int *slew_rates;453 int rate_count = 0;454 455 switch (axp20x->variant) {456 case AXP209_ID:457 if (id == AXP20X_DCDC2) {458 slew_rates = axp209_dcdc2_ldo3_slew_rates;459 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);460 reg = AXP20X_DCDC2_LDO3_V_RAMP;461 mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |462 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;463 enable = (ramp > 0) ?464 AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0;465 break;466 }467 468 if (id == AXP20X_LDO3) {469 slew_rates = axp209_dcdc2_ldo3_slew_rates;470 rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);471 reg = AXP20X_DCDC2_LDO3_V_RAMP;472 mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |473 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;474 enable = (ramp > 0) ?475 AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0;476 break;477 }478 479 if (rate_count > 0)480 break;481 482 fallthrough;483 default:484 /* Not supported for this regulator */485 return -ENOTSUPP;486 }487 488 if (ramp == 0) {489 cfg = enable;490 } else {491 int i;492 493 for (i = 0; i < rate_count; i++) {494 if (ramp > slew_rates[i])495 break;496 497 if (id == AXP20X_DCDC2)498 cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i);499 else500 cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);501 }502 503 if (cfg == 0xff) {504 dev_err(axp20x->dev, "unsupported ramp value %d", ramp);505 return -EINVAL;506 }507 508 cfg |= enable;509 }510 511 return regmap_update_bits(axp20x->regmap, reg, mask, cfg);512}513 514static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)515{516 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);517 int id = rdev_get_id(rdev);518 519 switch (axp20x->variant) {520 case AXP209_ID:521 if ((id == AXP20X_LDO3) &&522 rdev->constraints && rdev->constraints->soft_start) {523 int v_out;524 int ret;525 526 /*527 * On some boards, the LDO3 can be overloaded when528 * turning on, causing the entire PMIC to shutdown529 * without warning. Turning it on at the minimal voltage530 * and then setting the voltage to the requested value531 * works reliably.532 */533 if (regulator_is_enabled_regmap(rdev))534 break;535 536 v_out = regulator_get_voltage_sel_regmap(rdev);537 if (v_out < 0)538 return v_out;539 540 if (v_out == 0)541 break;542 543 ret = regulator_set_voltage_sel_regmap(rdev, 0x00);544 /*545 * A small pause is needed between546 * setting the voltage and enabling the LDO to give the547 * internal state machine time to process the request.548 */549 usleep_range(1000, 5000);550 ret |= regulator_enable_regmap(rdev);551 ret |= regulator_set_voltage_sel_regmap(rdev, v_out);552 553 return ret;554 }555 break;556 default:557 /* No quirks */558 break;559 }560 561 return regulator_enable_regmap(rdev);562};563 564static const struct regulator_ops axp20x_ops_fixed = {565 .list_voltage = regulator_list_voltage_linear,566};567 568static const struct regulator_ops axp20x_ops_range = {569 .set_voltage_sel = regulator_set_voltage_sel_regmap,570 .get_voltage_sel = regulator_get_voltage_sel_regmap,571 .list_voltage = regulator_list_voltage_linear_range,572 .enable = regulator_enable_regmap,573 .disable = regulator_disable_regmap,574 .is_enabled = regulator_is_enabled_regmap,575};576 577static const struct regulator_ops axp20x_ops = {578 .set_voltage_sel = regulator_set_voltage_sel_regmap,579 .get_voltage_sel = regulator_get_voltage_sel_regmap,580 .list_voltage = regulator_list_voltage_linear,581 .enable = axp20x_regulator_enable_regmap,582 .disable = regulator_disable_regmap,583 .is_enabled = regulator_is_enabled_regmap,584 .set_ramp_delay = axp20x_set_ramp_delay,585};586 587static const struct regulator_ops axp20x_ops_sw = {588 .enable = regulator_enable_regmap,589 .disable = regulator_disable_regmap,590 .is_enabled = regulator_is_enabled_regmap,591};592 593static const struct linear_range axp20x_ldo4_ranges[] = {594 REGULATOR_LINEAR_RANGE(1250000,595 AXP20X_LDO4_V_OUT_1250mV_START,596 AXP20X_LDO4_V_OUT_1250mV_END,597 0),598 REGULATOR_LINEAR_RANGE(1300000,599 AXP20X_LDO4_V_OUT_1300mV_START,600 AXP20X_LDO4_V_OUT_1300mV_END,601 100000),602 REGULATOR_LINEAR_RANGE(2500000,603 AXP20X_LDO4_V_OUT_2500mV_START,604 AXP20X_LDO4_V_OUT_2500mV_END,605 0),606 REGULATOR_LINEAR_RANGE(2700000,607 AXP20X_LDO4_V_OUT_2700mV_START,608 AXP20X_LDO4_V_OUT_2700mV_END,609 100000),610 REGULATOR_LINEAR_RANGE(3000000,611 AXP20X_LDO4_V_OUT_3000mV_START,612 AXP20X_LDO4_V_OUT_3000mV_END,613 100000),614};615 616static const struct regulator_desc axp20x_regulators[] = {617 AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,618 AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,619 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),620 AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,621 AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,622 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),623 AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),624 AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,625 AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK,626 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),627 AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,628 AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,629 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),630 AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",631 axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,632 AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK,633 AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),634 AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,635 AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,636 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,637 AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),638};639 640static const struct regulator_desc axp22x_regulators[] = {641 AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,642 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,643 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),644 AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,645 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,646 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),647 AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,648 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,649 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),650 AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,651 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,652 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),653 AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,654 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,655 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),656 /* secondary switchable output of DCDC1 */657 AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,658 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),659 /* LDO regulator internally chained to DCDC5 */660 AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,661 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,662 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),663 AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,664 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,665 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),666 AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,667 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,668 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),669 AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,670 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,671 AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),672 AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,673 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,674 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),675 AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,676 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,677 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),678 AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,679 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,680 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),681 AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,682 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,683 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),684 AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,685 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,686 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),687 AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,688 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,689 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),690 AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,691 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,692 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),693 /* Note the datasheet only guarantees reliable operation up to694 * 3.3V, this needs to be enforced via dts provided constraints */695 AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,696 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,697 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,698 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),699 /* Note the datasheet only guarantees reliable operation up to700 * 3.3V, this needs to be enforced via dts provided constraints */701 AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,702 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,703 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,704 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),705 AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),706};707 708static const struct regulator_desc axp22x_drivevbus_regulator = {709 .name = "drivevbus",710 .supply_name = "drivevbus",711 .of_match = of_match_ptr("drivevbus"),712 .regulators_node = of_match_ptr("regulators"),713 .type = REGULATOR_VOLTAGE,714 .owner = THIS_MODULE,715 .enable_reg = AXP20X_VBUS_IPSOUT_MGMT,716 .enable_mask = AXP20X_VBUS_IPSOUT_MGMT_MASK,717 .ops = &axp20x_ops_sw,718};719 720static const struct linear_range axp313a_dcdc1_ranges[] = {721 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),722 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),723 REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000),724};725 726static const struct linear_range axp313a_dcdc2_ranges[] = {727 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),728 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),729};730 731/*732 * This is deviating from the datasheet. The values here are taken from the733 * BSP driver and have been confirmed by measurements.734 */735static const struct linear_range axp313a_dcdc3_ranges[] = {736 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),737 REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000),738};739 740static const struct regulator_desc axp313a_regulators[] = {741 AXP_DESC_RANGES(AXP313A, DCDC1, "dcdc1", "vin1",742 axp313a_dcdc1_ranges, AXP313A_DCDC1_NUM_VOLTAGES,743 AXP313A_DCDC1_CONTROL, AXP313A_DCDC_V_OUT_MASK,744 AXP313A_OUTPUT_CONTROL, BIT(0)),745 AXP_DESC_RANGES(AXP313A, DCDC2, "dcdc2", "vin2",746 axp313a_dcdc2_ranges, AXP313A_DCDC23_NUM_VOLTAGES,747 AXP313A_DCDC2_CONTROL, AXP313A_DCDC_V_OUT_MASK,748 AXP313A_OUTPUT_CONTROL, BIT(1)),749 AXP_DESC_RANGES(AXP313A, DCDC3, "dcdc3", "vin3",750 axp313a_dcdc3_ranges, AXP313A_DCDC23_NUM_VOLTAGES,751 AXP313A_DCDC3_CONTROL, AXP313A_DCDC_V_OUT_MASK,752 AXP313A_OUTPUT_CONTROL, BIT(2)),753 AXP_DESC(AXP313A, ALDO1, "aldo1", "vin1", 500, 3500, 100,754 AXP313A_ALDO1_CONTROL, AXP313A_LDO_V_OUT_MASK,755 AXP313A_OUTPUT_CONTROL, BIT(3)),756 AXP_DESC(AXP313A, DLDO1, "dldo1", "vin1", 500, 3500, 100,757 AXP313A_DLDO1_CONTROL, AXP313A_LDO_V_OUT_MASK,758 AXP313A_OUTPUT_CONTROL, BIT(4)),759 AXP_DESC_FIXED(AXP313A, RTC_LDO, "rtc-ldo", "vin1", 1800),760};761 762static const struct linear_range axp717_dcdc1_ranges[] = {763 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),764 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),765};766 767/*768 * The manual says that the last voltage is 3.4V, encoded as 0b1101011 (107),769 * but every other method proves that this is wrong, so it's really 106 that770 * programs the final 3.4V.771 */772static const struct linear_range axp717_dcdc2_ranges[] = {773 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),774 REGULATOR_LINEAR_RANGE(1220000, 71, 87, 20000),775 REGULATOR_LINEAR_RANGE(1600000, 88, 106, 100000),776};777 778static const struct linear_range axp717_dcdc3_ranges[] = {779 REGULATOR_LINEAR_RANGE(500000, 0, 70, 10000),780 REGULATOR_LINEAR_RANGE(1220000, 71, 102, 20000),781};782 783static const struct regulator_desc axp717_regulators[] = {784 AXP_DESC_RANGES(AXP717, DCDC1, "dcdc1", "vin1",785 axp717_dcdc1_ranges, AXP717_DCDC1_NUM_VOLTAGES,786 AXP717_DCDC1_CONTROL, AXP717_DCDC_V_OUT_MASK,787 AXP717_DCDC_OUTPUT_CONTROL, BIT(0)),788 AXP_DESC_RANGES(AXP717, DCDC2, "dcdc2", "vin2",789 axp717_dcdc2_ranges, AXP717_DCDC2_NUM_VOLTAGES,790 AXP717_DCDC2_CONTROL, AXP717_DCDC_V_OUT_MASK,791 AXP717_DCDC_OUTPUT_CONTROL, BIT(1)),792 AXP_DESC_RANGES(AXP717, DCDC3, "dcdc3", "vin3",793 axp717_dcdc3_ranges, AXP717_DCDC3_NUM_VOLTAGES,794 AXP717_DCDC3_CONTROL, AXP717_DCDC_V_OUT_MASK,795 AXP717_DCDC_OUTPUT_CONTROL, BIT(2)),796 AXP_DESC(AXP717, DCDC4, "dcdc4", "vin4", 1000, 3700, 100,797 AXP717_DCDC4_CONTROL, AXP717_DCDC_V_OUT_MASK,798 AXP717_DCDC_OUTPUT_CONTROL, BIT(3)),799 AXP_DESC(AXP717, ALDO1, "aldo1", "aldoin", 500, 3500, 100,800 AXP717_ALDO1_CONTROL, AXP717_LDO_V_OUT_MASK,801 AXP717_LDO0_OUTPUT_CONTROL, BIT(0)),802 AXP_DESC(AXP717, ALDO2, "aldo2", "aldoin", 500, 3500, 100,803 AXP717_ALDO2_CONTROL, AXP717_LDO_V_OUT_MASK,804 AXP717_LDO0_OUTPUT_CONTROL, BIT(1)),805 AXP_DESC(AXP717, ALDO3, "aldo3", "aldoin", 500, 3500, 100,806 AXP717_ALDO3_CONTROL, AXP717_LDO_V_OUT_MASK,807 AXP717_LDO0_OUTPUT_CONTROL, BIT(2)),808 AXP_DESC(AXP717, ALDO4, "aldo4", "aldoin", 500, 3500, 100,809 AXP717_ALDO4_CONTROL, AXP717_LDO_V_OUT_MASK,810 AXP717_LDO0_OUTPUT_CONTROL, BIT(3)),811 AXP_DESC(AXP717, BLDO1, "bldo1", "bldoin", 500, 3500, 100,812 AXP717_BLDO1_CONTROL, AXP717_LDO_V_OUT_MASK,813 AXP717_LDO0_OUTPUT_CONTROL, BIT(4)),814 AXP_DESC(AXP717, BLDO2, "bldo2", "bldoin", 500, 3500, 100,815 AXP717_BLDO2_CONTROL, AXP717_LDO_V_OUT_MASK,816 AXP717_LDO0_OUTPUT_CONTROL, BIT(5)),817 AXP_DESC(AXP717, BLDO3, "bldo3", "bldoin", 500, 3500, 100,818 AXP717_BLDO3_CONTROL, AXP717_LDO_V_OUT_MASK,819 AXP717_LDO0_OUTPUT_CONTROL, BIT(6)),820 AXP_DESC(AXP717, BLDO4, "bldo4", "bldoin", 500, 3500, 100,821 AXP717_BLDO4_CONTROL, AXP717_LDO_V_OUT_MASK,822 AXP717_LDO0_OUTPUT_CONTROL, BIT(7)),823 AXP_DESC(AXP717, CLDO1, "cldo1", "cldoin", 500, 3500, 100,824 AXP717_CLDO1_CONTROL, AXP717_LDO_V_OUT_MASK,825 AXP717_LDO1_OUTPUT_CONTROL, BIT(0)),826 AXP_DESC(AXP717, CLDO2, "cldo2", "cldoin", 500, 3500, 100,827 AXP717_CLDO2_CONTROL, AXP717_LDO_V_OUT_MASK,828 AXP717_LDO1_OUTPUT_CONTROL, BIT(1)),829 AXP_DESC(AXP717, CLDO3, "cldo3", "cldoin", 500, 3500, 100,830 AXP717_CLDO3_CONTROL, AXP717_LDO_V_OUT_MASK,831 AXP717_LDO1_OUTPUT_CONTROL, BIT(2)),832 AXP_DESC(AXP717, CLDO4, "cldo4", "cldoin", 500, 3500, 100,833 AXP717_CLDO4_CONTROL, AXP717_LDO_V_OUT_MASK,834 AXP717_LDO1_OUTPUT_CONTROL, BIT(3)),835 AXP_DESC(AXP717, CPUSLDO, "cpusldo", "vin1", 500, 1400, 50,836 AXP717_CPUSLDO_CONTROL, AXP717_LDO_V_OUT_MASK,837 AXP717_LDO1_OUTPUT_CONTROL, BIT(4)),838 AXP_DESC(AXP717, BOOST, "boost", "vin1", 4550, 5510, 64,839 AXP717_BOOST_CONTROL, AXP717_BOOST_V_OUT_MASK,840 AXP717_MODULE_EN_CONTROL_2, BIT(4)),841};842 843/* DCDC ranges shared with AXP813 */844static const struct linear_range axp803_dcdc234_ranges[] = {845 REGULATOR_LINEAR_RANGE(500000,846 AXP803_DCDC234_500mV_START,847 AXP803_DCDC234_500mV_END,848 10000),849 REGULATOR_LINEAR_RANGE(1220000,850 AXP803_DCDC234_1220mV_START,851 AXP803_DCDC234_1220mV_END,852 20000),853};854 855static const struct linear_range axp803_dcdc5_ranges[] = {856 REGULATOR_LINEAR_RANGE(800000,857 AXP803_DCDC5_800mV_START,858 AXP803_DCDC5_800mV_END,859 10000),860 REGULATOR_LINEAR_RANGE(1140000,861 AXP803_DCDC5_1140mV_START,862 AXP803_DCDC5_1140mV_END,863 20000),864};865 866static const struct linear_range axp803_dcdc6_ranges[] = {867 REGULATOR_LINEAR_RANGE(600000,868 AXP803_DCDC6_600mV_START,869 AXP803_DCDC6_600mV_END,870 10000),871 REGULATOR_LINEAR_RANGE(1120000,872 AXP803_DCDC6_1120mV_START,873 AXP803_DCDC6_1120mV_END,874 20000),875};876 877/* AXP806's CLDO2 and AXP809's DLDO1 share the same range */878static const struct linear_range axp803_dldo2_ranges[] = {879 REGULATOR_LINEAR_RANGE(700000,880 AXP803_DLDO2_700mV_START,881 AXP803_DLDO2_700mV_END,882 100000),883 REGULATOR_LINEAR_RANGE(3400000,884 AXP803_DLDO2_3400mV_START,885 AXP803_DLDO2_3400mV_END,886 200000),887};888 889static const struct regulator_desc axp803_regulators[] = {890 AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,891 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,892 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),893 AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",894 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,895 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,896 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),897 AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",898 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,899 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,900 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),901 AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",902 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,903 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,904 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),905 AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",906 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,907 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,908 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),909 AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",910 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,911 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,912 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),913 /* secondary switchable output of DCDC1 */914 AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,915 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),916 AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,917 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,918 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),919 AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,920 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,921 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),922 AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,923 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,924 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),925 AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,926 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,927 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),928 AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",929 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,930 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,931 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),932 AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,933 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,934 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),935 AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,936 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,937 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),938 AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,939 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,940 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),941 AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,942 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,943 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),944 AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,945 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,946 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),947 AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,948 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,949 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),950 AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,951 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,952 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),953 AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,954 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,955 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,956 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),957 AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,958 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,959 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,960 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),961 AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),962};963 964static const struct linear_range axp806_dcdca_ranges[] = {965 REGULATOR_LINEAR_RANGE(600000,966 AXP806_DCDCA_600mV_START,967 AXP806_DCDCA_600mV_END,968 10000),969 REGULATOR_LINEAR_RANGE(1120000,970 AXP806_DCDCA_1120mV_START,971 AXP806_DCDCA_1120mV_END,972 20000),973};974 975static const struct linear_range axp806_dcdcd_ranges[] = {976 REGULATOR_LINEAR_RANGE(600000,977 AXP806_DCDCD_600mV_START,978 AXP806_DCDCD_600mV_END,979 20000),980 REGULATOR_LINEAR_RANGE(1600000,981 AXP806_DCDCD_1600mV_START,982 AXP806_DCDCD_1600mV_END,983 100000),984};985 986static const struct regulator_desc axp806_regulators[] = {987 AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",988 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,989 AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,990 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),991 AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,992 AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,993 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),994 AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",995 axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,996 AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,997 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),998 AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",999 axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,1000 AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,1001 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),1002 AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,1003 AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,1004 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),1005 AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,1006 AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,1007 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),1008 AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,1009 AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,1010 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),1011 AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,1012 AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,1013 AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),1014 AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,1015 AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,1016 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),1017 AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,1018 AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,1019 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),1020 AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,1021 AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,1022 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),1023 AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,1024 AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,1025 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),1026 AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,1027 AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,1028 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),1029 AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",1030 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,1031 AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,1032 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),1033 AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,1034 AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,1035 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),1036 AXP_DESC_SW(AXP806, SW, "sw", "swin",1037 AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),1038};1039 1040static const struct linear_range axp809_dcdc4_ranges[] = {1041 REGULATOR_LINEAR_RANGE(600000,1042 AXP809_DCDC4_600mV_START,1043 AXP809_DCDC4_600mV_END,1044 20000),1045 REGULATOR_LINEAR_RANGE(1800000,1046 AXP809_DCDC4_1800mV_START,1047 AXP809_DCDC4_1800mV_END,1048 100000),1049};1050 1051static const struct regulator_desc axp809_regulators[] = {1052 AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,1053 AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,1054 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),1055 AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,1056 AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,1057 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),1058 AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,1059 AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,1060 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),1061 AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",1062 axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,1063 AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,1064 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),1065 AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,1066 AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,1067 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),1068 /* secondary switchable output of DCDC1 */1069 AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,1070 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),1071 /* LDO regulator internally chained to DCDC5 */1072 AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,1073 AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,1074 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),1075 AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,1076 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,1077 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),1078 AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,1079 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,1080 AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),1081 AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,1082 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,1083 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),1084 AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",1085 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,1086 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,1087 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),1088 AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,1089 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,1090 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),1091 AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,1092 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,1093 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),1094 AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,1095 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,1096 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),1097 AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,1098 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,1099 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),1100 /*1101 * Note the datasheet only guarantees reliable operation up to1102 * 3.3V, this needs to be enforced via dts provided constraints1103 */1104 AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,1105 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,1106 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,1107 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),1108 /*1109 * Note the datasheet only guarantees reliable operation up to1110 * 3.3V, this needs to be enforced via dts provided constraints1111 */1112 AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,1113 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,1114 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,1115 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),1116 AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),1117 AXP_DESC_SW(AXP809, SW, "sw", "swin",1118 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),1119};1120 1121static const struct regulator_desc axp813_regulators[] = {1122 AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,1123 AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,1124 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),1125 AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",1126 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,1127 AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,1128 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),1129 AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",1130 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,1131 AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,1132 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),1133 AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",1134 axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,1135 AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,1136 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),1137 AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",1138 axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,1139 AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,1140 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),1141 AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",1142 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,1143 AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,1144 AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),1145 AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",1146 axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,1147 AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,1148 AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),1149 AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,1150 AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,1151 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),1152 AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,1153 AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,1154 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),1155 AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,1156 AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,1157 AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),1158 AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,1159 AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,1160 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),1161 AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",1162 axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,1163 AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,1164 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),1165 AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,1166 AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,1167 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),1168 AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,1169 AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,1170 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),1171 AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,1172 AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,1173 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),1174 AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,1175 AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,1176 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),1177 AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,1178 AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,1179 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),1180 /* to do / check ... */1181 AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,1182 AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,1183 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),1184 AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,1185 AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,1186 AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),1187 /*1188 * TODO: FLDO3 = {DCDC5, FLDOIN} / 21189 *1190 * This means FLDO3 effectively switches supplies at runtime,1191 * something the regulator subsystem does not support.1192 */1193 AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),1194 AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,1195 AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,1196 AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,1197 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),1198 AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,1199 AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,1200 AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,1201 AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),1202 AXP_DESC_SW(AXP813, SW, "sw", "swin",1203 AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),1204};1205 1206static const struct linear_range axp15060_dcdc234_ranges[] = {1207 REGULATOR_LINEAR_RANGE(500000,1208 AXP15060_DCDC234_500mV_START,1209 AXP15060_DCDC234_500mV_END,1210 10000),1211 REGULATOR_LINEAR_RANGE(1220000,1212 AXP15060_DCDC234_1220mV_START,1213 AXP15060_DCDC234_1220mV_END,1214 20000),1215};1216 1217static const struct linear_range axp15060_dcdc5_ranges[] = {1218 REGULATOR_LINEAR_RANGE(800000,1219 AXP15060_DCDC5_800mV_START,1220 AXP15060_DCDC5_800mV_END,1221 10000),1222 REGULATOR_LINEAR_RANGE(1140000,1223 AXP15060_DCDC5_1140mV_START,1224 AXP15060_DCDC5_1140mV_END,1225 20000),1226};1227 1228static const struct regulator_desc axp15060_regulators[] = {1229 AXP_DESC(AXP15060, DCDC1, "dcdc1", "vin1", 1500, 3400, 100,1230 AXP15060_DCDC1_V_CTRL, AXP15060_DCDC1_V_CTRL_MASK,1231 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC1_MASK),1232 AXP_DESC_RANGES(AXP15060, DCDC2, "dcdc2", "vin2",1233 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,1234 AXP15060_DCDC2_V_CTRL, AXP15060_DCDC2_V_CTRL_MASK,1235 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC2_MASK),1236 AXP_DESC_RANGES(AXP15060, DCDC3, "dcdc3", "vin3",1237 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,1238 AXP15060_DCDC3_V_CTRL, AXP15060_DCDC3_V_CTRL_MASK,1239 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC3_MASK),1240 AXP_DESC_RANGES(AXP15060, DCDC4, "dcdc4", "vin4",1241 axp15060_dcdc234_ranges, AXP15060_DCDC234_NUM_VOLTAGES,1242 AXP15060_DCDC4_V_CTRL, AXP15060_DCDC4_V_CTRL_MASK,1243 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC4_MASK),1244 AXP_DESC_RANGES(AXP15060, DCDC5, "dcdc5", "vin5",1245 axp15060_dcdc5_ranges, AXP15060_DCDC5_NUM_VOLTAGES,1246 AXP15060_DCDC5_V_CTRL, AXP15060_DCDC5_V_CTRL_MASK,1247 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC5_MASK),1248 AXP_DESC(AXP15060, DCDC6, "dcdc6", "vin6", 500, 3400, 100,1249 AXP15060_DCDC6_V_CTRL, AXP15060_DCDC6_V_CTRL_MASK,1250 AXP15060_PWR_OUT_CTRL1, AXP15060_PWR_OUT_DCDC6_MASK),1251 AXP_DESC(AXP15060, ALDO1, "aldo1", "aldoin", 700, 3300, 100,1252 AXP15060_ALDO1_V_CTRL, AXP15060_ALDO1_V_CTRL_MASK,1253 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO1_MASK),1254 AXP_DESC(AXP15060, ALDO2, "aldo2", "aldoin", 700, 3300, 100,1255 AXP15060_ALDO2_V_CTRL, AXP15060_ALDO2_V_CTRL_MASK,1256 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO2_MASK),1257 AXP_DESC(AXP15060, ALDO3, "aldo3", "aldoin", 700, 3300, 100,1258 AXP15060_ALDO3_V_CTRL, AXP15060_ALDO3_V_CTRL_MASK,1259 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO3_MASK),1260 AXP_DESC(AXP15060, ALDO4, "aldo4", "aldoin", 700, 3300, 100,1261 AXP15060_ALDO4_V_CTRL, AXP15060_ALDO4_V_CTRL_MASK,1262 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO4_MASK),1263 AXP_DESC(AXP15060, ALDO5, "aldo5", "aldoin", 700, 3300, 100,1264 AXP15060_ALDO5_V_CTRL, AXP15060_ALDO5_V_CTRL_MASK,1265 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_ALDO5_MASK),1266 AXP_DESC(AXP15060, BLDO1, "bldo1", "bldoin", 700, 3300, 100,1267 AXP15060_BLDO1_V_CTRL, AXP15060_BLDO1_V_CTRL_MASK,1268 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO1_MASK),1269 AXP_DESC(AXP15060, BLDO2, "bldo2", "bldoin", 700, 3300, 100,1270 AXP15060_BLDO2_V_CTRL, AXP15060_BLDO2_V_CTRL_MASK,1271 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO2_MASK),1272 AXP_DESC(AXP15060, BLDO3, "bldo3", "bldoin", 700, 3300, 100,1273 AXP15060_BLDO3_V_CTRL, AXP15060_BLDO3_V_CTRL_MASK,1274 AXP15060_PWR_OUT_CTRL2, AXP15060_PWR_OUT_BLDO3_MASK),1275 AXP_DESC(AXP15060, BLDO4, "bldo4", "bldoin", 700, 3300, 100,1276 AXP15060_BLDO4_V_CTRL, AXP15060_BLDO4_V_CTRL_MASK,1277 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO4_MASK),1278 AXP_DESC(AXP15060, BLDO5, "bldo5", "bldoin", 700, 3300, 100,1279 AXP15060_BLDO5_V_CTRL, AXP15060_BLDO5_V_CTRL_MASK,1280 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_BLDO5_MASK),1281 AXP_DESC(AXP15060, CLDO1, "cldo1", "cldoin", 700, 3300, 100,1282 AXP15060_CLDO1_V_CTRL, AXP15060_CLDO1_V_CTRL_MASK,1283 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO1_MASK),1284 AXP_DESC(AXP15060, CLDO2, "cldo2", "cldoin", 700, 3300, 100,1285 AXP15060_CLDO2_V_CTRL, AXP15060_CLDO2_V_CTRL_MASK,1286 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO2_MASK),1287 AXP_DESC(AXP15060, CLDO3, "cldo3", "cldoin", 700, 3300, 100,1288 AXP15060_CLDO3_V_CTRL, AXP15060_CLDO3_V_CTRL_MASK,1289 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO3_MASK),1290 AXP_DESC(AXP15060, CLDO4, "cldo4", "cldoin", 700, 4200, 100,1291 AXP15060_CLDO4_V_CTRL, AXP15060_CLDO4_V_CTRL_MASK,1292 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CLDO4_MASK),1293 /* Supply comes from DCDC5 */1294 AXP_DESC(AXP15060, CPUSLDO, "cpusldo", NULL, 700, 1400, 50,1295 AXP15060_CPUSLDO_V_CTRL, AXP15060_CPUSLDO_V_CTRL_MASK,1296 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_CPUSLDO_MASK),1297 /* Supply comes from DCDC1 */1298 AXP_DESC_SW(AXP15060, SW, "sw", NULL,1299 AXP15060_PWR_OUT_CTRL3, AXP15060_PWR_OUT_SW_MASK),1300 /* Supply comes from ALDO1 */1301 AXP_DESC_FIXED(AXP15060, RTC_LDO, "rtc-ldo", NULL, 1800),1302};1303 1304static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)1305{1306 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);1307 unsigned int reg = AXP20X_DCDC_FREQ;1308 u32 min, max, def, step;1309 1310 switch (axp20x->variant) {1311 case AXP202_ID:1312 case AXP209_ID:1313 min = 750;1314 max = 1875;1315 def = 1500;1316 step = 75;1317 break;1318 case AXP803_ID:1319 case AXP813_ID:1320 /*1321 * AXP803/AXP813 DCDC work frequency setting has the same1322 * range and step as AXP22X, but at a different register.1323 * (See include/linux/mfd/axp20x.h)1324 */1325 reg = AXP803_DCDC_FREQ_CTRL;1326 fallthrough; /* to the check below */1327 case AXP806_ID:1328 /*1329 * AXP806 also have DCDC work frequency setting register at a1330 * different position.1331 */1332 if (axp20x->variant == AXP806_ID)1333 reg = AXP806_DCDC_FREQ_CTRL;1334 fallthrough;1335 case AXP221_ID:1336 case AXP223_ID:1337 case AXP809_ID:1338 min = 1800;1339 max = 4050;1340 def = 3000;1341 step = 150;1342 break;1343 case AXP313A_ID:1344 case AXP717_ID:1345 case AXP15060_ID:1346 /* The DCDC PWM frequency seems to be fixed to 3 MHz. */1347 if (dcdcfreq != 0) {1348 dev_err(&pdev->dev,1349 "DCDC frequency on this PMIC is fixed to 3 MHz.\n");1350 return -EINVAL;1351 }1352 1353 return 0;1354 default:1355 dev_err(&pdev->dev,1356 "Setting DCDC frequency for unsupported AXP variant\n");1357 return -EINVAL;1358 }1359 1360 if (dcdcfreq == 0)1361 dcdcfreq = def;1362 1363 if (dcdcfreq < min) {1364 dcdcfreq = min;1365 dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",1366 min);1367 }1368 1369 if (dcdcfreq > max) {1370 dcdcfreq = max;1371 dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",1372 max);1373 }1374 1375 dcdcfreq = (dcdcfreq - min) / step;1376 1377 return regmap_update_bits(axp20x->regmap, reg,1378 AXP20X_FREQ_DCDC_MASK, dcdcfreq);1379}1380 1381static int axp20x_regulator_parse_dt(struct platform_device *pdev)1382{1383 struct device_node *np, *regulators;1384 int ret = 0;1385 u32 dcdcfreq = 0;1386 1387 np = of_node_get(pdev->dev.parent->of_node);1388 if (!np)1389 return 0;1390 1391 regulators = of_get_child_by_name(np, "regulators");1392 if (!regulators) {1393 dev_warn(&pdev->dev, "regulators node not found\n");1394 } else {1395 of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);1396 ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);1397 if (ret < 0) {1398 dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);1399 }1400 of_node_put(regulators);1401 }1402 1403 of_node_put(np);1404 return ret;1405}1406 1407static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)1408{1409 struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);1410 unsigned int reg = AXP20X_DCDC_MODE;1411 unsigned int mask;1412 1413 switch (axp20x->variant) {1414 case AXP202_ID:1415 case AXP209_ID:1416 if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))1417 return -EINVAL;1418 1419 mask = AXP20X_WORKMODE_DCDC2_MASK;1420 if (id == AXP20X_DCDC3)1421 mask = AXP20X_WORKMODE_DCDC3_MASK;1422 1423 workmode <<= ffs(mask) - 1;1424 break;1425 1426 case AXP806_ID:1427 /*1428 * AXP806 DCDC regulator IDs have the same range as AXP22X.1429 * (See include/linux/mfd/axp20x.h)1430 */1431 reg = AXP806_DCDC_MODE_CTRL2;1432 fallthrough; /* to the check below */1433 case AXP221_ID:1434 case AXP223_ID:1435 case AXP809_ID:1436 if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)1437 return -EINVAL;1438 1439 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);1440 workmode <<= id - AXP22X_DCDC1;1441 break;1442 1443 case AXP803_ID:1444 if (id < AXP803_DCDC1 || id > AXP803_DCDC6)1445 return -EINVAL;1446 1447 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1);1448 workmode <<= id - AXP803_DCDC1;1449 break;1450 1451 case AXP813_ID:1452 if (id < AXP813_DCDC1 || id > AXP813_DCDC7)1453 return -EINVAL;1454 1455 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1);1456 workmode <<= id - AXP813_DCDC1;1457 break;1458 1459 case AXP15060_ID:1460 reg = AXP15060_DCDC_MODE_CTRL2;1461 if (id < AXP15060_DCDC1 || id > AXP15060_DCDC6)1462 return -EINVAL;1463 1464 mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP15060_DCDC1);1465 workmode <<= id - AXP15060_DCDC1;1466 break;1467 1468 default:1469 /* should not happen */1470 WARN_ON(1);1471 return -EINVAL;1472 }1473 1474 return regmap_update_bits(rdev->regmap, reg, mask, workmode);1475}1476 1477/*1478 * This function checks whether a regulator is part of a poly-phase1479 * output setup based on the registers settings. Returns true if it is.1480 */1481static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)1482{1483 u32 reg = 0;1484 1485 /*1486 * Currently in our supported AXP variants, only AXP803, AXP806,1487 * AXP813 and AXP15060 have polyphase regulators.1488 */1489 switch (axp20x->variant) {1490 case AXP803_ID:1491 case AXP813_ID:1492 regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, ®);1493 1494 switch (id) {1495 case AXP803_DCDC3:1496 return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);1497 case AXP803_DCDC6:1498 return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);1499 }1500 break;1501 1502 case AXP806_ID:1503 regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®);1504 1505 switch (id) {1506 case AXP806_DCDCB:1507 return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==1508 AXP806_DCDCAB_POLYPHASE_DUAL) ||1509 ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==1510 AXP806_DCDCABC_POLYPHASE_TRI));1511 case AXP806_DCDCC:1512 return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==1513 AXP806_DCDCABC_POLYPHASE_TRI);1514 case AXP806_DCDCE:1515 return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);1516 }1517 break;1518 1519 case AXP15060_ID:1520 regmap_read(axp20x->regmap, AXP15060_DCDC_MODE_CTRL1, ®);1521 1522 switch (id) {1523 case AXP15060_DCDC3:1524 return !!(reg & AXP15060_DCDC23_POLYPHASE_DUAL_MASK);1525 case AXP15060_DCDC6:1526 return !!(reg & AXP15060_DCDC46_POLYPHASE_DUAL_MASK);1527 }1528 break;1529 1530 default:1531 return false;1532 }1533 1534 return false;1535}1536 1537static int axp20x_regulator_probe(struct platform_device *pdev)1538{1539 struct regulator_dev *rdev;1540 struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);1541 const struct regulator_desc *regulators;1542 struct regulator_config config = {1543 .dev = pdev->dev.parent,1544 .regmap = axp20x->regmap,1545 .driver_data = axp20x,1546 };1547 int ret, i, nregulators;1548 u32 workmode;1549 const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;1550 const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;1551 const char *aldo1_name = axp15060_regulators[AXP15060_ALDO1].name;1552 bool drivevbus = false;1553 1554 switch (axp20x->variant) {1555 case AXP202_ID:1556 case AXP209_ID:1557 regulators = axp20x_regulators;1558 nregulators = AXP20X_REG_ID_MAX;1559 break;1560 case AXP221_ID:1561 case AXP223_ID:1562 regulators = axp22x_regulators;1563 nregulators = AXP22X_REG_ID_MAX;1564 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,1565 "x-powers,drive-vbus-en");1566 break;1567 case AXP313A_ID:1568 regulators = axp313a_regulators;1569 nregulators = AXP313A_REG_ID_MAX;1570 break;1571 case AXP717_ID:1572 regulators = axp717_regulators;1573 nregulators = AXP717_REG_ID_MAX;1574 break;1575 case AXP803_ID:1576 regulators = axp803_regulators;1577 nregulators = AXP803_REG_ID_MAX;1578 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,1579 "x-powers,drive-vbus-en");1580 break;1581 case AXP806_ID:1582 regulators = axp806_regulators;1583 nregulators = AXP806_REG_ID_MAX;1584 break;1585 case AXP809_ID:1586 regulators = axp809_regulators;1587 nregulators = AXP809_REG_ID_MAX;1588 break;1589 case AXP813_ID:1590 regulators = axp813_regulators;1591 nregulators = AXP813_REG_ID_MAX;1592 drivevbus = of_property_read_bool(pdev->dev.parent->of_node,1593 "x-powers,drive-vbus-en");1594 break;1595 case AXP15060_ID:1596 regulators = axp15060_regulators;1597 nregulators = AXP15060_REG_ID_MAX;1598 break;1599 default:1600 dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",1601 axp20x->variant);1602 return -EINVAL;1603 }1604 1605 /* This only sets the dcdc freq. Ignore any errors */1606 axp20x_regulator_parse_dt(pdev);1607 1608 for (i = 0; i < nregulators; i++) {1609 const struct regulator_desc *desc = ®ulators[i];1610 struct regulator_desc *new_desc;1611 1612 /*1613 * If this regulator is a slave in a poly-phase setup,1614 * skip it, as its controls are bound to the master1615 * regulator and won't work.1616 */1617 if (axp20x_is_polyphase_slave(axp20x, i))1618 continue;1619 1620 /* Support for AXP813's FLDO3 is not implemented */1621 if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3)1622 continue;1623 1624 /*1625 * Regulators DC1SW, DC5LDO and RTCLDO on AXP15060 are1626 * connected internally, so we have to handle their supply1627 * names separately.1628 *1629 * We always register the regulators in proper sequence,1630 * so the supply names are correctly read. See the last1631 * part of this loop to see where we save the DT defined1632 * name.1633 */1634 if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||1635 (regulators == axp803_regulators && i == AXP803_DC1SW) ||1636 (regulators == axp809_regulators && i == AXP809_DC1SW) ||1637 (regulators == axp15060_regulators && i == AXP15060_SW)) {1638 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),1639 GFP_KERNEL);1640 if (!new_desc)1641 return -ENOMEM;1642 1643 *new_desc = regulators[i];1644 new_desc->supply_name = dcdc1_name;1645 desc = new_desc;1646 }1647 1648 if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||1649 (regulators == axp809_regulators && i == AXP809_DC5LDO) ||1650 (regulators == axp15060_regulators && i == AXP15060_CPUSLDO)) {1651 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),1652 GFP_KERNEL);1653 if (!new_desc)1654 return -ENOMEM;1655 1656 *new_desc = regulators[i];1657 new_desc->supply_name = dcdc5_name;1658 desc = new_desc;1659 }1660 1661 1662 if (regulators == axp15060_regulators && i == AXP15060_RTC_LDO) {1663 new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),1664 GFP_KERNEL);1665 if (!new_desc)1666 return -ENOMEM;1667 1668 *new_desc = regulators[i];1669 new_desc->supply_name = aldo1_name;1670 desc = new_desc;1671 }1672 1673 rdev = devm_regulator_register(&pdev->dev, desc, &config);1674 if (IS_ERR(rdev)) {1675 dev_err(&pdev->dev, "Failed to register %s\n",1676 regulators[i].name);1677 1678 return PTR_ERR(rdev);1679 }1680 1681 ret = of_property_read_u32(rdev->dev.of_node,1682 "x-powers,dcdc-workmode",1683 &workmode);1684 if (!ret) {1685 if (axp20x_set_dcdc_workmode(rdev, i, workmode))1686 dev_err(&pdev->dev, "Failed to set workmode on %s\n",1687 rdev->desc->name);1688 }1689 1690 /*1691 * Save AXP22X DCDC1 / DCDC5 / AXP15060 ALDO1 regulator names for later.1692 */1693 if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||1694 (regulators == axp809_regulators && i == AXP809_DCDC1) ||1695 (regulators == axp15060_regulators && i == AXP15060_DCDC1))1696 of_property_read_string(rdev->dev.of_node,1697 "regulator-name",1698 &dcdc1_name);1699 1700 if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||1701 (regulators == axp809_regulators && i == AXP809_DCDC5) ||1702 (regulators == axp15060_regulators && i == AXP15060_DCDC5))1703 of_property_read_string(rdev->dev.of_node,1704 "regulator-name",1705 &dcdc5_name);1706 1707 if (regulators == axp15060_regulators && i == AXP15060_ALDO1)1708 of_property_read_string(rdev->dev.of_node,1709 "regulator-name",1710 &aldo1_name);1711 }1712 1713 if (drivevbus) {1714 /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */1715 regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,1716 AXP22X_MISC_N_VBUSEN_FUNC, 0);1717 rdev = devm_regulator_register(&pdev->dev,1718 &axp22x_drivevbus_regulator,1719 &config);1720 if (IS_ERR(rdev)) {1721 dev_err(&pdev->dev, "Failed to register drivevbus\n");1722 return PTR_ERR(rdev);1723 }1724 }1725 1726 return 0;1727}1728 1729static struct platform_driver axp20x_regulator_driver = {1730 .probe = axp20x_regulator_probe,1731 .driver = {1732 .name = "axp20x-regulator",1733 .probe_type = PROBE_PREFER_ASYNCHRONOUS,1734 },1735};1736 1737module_platform_driver(axp20x_regulator_driver);1738 1739MODULE_LICENSE("GPL v2");1740MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");1741MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");1742MODULE_ALIAS("platform:axp20x-regulator");1743