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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2015 MediaTek Inc.4 * Author: Henry Chen <henryc.chen@mediatek.com>5 */6 7#ifndef __MT6311_REGULATOR_H__8#define __MT6311_REGULATOR_H__9 10#define MT6311_SWCID 0x0111 12#define MT6311_TOP_INT_CON 0x1813#define MT6311_TOP_INT_MON 0x1914 15#define MT6311_VDVFS11_CON0 0x8716#define MT6311_VDVFS11_CON7 0x8817#define MT6311_VDVFS11_CON8 0x8918#define MT6311_VDVFS11_CON9 0x8A19#define MT6311_VDVFS11_CON10 0x8B20#define MT6311_VDVFS11_CON11 0x8C21#define MT6311_VDVFS11_CON12 0x8D22#define MT6311_VDVFS11_CON13 0x8E23#define MT6311_VDVFS11_CON14 0x8F24#define MT6311_VDVFS11_CON15 0x9025#define MT6311_VDVFS11_CON16 0x9126#define MT6311_VDVFS11_CON17 0x9227#define MT6311_VDVFS11_CON18 0x9328#define MT6311_VDVFS11_CON19 0x9429 30#define MT6311_LDO_CON0 0xCC31#define MT6311_LDO_OCFB0 0xCD32#define MT6311_LDO_CON2 0xCE33#define MT6311_LDO_CON3 0xCF34#define MT6311_LDO_CON4 0xD035#define MT6311_FQMTR_CON0 0xD136#define MT6311_FQMTR_CON1 0xD237#define MT6311_FQMTR_CON2 0xD338#define MT6311_FQMTR_CON3 0xD439#define MT6311_FQMTR_CON4 0xD540 41#define MT6311_PMIC_RG_INT_POL_MASK 0x142#define MT6311_PMIC_RG_INT_EN_MASK 0x243#define MT6311_PMIC_RG_BUCK_OC_INT_STATUS_MASK 0x1044 45#define MT6311_PMIC_VDVFS11_EN_CTRL_MASK 0x146#define MT6311_PMIC_VDVFS11_VOSEL_CTRL_MASK 0x247#define MT6311_PMIC_VDVFS11_EN_SEL_MASK 0x348#define MT6311_PMIC_VDVFS11_VOSEL_SEL_MASK 0xc49#define MT6311_PMIC_VDVFS11_EN_MASK 0x150#define MT6311_PMIC_VDVFS11_VOSEL_MASK 0x7F51#define MT6311_PMIC_VDVFS11_VOSEL_ON_MASK 0x7F52#define MT6311_PMIC_VDVFS11_VOSEL_SLEEP_MASK 0x7F53#define MT6311_PMIC_NI_VDVFS11_VOSEL_MASK 0x7F54 55#define MT6311_PMIC_RG_VBIASN_EN_MASK 0x156 57#endif58