506 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * SLG51000 High PSRR, Multi-Output Regulators4 * Copyright (C) 2019 Dialog Semiconductor5 *6 * Author: Eric Jeong <eric.jeong.opensource@diasemi.com>7 */8 9#ifndef __SLG51000_REGISTERS_H__10#define __SLG51000_REGISTERS_H__11 12/* Registers */13 14#define SLG51000_SYSCTL_PATN_ID_B0 0x110515#define SLG51000_SYSCTL_PATN_ID_B1 0x110616#define SLG51000_SYSCTL_PATN_ID_B2 0x110717#define SLG51000_SYSCTL_SYS_CONF_A 0x110918#define SLG51000_SYSCTL_SYS_CONF_D 0x110c19#define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d20#define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e21#define SLG51000_SYSCTL_REFGEN_CONF_C 0x111122#define SLG51000_SYSCTL_UVLO_CONF_A 0x111223#define SLG51000_SYSCTL_FAULT_LOG1 0x111524#define SLG51000_SYSCTL_EVENT 0x111625#define SLG51000_SYSCTL_STATUS 0x111726#define SLG51000_SYSCTL_IRQ_MASK 0x111827#define SLG51000_IO_GPIO1_CONF 0x150028#define SLG51000_IO_GPIO2_CONF 0x150129#define SLG51000_IO_GPIO3_CONF 0x150230#define SLG51000_IO_GPIO4_CONF 0x150331#define SLG51000_IO_GPIO5_CONF 0x150432#define SLG51000_IO_GPIO6_CONF 0x150533#define SLG51000_IO_GPIO_STATUS 0x150634#define SLG51000_LUTARRAY_LUT_VAL_0 0x160035#define SLG51000_LUTARRAY_LUT_VAL_1 0x160136#define SLG51000_LUTARRAY_LUT_VAL_2 0x160237#define SLG51000_LUTARRAY_LUT_VAL_3 0x160338#define SLG51000_LUTARRAY_LUT_VAL_4 0x160439#define SLG51000_LUTARRAY_LUT_VAL_5 0x160540#define SLG51000_LUTARRAY_LUT_VAL_6 0x160641#define SLG51000_LUTARRAY_LUT_VAL_7 0x160742#define SLG51000_LUTARRAY_LUT_VAL_8 0x160843#define SLG51000_LUTARRAY_LUT_VAL_9 0x160944#define SLG51000_LUTARRAY_LUT_VAL_10 0x160a45#define SLG51000_LUTARRAY_LUT_VAL_11 0x160b46#define SLG51000_MUXARRAY_INPUT_SEL_0 0x170047#define SLG51000_MUXARRAY_INPUT_SEL_1 0x170148#define SLG51000_MUXARRAY_INPUT_SEL_2 0x170249#define SLG51000_MUXARRAY_INPUT_SEL_3 0x170350#define SLG51000_MUXARRAY_INPUT_SEL_4 0x170451#define SLG51000_MUXARRAY_INPUT_SEL_5 0x170552#define SLG51000_MUXARRAY_INPUT_SEL_6 0x170653#define SLG51000_MUXARRAY_INPUT_SEL_7 0x170754#define SLG51000_MUXARRAY_INPUT_SEL_8 0x170855#define SLG51000_MUXARRAY_INPUT_SEL_9 0x170956#define SLG51000_MUXARRAY_INPUT_SEL_10 0x170a57#define SLG51000_MUXARRAY_INPUT_SEL_11 0x170b58#define SLG51000_MUXARRAY_INPUT_SEL_12 0x170c59#define SLG51000_MUXARRAY_INPUT_SEL_13 0x170d60#define SLG51000_MUXARRAY_INPUT_SEL_14 0x170e61#define SLG51000_MUXARRAY_INPUT_SEL_15 0x170f62#define SLG51000_MUXARRAY_INPUT_SEL_16 0x171063#define SLG51000_MUXARRAY_INPUT_SEL_17 0x171164#define SLG51000_MUXARRAY_INPUT_SEL_18 0x171265#define SLG51000_MUXARRAY_INPUT_SEL_19 0x171366#define SLG51000_MUXARRAY_INPUT_SEL_20 0x171467#define SLG51000_MUXARRAY_INPUT_SEL_21 0x171568#define SLG51000_MUXARRAY_INPUT_SEL_22 0x171669#define SLG51000_MUXARRAY_INPUT_SEL_23 0x171770#define SLG51000_MUXARRAY_INPUT_SEL_24 0x171871#define SLG51000_MUXARRAY_INPUT_SEL_25 0x171972#define SLG51000_MUXARRAY_INPUT_SEL_26 0x171a73#define SLG51000_MUXARRAY_INPUT_SEL_27 0x171b74#define SLG51000_MUXARRAY_INPUT_SEL_28 0x171c75#define SLG51000_MUXARRAY_INPUT_SEL_29 0x171d76#define SLG51000_MUXARRAY_INPUT_SEL_30 0x171e77#define SLG51000_MUXARRAY_INPUT_SEL_31 0x171f78#define SLG51000_MUXARRAY_INPUT_SEL_32 0x172079#define SLG51000_MUXARRAY_INPUT_SEL_33 0x172180#define SLG51000_MUXARRAY_INPUT_SEL_34 0x172281#define SLG51000_MUXARRAY_INPUT_SEL_35 0x172382#define SLG51000_MUXARRAY_INPUT_SEL_36 0x172483#define SLG51000_MUXARRAY_INPUT_SEL_37 0x172584#define SLG51000_MUXARRAY_INPUT_SEL_38 0x172685#define SLG51000_MUXARRAY_INPUT_SEL_39 0x172786#define SLG51000_MUXARRAY_INPUT_SEL_40 0x172887#define SLG51000_MUXARRAY_INPUT_SEL_41 0x172988#define SLG51000_MUXARRAY_INPUT_SEL_42 0x172a89#define SLG51000_MUXARRAY_INPUT_SEL_43 0x172b90#define SLG51000_MUXARRAY_INPUT_SEL_44 0x172c91#define SLG51000_MUXARRAY_INPUT_SEL_45 0x172d92#define SLG51000_MUXARRAY_INPUT_SEL_46 0x172e93#define SLG51000_MUXARRAY_INPUT_SEL_47 0x172f94#define SLG51000_MUXARRAY_INPUT_SEL_48 0x173095#define SLG51000_MUXARRAY_INPUT_SEL_49 0x173196#define SLG51000_MUXARRAY_INPUT_SEL_50 0x173297#define SLG51000_MUXARRAY_INPUT_SEL_51 0x173398#define SLG51000_MUXARRAY_INPUT_SEL_52 0x173499#define SLG51000_MUXARRAY_INPUT_SEL_53 0x1735100#define SLG51000_MUXARRAY_INPUT_SEL_54 0x1736101#define SLG51000_MUXARRAY_INPUT_SEL_55 0x1737102#define SLG51000_MUXARRAY_INPUT_SEL_56 0x1738103#define SLG51000_MUXARRAY_INPUT_SEL_57 0x1739104#define SLG51000_MUXARRAY_INPUT_SEL_58 0x173a105#define SLG51000_MUXARRAY_INPUT_SEL_59 0x173b106#define SLG51000_MUXARRAY_INPUT_SEL_60 0x173c107#define SLG51000_MUXARRAY_INPUT_SEL_61 0x173d108#define SLG51000_MUXARRAY_INPUT_SEL_62 0x173e109#define SLG51000_MUXARRAY_INPUT_SEL_63 0x173f110#define SLG51000_PWRSEQ_RESOURCE_EN_0 0x1900111#define SLG51000_PWRSEQ_RESOURCE_EN_1 0x1901112#define SLG51000_PWRSEQ_RESOURCE_EN_2 0x1902113#define SLG51000_PWRSEQ_RESOURCE_EN_3 0x1903114#define SLG51000_PWRSEQ_RESOURCE_EN_4 0x1904115#define SLG51000_PWRSEQ_RESOURCE_EN_5 0x1905116#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 0x1906117#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 0x1907118#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP1 0x1908119#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN1 0x1909120#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP2 0x190a121#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN2 0x190b122#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP3 0x190c123#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN3 0x190d124#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP4 0x190e125#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN4 0x190f126#define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5 0x1910127#define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5 0x1911128#define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A 0x1912129#define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_B 0x1913130#define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C 0x1914131#define SLG51000_PWRSEQ_INPUT_SENSE_CONF_A 0x1915132#define SLG51000_PWRSEQ_INPUT_SENSE_CONF_B 0x1916133#define SLG51000_LDO1_VSEL 0x2000134#define SLG51000_LDO1_MINV 0x2060135#define SLG51000_LDO1_MAXV 0x2061136#define SLG51000_LDO1_MISC1 0x2064137#define SLG51000_LDO1_VSEL_ACTUAL 0x2065138#define SLG51000_LDO1_EVENT 0x20c0139#define SLG51000_LDO1_STATUS 0x20c1140#define SLG51000_LDO1_IRQ_MASK 0x20c2141#define SLG51000_LDO2_VSEL 0x2200142#define SLG51000_LDO2_MINV 0x2260143#define SLG51000_LDO2_MAXV 0x2261144#define SLG51000_LDO2_MISC1 0x2264145#define SLG51000_LDO2_VSEL_ACTUAL 0x2265146#define SLG51000_LDO2_EVENT 0x22c0147#define SLG51000_LDO2_STATUS 0x22c1148#define SLG51000_LDO2_IRQ_MASK 0x22c2149#define SLG51000_LDO3_VSEL 0x2300150#define SLG51000_LDO3_MINV 0x2360151#define SLG51000_LDO3_MAXV 0x2361152#define SLG51000_LDO3_CONF1 0x2364153#define SLG51000_LDO3_CONF2 0x2365154#define SLG51000_LDO3_VSEL_ACTUAL 0x2366155#define SLG51000_LDO3_EVENT 0x23c0156#define SLG51000_LDO3_STATUS 0x23c1157#define SLG51000_LDO3_IRQ_MASK 0x23c2158#define SLG51000_LDO4_VSEL 0x2500159#define SLG51000_LDO4_MINV 0x2560160#define SLG51000_LDO4_MAXV 0x2561161#define SLG51000_LDO4_CONF1 0x2564162#define SLG51000_LDO4_CONF2 0x2565163#define SLG51000_LDO4_VSEL_ACTUAL 0x2566164#define SLG51000_LDO4_EVENT 0x25c0165#define SLG51000_LDO4_STATUS 0x25c1166#define SLG51000_LDO4_IRQ_MASK 0x25c2167#define SLG51000_LDO5_VSEL 0x2700168#define SLG51000_LDO5_MINV 0x2760169#define SLG51000_LDO5_MAXV 0x2761170#define SLG51000_LDO5_TRIM2 0x2763171#define SLG51000_LDO5_CONF1 0x2765172#define SLG51000_LDO5_CONF2 0x2766173#define SLG51000_LDO5_VSEL_ACTUAL 0x2767174#define SLG51000_LDO5_EVENT 0x27c0175#define SLG51000_LDO5_STATUS 0x27c1176#define SLG51000_LDO5_IRQ_MASK 0x27c2177#define SLG51000_LDO6_VSEL 0x2900178#define SLG51000_LDO6_MINV 0x2960179#define SLG51000_LDO6_MAXV 0x2961180#define SLG51000_LDO6_TRIM2 0x2963181#define SLG51000_LDO6_CONF1 0x2965182#define SLG51000_LDO6_CONF2 0x2966183#define SLG51000_LDO6_VSEL_ACTUAL 0x2967184#define SLG51000_LDO6_EVENT 0x29c0185#define SLG51000_LDO6_STATUS 0x29c1186#define SLG51000_LDO6_IRQ_MASK 0x29c2187#define SLG51000_LDO7_VSEL 0x3100188#define SLG51000_LDO7_MINV 0x3160189#define SLG51000_LDO7_MAXV 0x3161190#define SLG51000_LDO7_CONF1 0x3164191#define SLG51000_LDO7_CONF2 0x3165192#define SLG51000_LDO7_VSEL_ACTUAL 0x3166193#define SLG51000_LDO7_EVENT 0x31c0194#define SLG51000_LDO7_STATUS 0x31c1195#define SLG51000_LDO7_IRQ_MASK 0x31c2196#define SLG51000_OTP_EVENT 0x782b197#define SLG51000_OTP_IRQ_MASK 0x782d198#define SLG51000_OTP_LOCK_OTP_PROG 0x78fe199#define SLG51000_OTP_LOCK_CTRL 0x78ff200#define SLG51000_LOCK_GLOBAL_LOCK_CTRL1 0x8000201 202/* Register Bit Fields */203 204/* SLG51000_SYSCTL_PATTERN_ID_BYTE0 = 0x1105 */205#define SLG51000_PATTERN_ID_BYTE0_SHIFT 0206#define SLG51000_PATTERN_ID_BYTE0_MASK (0xff << 0)207 208/* SLG51000_SYSCTL_PATTERN_ID_BYTE1 = 0x1106 */209#define SLG51000_PATTERN_ID_BYTE1_SHIFT 0210#define SLG51000_PATTERN_ID_BYTE1_MASK (0xff << 0)211 212/* SLG51000_SYSCTL_PATTERN_ID_BYTE2 = 0x1107 */213#define SLG51000_PATTERN_ID_BYTE2_SHIFT 0214#define SLG51000_PATTERN_ID_BYTE2_MASK (0xff << 0)215 216/* SLG51000_SYSCTL_SYS_CONF_A = 0x1109 */217#define SLG51000_I2C_ADDRESS_SHIFT 0218#define SLG51000_I2C_ADDRESS_MASK (0x7f << 0)219#define SLG51000_I2C_DISABLE_SHIFT 7220#define SLG51000_I2C_DISABLE_MASK (0x01 << 7)221 222/* SLG51000_SYSCTL_SYS_CONF_D = 0x110c */223#define SLG51000_CS_T_DEB_SHIFT 6224#define SLG51000_CS_T_DEB_MASK (0x03 << 6)225#define SLG51000_I2C_CLR_MODE_SHIFT 5226#define SLG51000_I2C_CLR_MODE_MASK (0x01 << 5)227 228/* SLG51000_SYSCTL_MATRIX_CTRL_CONF_A = 0x110d */229#define SLG51000_RESOURCE_CTRL_SHIFT 0230#define SLG51000_RESOURCE_CTRL_MASK (0xff << 0)231 232/* SLG51000_SYSCTL_MATRIX_CTRL_CONF_B = 0x110e */233#define SLG51000_MATRIX_EVENT_SENSE_SHIFT 0234#define SLG51000_MATRIX_EVENT_SENSE_MASK (0x07 << 0)235 236/* SLG51000_SYSCTL_REFGEN_CONF_C = 0x1111 */237#define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_SHIFT 2238#define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_MASK (0x03 << 2)239#define SLG51000_REFGEN_SEL_TEMP_WARN_THR_SHIFT 0240#define SLG51000_REFGEN_SEL_TEMP_WARN_THR_MASK (0x03 << 0)241 242/* SLG51000_SYSCTL_UVLO_CONF_A = 0x1112 */243#define SLG51000_VMON_UVLO_SEL_THR_SHIFT 0244#define SLG51000_VMON_UVLO_SEL_THR_MASK (0x1f << 0)245 246/* SLG51000_SYSCTL_FAULT_LOG1 = 0x1115 */247#define SLG51000_FLT_POR_SHIFT 5248#define SLG51000_FLT_POR_MASK (0x01 << 5)249#define SLG51000_FLT_RST_SHIFT 4250#define SLG51000_FLT_RST_MASK (0x01 << 4)251#define SLG51000_FLT_POWER_SEQ_CRASH_REQ_SHIFT 2252#define SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK (0x01 << 2)253#define SLG51000_FLT_OVER_TEMP_SHIFT 1254#define SLG51000_FLT_OVER_TEMP_MASK (0x01 << 1)255 256/* SLG51000_SYSCTL_EVENT = 0x1116 */257#define SLG51000_EVT_MATRIX_SHIFT 1258#define SLG51000_EVT_MATRIX_MASK (0x01 << 1)259#define SLG51000_EVT_HIGH_TEMP_WARN_SHIFT 0260#define SLG51000_EVT_HIGH_TEMP_WARN_MASK (0x01 << 0)261 262/* SLG51000_SYSCTL_STATUS = 0x1117 */263#define SLG51000_STA_MATRIX_SHIFT 1264#define SLG51000_STA_MATRIX_MASK (0x01 << 1)265#define SLG51000_STA_HIGH_TEMP_WARN_SHIFT 0266#define SLG51000_STA_HIGH_TEMP_WARN_MASK (0x01 << 0)267 268/* SLG51000_SYSCTL_IRQ_MASK = 0x1118 */269#define SLG51000_IRQ_MATRIX_SHIFT 1270#define SLG51000_IRQ_MATRIX_MASK (0x01 << 1)271#define SLG51000_IRQ_HIGH_TEMP_WARN_SHIFT 0272#define SLG51000_IRQ_HIGH_TEMP_WARN_MASK (0x01 << 0)273 274/* SLG51000_IO_GPIO1_CONF ~ SLG51000_IO_GPIO5_CONF =275 * 0x1500, 0x1501, 0x1502, 0x1503, 0x1504276 */277#define SLG51000_GPIO_DIR_SHIFT 7278#define SLG51000_GPIO_DIR_MASK (0x01 << 7)279#define SLG51000_GPIO_SENS_SHIFT 5280#define SLG51000_GPIO_SENS_MASK (0x03 << 5)281#define SLG51000_GPIO_INVERT_SHIFT 4282#define SLG51000_GPIO_INVERT_MASK (0x01 << 4)283#define SLG51000_GPIO_BYP_SHIFT 3284#define SLG51000_GPIO_BYP_MASK (0x01 << 3)285#define SLG51000_GPIO_T_DEB_SHIFT 1286#define SLG51000_GPIO_T_DEB_MASK (0x03 << 1)287#define SLG51000_GPIO_LEVEL_SHIFT 0288#define SLG51000_GPIO_LEVEL_MASK (0x01 << 0)289 290/* SLG51000_IO_GPIO6_CONF = 0x1505 */291#define SLG51000_GPIO6_SENS_SHIFT 5292#define SLG51000_GPIO6_SENS_MASK (0x03 << 5)293#define SLG51000_GPIO6_INVERT_SHIFT 4294#define SLG51000_GPIO6_INVERT_MASK (0x01 << 4)295#define SLG51000_GPIO6_T_DEB_SHIFT 1296#define SLG51000_GPIO6_T_DEB_MASK (0x03 << 1)297#define SLG51000_GPIO6_LEVEL_SHIFT 0298#define SLG51000_GPIO6_LEVEL_MASK (0x01 << 0)299 300/* SLG51000_IO_GPIO_STATUS = 0x1506 */301#define SLG51000_GPIO6_STATUS_SHIFT 5302#define SLG51000_GPIO6_STATUS_MASK (0x01 << 5)303#define SLG51000_GPIO5_STATUS_SHIFT 4304#define SLG51000_GPIO5_STATUS_MASK (0x01 << 4)305#define SLG51000_GPIO4_STATUS_SHIFT 3306#define SLG51000_GPIO4_STATUS_MASK (0x01 << 3)307#define SLG51000_GPIO3_STATUS_SHIFT 2308#define SLG51000_GPIO3_STATUS_MASK (0x01 << 2)309#define SLG51000_GPIO2_STATUS_SHIFT 1310#define SLG51000_GPIO2_STATUS_MASK (0x01 << 1)311#define SLG51000_GPIO1_STATUS_SHIFT 0312#define SLG51000_GPIO1_STATUS_MASK (0x01 << 0)313 314/* SLG51000_LUTARRAY_LUT_VAL_0 ~ SLG51000_LUTARRAY_LUT_VAL_11315 * 0x1600, 0x1601, 0x1602, 0x1603, 0x1604, 0x1605,316 * 0x1606, 0x1607, 0x1608, 0x1609, 0x160a, 0x160b317 */318#define SLG51000_LUT_VAL_SHIFT 0319#define SLG51000_LUT_VAL_MASK (0xff << 0)320 321/* SLG51000_MUXARRAY_INPUT_SEL_0 ~ SLG51000_MUXARRAY_INPUT_SEL_63322 * 0x1700, 0x1701, 0x1702, 0x1703, 0x1704, 0x1705,323 * 0x1706, 0x1707, 0x1708, 0x1709, 0x170a, 0x170b,324 * 0x170c, 0x170d, 0x170e, 0x170f, 0x1710, 0x1711,325 * 0x1712, 0x1713, 0x1714, 0x1715, 0x1716, 0x1717,326 * 0x1718, 0x1719, 0x171a, 0x171b, 0x171c, 0x171d,327 * 0x171e, 0x171f, 0x1720, 0x1721, 0x1722, 0x1723,328 * 0x1724, 0x1725, 0x1726, 0x1727, 0x1728, 0x1729,329 * 0x173a, 0x173b, 0x173c, 0x173d, 0x173e, 0x173f,330 */331#define SLG51000_INPUT_SEL_SHIFT 0332#define SLG51000_INPUT_SEL_MASK (0x3f << 0)333 334/* SLG51000_PWRSEQ_RESOURCE_EN_0 ~ SLG51000_PWRSEQ_RESOURCE_EN_5335 * 0x1900, 0x1901, 0x1902, 0x1903, 0x1904, 0x1905336 */337#define SLG51000_RESOURCE_EN_DOWN0_SHIFT 4338#define SLG51000_RESOURCE_EN_DOWN0_MASK (0x07 << 4)339#define SLG51000_RESOURCE_EN_UP0_SHIFT 0340#define SLG51000_RESOURCE_EN_UP0_MASK (0x07 << 0)341 342/* SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5343 * 0x1906, 0x1908, 0x190a, 0x190c, 0x190e, 0x1910344 */345#define SLG51000_SLOT_TIME_MIN_UP_SHIFT 0346#define SLG51000_SLOT_TIME_MIN_UP_MASK (0xff << 0)347 348/* SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5349 * 0x1907, 0x1909, 0x190b, 0x190d, 0x190f, 0x1911350 */351#define SLG51000_SLOT_TIME_MIN_DOWN_SHIFT 0352#define SLG51000_SLOT_TIME_MIN_DOWN_MASK (0xff << 0)353 354/* SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A ~ SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C355 * 0x1912, 0x1913, 0x1914356 */357#define SLG51000_SLOT_TIME_MAX_DOWN1_SHIFT 6358#define SLG51000_SLOT_TIME_MAX_DOWN1_MASK (0x03 << 6)359#define SLG51000_SLOT_TIME_MAX_UP1_SHIFT 4360#define SLG51000_SLOT_TIME_MAX_UP1_MASK (0x03 << 4)361#define SLG51000_SLOT_TIME_MAX_DOWN0_SHIFT 2362#define SLG51000_SLOT_TIME_MAX_DOWN0_MASK (0x03 << 2)363#define SLG51000_SLOT_TIME_MAX_UP0_SHIFT 0364#define SLG51000_SLOT_TIME_MAX_UP0_MASK (0x03 << 0)365 366/* SLG51000_PWRSEQ_INPUT_SENSE_CONF_A = 0x1915 */367#define SLG51000_TRIG_UP_SENSE_SHIFT 6368#define SLG51000_TRIG_UP_SENSE_MASK (0x01 << 6)369#define SLG51000_UP_EN_SENSE5_SHIFT 5370#define SLG51000_UP_EN_SENSE5_MASK (0x01 << 5)371#define SLG51000_UP_EN_SENSE4_SHIFT 4372#define SLG51000_UP_EN_SENSE4_MASK (0x01 << 4)373#define SLG51000_UP_EN_SENSE3_SHIFT 3374#define SLG51000_UP_EN_SENSE3_MASK (0x01 << 3)375#define SLG51000_UP_EN_SENSE2_SHIFT 2376#define SLG51000_UP_EN_SENSE2_MASK (0x01 << 2)377#define SLG51000_UP_EN_SENSE1_SHIFT 1378#define SLG51000_UP_EN_SENSE1_MASK (0x01 << 1)379#define SLG51000_UP_EN_SENSE0_SHIFT 0380#define SLG51000_UP_EN_SENSE0_MASK (0x01 << 0)381 382/* SLG51000_PWRSEQ_INPUT_SENSE_CONF_B = 0x1916 */383#define SLG51000_CRASH_DETECT_SENSE_SHIFT 7384#define SLG51000_CRASH_DETECT_SENSE_MASK (0x01 << 7)385#define SLG51000_TRIG_DOWN_SENSE_SHIFT 6386#define SLG51000_TRIG_DOWN_SENSE_MASK (0x01 << 6)387#define SLG51000_DOWN_EN_SENSE5_SHIFT 5388#define SLG51000_DOWN_EN_SENSE5_MASK (0x01 << 5)389#define SLG51000_DOWN_EN_SENSE4_SHIFT 4390#define SLG51000_DOWN_EN_SENSE4_MASK (0x01 << 4)391#define SLG51000_DOWN_EN_SENSE3_SHIFT 3392#define SLG51000_DOWN_EN_SENSE3_MASK (0x01 << 3)393#define SLG51000_DOWN_EN_SENSE2_SHIFT 2394#define SLG51000_DOWN_EN_SENSE2_MASK (0x01 << 2)395#define SLG51000_DOWN_EN_SENSE1_SHIFT 1396#define SLG51000_DOWN_EN_SENSE1_MASK (0x01 << 1)397#define SLG51000_DOWN_EN_SENSE0_SHIFT 0398#define SLG51000_DOWN_EN_SENSE0_MASK (0x01 << 0)399 400/* SLG51000_LDO1_VSEL ~ SLG51000_LDO7_VSEL =401 * 0x2000, 0x2200, 0x2300, 0x2500, 0x2700, 0x2900, 0x3100402 */403#define SLG51000_VSEL_SHIFT 0404#define SLG51000_VSEL_MASK (0xff << 0)405 406/* SLG51000_LDO1_MINV ~ SLG51000_LDO7_MINV =407 * 0x2060, 0x2260, 0x2360, 0x2560, 0x2760, 0x2960, 0x3160408 */409#define SLG51000_MINV_SHIFT 0410#define SLG51000_MINV_MASK (0xff << 0)411 412/* SLG51000_LDO1_MAXV ~ SLG51000_LDO7_MAXV =413 * 0x2061, 0x2261, 0x2361, 0x2561, 0x2761, 0x2961, 0x3161414 */415#define SLG51000_MAXV_SHIFT 0416#define SLG51000_MAXV_MASK (0xff << 0)417 418/* SLG51000_LDO1_MISC1 = 0x2064, SLG51000_LDO2_MISC1 = 0x2264 */419#define SLG51000_SEL_VRANGE_SHIFT 0420#define SLG51000_SEL_VRANGE_MASK (0x01 << 0)421 422/* SLG51000_LDO1_VSEL_ACTUAL ~ SLG51000_LDO7_VSEL_ACTUAL =423 * 0x2065, 0x2265, 0x2366, 0x2566, 0x2767, 0x2967, 0x3166424 */425#define SLG51000_VSEL_ACTUAL_SHIFT 0426#define SLG51000_VSEL_ACTUAL_MASK (0xff << 0)427 428/* SLG51000_LDO1_EVENT ~ SLG51000_LDO7_EVENT =429 * 0x20c0, 0x22c0, 0x23c0, 0x25c0, 0x27c0, 0x29c0, 0x31c0430 */431#define SLG51000_EVT_ILIM_FLAG_SHIFT 0432#define SLG51000_EVT_ILIM_FLAG_MASK (0x01 << 0)433#define SLG51000_EVT_VOUT_OK_FLAG_SHIFT 1434#define SLG51000_EVT_VOUT_OK_FLAG_MASK (0x01 << 1)435 436/* SLG51000_LDO1_STATUS ~ SLG51000_LDO7_STATUS =437 * 0x20c1, 0x22c1, 0x23c1, 0x25c1, 0x27c1, 0x29c1, 0x31c1438 */439#define SLG51000_STA_ILIM_FLAG_SHIFT 0440#define SLG51000_STA_ILIM_FLAG_MASK (0x01 << 0)441#define SLG51000_STA_VOUT_OK_FLAG_SHIFT 1442#define SLG51000_STA_VOUT_OK_FLAG_MASK (0x01 << 1)443 444/* SLG51000_LDO1_IRQ_MASK ~ SLG51000_LDO7_IRQ_MASK =445 * 0x20c2, 0x22c2, 0x23c2, 0x25c2, 0x27c2, 0x29c2, 0x31c2446 */447#define SLG51000_IRQ_ILIM_FLAG_SHIFT 0448#define SLG51000_IRQ_ILIM_FLAG_MASK (0x01 << 0)449 450/* SLG51000_LDO3_CONF1 ~ SLG51000_LDO7_CONF1 =451 * 0x2364, 0x2564, 0x2765, 0x2965, 0x3164452 */453#define SLG51000_SEL_START_ILIM_SHIFT 0454#define SLG51000_SEL_START_ILIM_MASK (0x7f << 0)455 456/* SLG51000_LDO3_CONF2 ~ SLG51000_LDO7_CONF2 =457 * 0x2365, 0x2565, 0x2766, 0x2966, 0x3165458 */459#define SLG51000_SEL_FUNC_ILIM_SHIFT 0460#define SLG51000_SEL_FUNC_ILIM_MASK (0x7f << 0)461 462/* SLG51000_LDO5_TRIM2 = 0x2763, SLG51000_LDO6_TRIM2 = 0x2963 */463#define SLG51000_SEL_BYP_SLEW_RATE_SHIFT 2464#define SLG51000_SEL_BYP_SLEW_RATE_MASK (0x03 << 2)465#define SLG51000_SEL_BYP_VGATE_SHIFT 1466#define SLG51000_SEL_BYP_VGATE_MASK (0x01 << 1)467#define SLG51000_SEL_BYP_MODE_SHIFT 0468#define SLG51000_SEL_BYP_MODE_MASK (0x01 << 0)469 470/* SLG51000_OTP_EVENT = 0x782b */471#define SLG51000_EVT_CRC_SHIFT 0472#define SLG51000_EVT_CRC_MASK (0x01 << 0)473 474/* SLG51000_OTP_IRQ_MASK = 0x782d */475#define SLG51000_IRQ_CRC_SHIFT 0476#define SLG51000_IRQ_CRC_MASK (0x01 << 0)477 478/* SLG51000_OTP_LOCK_OTP_PROG = 0x78fe */479#define SLG51000_LOCK_OTP_PROG_SHIFT 0480#define SLG51000_LOCK_OTP_PROG_MASK (0x01 << 0)481 482/* SLG51000_OTP_LOCK_CTRL = 0x78ff */483#define SLG51000_LOCK_DFT_SHIFT 1484#define SLG51000_LOCK_DFT_MASK (0x01 << 1)485#define SLG51000_LOCK_RWT_SHIFT 0486#define SLG51000_LOCK_RWT_MASK (0x01 << 0)487 488/* SLG51000_LOCK_GLOBAL_LOCK_CTRL1 = 0x8000 */489#define SLG51000_LDO7_LOCK_SHIFT 7490#define SLG51000_LDO7_LOCK_MASK (0x01 << 7)491#define SLG51000_LDO6_LOCK_SHIFT 6492#define SLG51000_LDO6_LOCK_MASK (0x01 << 6)493#define SLG51000_LDO5_LOCK_SHIFT 5494#define SLG51000_LDO5_LOCK_MASK (0x01 << 5)495#define SLG51000_LDO4_LOCK_SHIFT 4496#define SLG51000_LDO4_LOCK_MASK (0x01 << 4)497#define SLG51000_LDO3_LOCK_SHIFT 3498#define SLG51000_LDO3_LOCK_MASK (0x01 << 3)499#define SLG51000_LDO2_LOCK_SHIFT 2500#define SLG51000_LDO2_LOCK_MASK (0x01 << 2)501#define SLG51000_LDO1_LOCK_SHIFT 1502#define SLG51000_LDO1_LOCK_MASK (0x01 << 1)503 504#endif /* __SLG51000_REGISTERS_H__ */505 506