178 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2019 MediaTek Inc.4 */5 6#ifndef __RPROC_MTK_COMMON_H7#define __RPROC_MTK_COMMON_H8 9#include <linux/interrupt.h>10#include <linux/kernel.h>11#include <linux/platform_device.h>12#include <linux/remoteproc.h>13#include <linux/remoteproc/mtk_scp.h>14 15#define MT8183_SW_RSTN 0x016#define MT8183_SW_RSTN_BIT BIT(0)17#define MT8183_SCP_TO_HOST 0x1C18#define MT8183_SCP_IPC_INT_BIT BIT(0)19#define MT8183_SCP_WDT_INT_BIT BIT(8)20#define MT8183_HOST_TO_SCP 0x2821#define MT8183_HOST_IPC_INT_BIT BIT(0)22#define MT8183_WDT_CFG 0x8423#define MT8183_SCP_CLK_SW_SEL 0x400024#define MT8183_SCP_CLK_DIV_SEL 0x402425#define MT8183_SCP_SRAM_PDN 0x402C26#define MT8183_SCP_L1_SRAM_PD 0x408027#define MT8183_SCP_TCM_TAIL_SRAM_PD 0x409428 29#define MT8183_SCP_CACHE_SEL(x) (0x14000 + (x) * 0x3000)30#define MT8183_SCP_CACHE_CON MT8183_SCP_CACHE_SEL(0)31#define MT8183_SCP_DCACHE_CON MT8183_SCP_CACHE_SEL(1)32#define MT8183_SCP_CACHESIZE_8KB BIT(8)33#define MT8183_SCP_CACHE_CON_WAYEN BIT(10)34 35#define MT8186_SCP_L1_SRAM_PD_P1 0x40B036#define MT8186_SCP_L1_SRAM_PD_p2 0x40B437 38#define MT8192_L2TCM_SRAM_PD_0 0x10C039#define MT8192_L2TCM_SRAM_PD_1 0x10C440#define MT8192_L2TCM_SRAM_PD_2 0x10C841#define MT8192_L1TCM_SRAM_PDN 0x102C42#define MT8192_CPU0_SRAM_PD 0x108043 44#define MT8192_SCP2APMCU_IPC_SET 0x408045#define MT8192_SCP2APMCU_IPC_CLR 0x408446#define MT8192_SCP_IPC_INT_BIT BIT(0)47#define MT8192_SCP2SPM_IPC_CLR 0x409448#define MT8192_GIPC_IN_SET 0x409849#define MT8192_HOST_IPC_INT_BIT BIT(0)50#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4)51 52#define MT8192_CORE0_SW_RSTN_CLR 0x1000053#define MT8192_CORE0_SW_RSTN_SET 0x1000454#define MT8192_CORE0_MEM_ATT_PREDEF 0x1000855#define MT8192_CORE0_WDT_IRQ 0x1003056#define MT8192_CORE0_WDT_CFG 0x1003457 58#define MT8195_SYS_STATUS 0x400459#define MT8195_CORE0_WDT BIT(16)60#define MT8195_CORE1_WDT BIT(17)61 62#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)63 64#define MT8195_CPU1_SRAM_PD 0x108465#define MT8195_SSHUB2APMCU_IPC_SET 0x408866#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C67#define MT8195_CORE1_SW_RSTN_CLR 0x2000068#define MT8195_CORE1_SW_RSTN_SET 0x2000469#define MT8195_CORE1_MEM_ATT_PREDEF 0x2000870#define MT8195_CORE1_WDT_IRQ 0x2003071#define MT8195_CORE1_WDT_CFG 0x2003472 73#define MT8195_SEC_CTRL 0x8500074#define MT8195_CORE_OFFSET_ENABLE_D BIT(13)75#define MT8195_CORE_OFFSET_ENABLE_I BIT(12)76#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b077#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b478#define MT8195_L2TCM_OFFSET 0x850d079 80#define SCP_FW_VER_LEN 3281 82struct scp_run {83 u32 signaled;84 s8 fw_ver[SCP_FW_VER_LEN];85 u32 dec_capability;86 u32 enc_capability;87 wait_queue_head_t wq;88};89 90struct scp_ipi_desc {91 /* For protecting handler. */92 struct mutex lock;93 scp_ipi_handler_t handler;94 void *priv;95};96 97struct mtk_scp;98 99struct mtk_scp_sizes_data {100 size_t max_dram_size;101 size_t ipi_share_buffer_size;102};103 104struct mtk_scp_of_data {105 int (*scp_clk_get)(struct mtk_scp *scp);106 int (*scp_before_load)(struct mtk_scp *scp);107 void (*scp_irq_handler)(struct mtk_scp *scp);108 void (*scp_reset_assert)(struct mtk_scp *scp);109 void (*scp_reset_deassert)(struct mtk_scp *scp);110 void (*scp_stop)(struct mtk_scp *scp);111 void *(*scp_da_to_va)(struct mtk_scp *scp, u64 da, size_t len);112 113 u32 host_to_scp_reg;114 u32 host_to_scp_int_bit;115 116 size_t ipi_buf_offset;117 const struct mtk_scp_sizes_data *scp_sizes;118};119 120struct mtk_scp_of_cluster {121 void __iomem *reg_base;122 void __iomem *l1tcm_base;123 size_t l1tcm_size;124 phys_addr_t l1tcm_phys;125 struct list_head mtk_scp_list;126 /* Prevent concurrent operations of this structure and L2TCM power control. */127 struct mutex cluster_lock;128 u32 l2tcm_refcnt;129};130 131struct mtk_scp {132 struct device *dev;133 struct rproc *rproc;134 struct clk *clk;135 void __iomem *sram_base;136 size_t sram_size;137 phys_addr_t sram_phys;138 139 const struct mtk_scp_of_data *data;140 141 struct mtk_share_obj __iomem *recv_buf;142 struct mtk_share_obj __iomem *send_buf;143 struct scp_run run;144 /* To prevent multiple ipi_send run concurrently. */145 struct mutex send_lock;146 struct scp_ipi_desc ipi_desc[SCP_IPI_MAX];147 bool ipi_id_ack[SCP_IPI_MAX];148 wait_queue_head_t ack_wq;149 u8 *share_buf;150 151 void *cpu_addr;152 dma_addr_t dma_addr;153 154 struct rproc_subdev *rpmsg_subdev;155 156 struct list_head elem;157 struct mtk_scp_of_cluster *cluster;158};159 160/**161 * struct mtk_share_obj - SRAM buffer shared with AP and SCP162 *163 * @id: IPI id164 * @len: share buffer length165 * @share_buf: share buffer data166 */167struct mtk_share_obj {168 u32 id;169 u32 len;170 u8 *share_buf;171};172 173void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len);174void scp_ipi_lock(struct mtk_scp *scp, u32 id);175void scp_ipi_unlock(struct mtk_scp *scp, u32 id);176 177#endif178