853 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * Qualcomm Technology Inc. ADSP Peripheral Image Loader for SDM845.4 * Copyright (c) 2018, The Linux Foundation. All rights reserved.5 */6 7#include <linux/clk.h>8#include <linux/delay.h>9#include <linux/firmware.h>10#include <linux/interrupt.h>11#include <linux/io.h>12#include <linux/iommu.h>13#include <linux/iopoll.h>14#include <linux/kernel.h>15#include <linux/mfd/syscon.h>16#include <linux/module.h>17#include <linux/of.h>18#include <linux/of_reserved_mem.h>19#include <linux/platform_device.h>20#include <linux/pm_domain.h>21#include <linux/pm_runtime.h>22#include <linux/regmap.h>23#include <linux/remoteproc.h>24#include <linux/reset.h>25#include <linux/soc/qcom/mdt_loader.h>26#include <linux/soc/qcom/smem.h>27#include <linux/soc/qcom/smem_state.h>28 29#include "qcom_common.h"30#include "qcom_pil_info.h"31#include "qcom_q6v5.h"32#include "remoteproc_internal.h"33 34/* time out value */35#define ACK_TIMEOUT 100036#define ACK_TIMEOUT_US 100000037#define BOOT_FSM_TIMEOUT 1000038/* mask values */39#define EVB_MASK GENMASK(27, 4)40/*QDSP6SS register offsets*/41#define RST_EVB_REG 0x1042#define CORE_START_REG 0x40043#define BOOT_CMD_REG 0x40444#define BOOT_STATUS_REG 0x40845#define RET_CFG_REG 0x1C46/*TCSR register offsets*/47#define LPASS_MASTER_IDLE_REG 0x848#define LPASS_HALTACK_REG 0x449#define LPASS_PWR_ON_REG 0x1050#define LPASS_HALTREQ_REG 0x051 52#define SID_MASK_DEFAULT 0xF53 54#define QDSP6SS_XO_CBCR 0x3855#define QDSP6SS_CORE_CBCR 0x2056#define QDSP6SS_SLEEP_CBCR 0x3c57 58#define LPASS_BOOT_CORE_START BIT(0)59#define LPASS_BOOT_CMD_START BIT(0)60#define LPASS_EFUSE_Q6SS_EVB_SEL 0x061 62struct adsp_pil_data {63 int crash_reason_smem;64 const char *firmware_name;65 66 const char *ssr_name;67 const char *sysmon_name;68 int ssctl_id;69 bool is_wpss;70 bool has_iommu;71 bool auto_boot;72 73 const char **clk_ids;74 int num_clks;75 const char **pd_names;76 unsigned int num_pds;77 const char *load_state;78};79 80struct qcom_adsp {81 struct device *dev;82 struct rproc *rproc;83 84 struct qcom_q6v5 q6v5;85 86 struct clk *xo;87 88 int num_clks;89 struct clk_bulk_data *clks;90 91 void __iomem *qdsp6ss_base;92 void __iomem *lpass_efuse;93 94 struct reset_control *pdc_sync_reset;95 struct reset_control *restart;96 97 struct regmap *halt_map;98 unsigned int halt_lpass;99 100 int crash_reason_smem;101 const char *info_name;102 103 struct completion start_done;104 struct completion stop_done;105 106 phys_addr_t mem_phys;107 phys_addr_t mem_reloc;108 void *mem_region;109 size_t mem_size;110 bool has_iommu;111 112 struct dev_pm_domain_list *pd_list;113 114 struct qcom_rproc_glink glink_subdev;115 struct qcom_rproc_pdm pdm_subdev;116 struct qcom_rproc_ssr ssr_subdev;117 struct qcom_sysmon *sysmon;118 119 int (*shutdown)(struct qcom_adsp *adsp);120};121 122static int qcom_rproc_pds_attach(struct qcom_adsp *adsp, const char **pd_names,123 unsigned int num_pds)124{125 struct device *dev = adsp->dev;126 struct dev_pm_domain_attach_data pd_data = {127 .pd_names = pd_names,128 .num_pd_names = num_pds,129 };130 int ret;131 132 /* Handle single power domain */133 if (dev->pm_domain)134 goto out;135 136 if (!pd_names)137 return 0;138 139 ret = dev_pm_domain_attach_list(dev, &pd_data, &adsp->pd_list);140 if (ret < 0)141 return ret;142 143out:144 pm_runtime_enable(dev);145 return 0;146}147 148static void qcom_rproc_pds_detach(struct qcom_adsp *adsp)149{150 struct device *dev = adsp->dev;151 struct dev_pm_domain_list *pds = adsp->pd_list;152 153 dev_pm_domain_detach_list(pds);154 155 if (dev->pm_domain || pds)156 pm_runtime_disable(adsp->dev);157}158 159static int qcom_rproc_pds_enable(struct qcom_adsp *adsp)160{161 struct device *dev = adsp->dev;162 struct dev_pm_domain_list *pds = adsp->pd_list;163 int ret, i = 0;164 165 if (!dev->pm_domain && !pds)166 return 0;167 168 if (dev->pm_domain)169 dev_pm_genpd_set_performance_state(dev, INT_MAX);170 171 while (pds && i < pds->num_pds) {172 dev_pm_genpd_set_performance_state(pds->pd_devs[i], INT_MAX);173 i++;174 }175 176 ret = pm_runtime_resume_and_get(dev);177 if (ret < 0) {178 while (pds && i > 0) {179 i--;180 dev_pm_genpd_set_performance_state(pds->pd_devs[i], 0);181 }182 183 if (dev->pm_domain)184 dev_pm_genpd_set_performance_state(dev, 0);185 }186 187 return ret;188}189 190static void qcom_rproc_pds_disable(struct qcom_adsp *adsp)191{192 struct device *dev = adsp->dev;193 struct dev_pm_domain_list *pds = adsp->pd_list;194 int i = 0;195 196 if (!dev->pm_domain && !pds)197 return;198 199 if (dev->pm_domain)200 dev_pm_genpd_set_performance_state(dev, 0);201 202 while (pds && i < pds->num_pds) {203 dev_pm_genpd_set_performance_state(pds->pd_devs[i], 0);204 i++;205 }206 207 pm_runtime_put(dev);208}209 210static int qcom_wpss_shutdown(struct qcom_adsp *adsp)211{212 unsigned int val;213 214 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 1);215 216 /* Wait for halt ACK from QDSP6 */217 regmap_read_poll_timeout(adsp->halt_map,218 adsp->halt_lpass + LPASS_HALTACK_REG, val,219 val, 1000, ACK_TIMEOUT_US);220 221 /* Assert the WPSS PDC Reset */222 reset_control_assert(adsp->pdc_sync_reset);223 224 /* Place the WPSS processor into reset */225 reset_control_assert(adsp->restart);226 227 /* wait after asserting subsystem restart from AOSS */228 usleep_range(200, 205);229 230 /* Remove the WPSS reset */231 reset_control_deassert(adsp->restart);232 233 /* De-assert the WPSS PDC Reset */234 reset_control_deassert(adsp->pdc_sync_reset);235 236 usleep_range(100, 105);237 238 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);239 240 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);241 242 /* Wait for halt ACK from QDSP6 */243 regmap_read_poll_timeout(adsp->halt_map,244 adsp->halt_lpass + LPASS_HALTACK_REG, val,245 !val, 1000, ACK_TIMEOUT_US);246 247 return 0;248}249 250static int qcom_adsp_shutdown(struct qcom_adsp *adsp)251{252 unsigned long timeout;253 unsigned int val;254 int ret;255 256 /* Reset the retention logic */257 val = readl(adsp->qdsp6ss_base + RET_CFG_REG);258 val |= 0x1;259 writel(val, adsp->qdsp6ss_base + RET_CFG_REG);260 261 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);262 263 /* QDSP6 master port needs to be explicitly halted */264 ret = regmap_read(adsp->halt_map,265 adsp->halt_lpass + LPASS_PWR_ON_REG, &val);266 if (ret || !val)267 goto reset;268 269 ret = regmap_read(adsp->halt_map,270 adsp->halt_lpass + LPASS_MASTER_IDLE_REG,271 &val);272 if (ret || val)273 goto reset;274 275 regmap_write(adsp->halt_map,276 adsp->halt_lpass + LPASS_HALTREQ_REG, 1);277 278 /* Wait for halt ACK from QDSP6 */279 timeout = jiffies + msecs_to_jiffies(ACK_TIMEOUT);280 for (;;) {281 ret = regmap_read(adsp->halt_map,282 adsp->halt_lpass + LPASS_HALTACK_REG, &val);283 if (ret || val || time_after(jiffies, timeout))284 break;285 286 usleep_range(1000, 1100);287 }288 289 ret = regmap_read(adsp->halt_map,290 adsp->halt_lpass + LPASS_MASTER_IDLE_REG, &val);291 if (ret || !val)292 dev_err(adsp->dev, "port failed halt\n");293 294reset:295 /* Assert the LPASS PDC Reset */296 reset_control_assert(adsp->pdc_sync_reset);297 /* Place the LPASS processor into reset */298 reset_control_assert(adsp->restart);299 /* wait after asserting subsystem restart from AOSS */300 usleep_range(200, 300);301 302 /* Clear the halt request for the AXIM and AHBM for Q6 */303 regmap_write(adsp->halt_map, adsp->halt_lpass + LPASS_HALTREQ_REG, 0);304 305 /* De-assert the LPASS PDC Reset */306 reset_control_deassert(adsp->pdc_sync_reset);307 /* Remove the LPASS reset */308 reset_control_deassert(adsp->restart);309 /* wait after de-asserting subsystem restart from AOSS */310 usleep_range(200, 300);311 312 return 0;313}314 315static int adsp_load(struct rproc *rproc, const struct firmware *fw)316{317 struct qcom_adsp *adsp = rproc->priv;318 int ret;319 320 ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,321 adsp->mem_region, adsp->mem_phys,322 adsp->mem_size, &adsp->mem_reloc);323 if (ret)324 return ret;325 326 qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);327 328 return 0;329}330 331static void adsp_unmap_carveout(struct rproc *rproc)332{333 struct qcom_adsp *adsp = rproc->priv;334 335 if (adsp->has_iommu)336 iommu_unmap(rproc->domain, adsp->mem_phys, adsp->mem_size);337}338 339static int adsp_map_carveout(struct rproc *rproc)340{341 struct qcom_adsp *adsp = rproc->priv;342 struct of_phandle_args args;343 long long sid;344 unsigned long iova;345 int ret;346 347 if (!adsp->has_iommu)348 return 0;349 350 if (!rproc->domain)351 return -EINVAL;352 353 ret = of_parse_phandle_with_args(adsp->dev->of_node, "iommus", "#iommu-cells", 0, &args);354 if (ret < 0)355 return ret;356 357 sid = args.args[0] & SID_MASK_DEFAULT;358 359 /* Add SID configuration for ADSP Firmware to SMMU */360 iova = adsp->mem_phys | (sid << 32);361 362 ret = iommu_map(rproc->domain, iova, adsp->mem_phys,363 adsp->mem_size, IOMMU_READ | IOMMU_WRITE,364 GFP_KERNEL);365 if (ret) {366 dev_err(adsp->dev, "Unable to map ADSP Physical Memory\n");367 return ret;368 }369 370 return 0;371}372 373static int adsp_start(struct rproc *rproc)374{375 struct qcom_adsp *adsp = rproc->priv;376 int ret;377 unsigned int val;378 379 ret = qcom_q6v5_prepare(&adsp->q6v5);380 if (ret)381 return ret;382 383 ret = adsp_map_carveout(rproc);384 if (ret) {385 dev_err(adsp->dev, "ADSP smmu mapping failed\n");386 goto disable_irqs;387 }388 389 ret = clk_prepare_enable(adsp->xo);390 if (ret)391 goto adsp_smmu_unmap;392 393 ret = qcom_rproc_pds_enable(adsp);394 if (ret < 0)395 goto disable_xo_clk;396 397 ret = clk_bulk_prepare_enable(adsp->num_clks, adsp->clks);398 if (ret) {399 dev_err(adsp->dev, "adsp clk_enable failed\n");400 goto disable_power_domain;401 }402 403 /* Enable the XO clock */404 writel(1, adsp->qdsp6ss_base + QDSP6SS_XO_CBCR);405 406 /* Enable the QDSP6SS sleep clock */407 writel(1, adsp->qdsp6ss_base + QDSP6SS_SLEEP_CBCR);408 409 /* Enable the QDSP6 core clock */410 writel(1, adsp->qdsp6ss_base + QDSP6SS_CORE_CBCR);411 412 /* Program boot address */413 writel(adsp->mem_phys >> 4, adsp->qdsp6ss_base + RST_EVB_REG);414 415 if (adsp->lpass_efuse)416 writel(LPASS_EFUSE_Q6SS_EVB_SEL, adsp->lpass_efuse);417 418 /* De-assert QDSP6 stop core. QDSP6 will execute after out of reset */419 writel(LPASS_BOOT_CORE_START, adsp->qdsp6ss_base + CORE_START_REG);420 421 /* Trigger boot FSM to start QDSP6 */422 writel(LPASS_BOOT_CMD_START, adsp->qdsp6ss_base + BOOT_CMD_REG);423 424 /* Wait for core to come out of reset */425 ret = readl_poll_timeout(adsp->qdsp6ss_base + BOOT_STATUS_REG,426 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);427 if (ret) {428 dev_err(adsp->dev, "failed to bootup adsp\n");429 goto disable_adsp_clks;430 }431 432 ret = qcom_q6v5_wait_for_start(&adsp->q6v5, msecs_to_jiffies(5 * HZ));433 if (ret == -ETIMEDOUT) {434 dev_err(adsp->dev, "start timed out\n");435 goto disable_adsp_clks;436 }437 438 return 0;439 440disable_adsp_clks:441 clk_bulk_disable_unprepare(adsp->num_clks, adsp->clks);442disable_power_domain:443 qcom_rproc_pds_disable(adsp);444disable_xo_clk:445 clk_disable_unprepare(adsp->xo);446adsp_smmu_unmap:447 adsp_unmap_carveout(rproc);448disable_irqs:449 qcom_q6v5_unprepare(&adsp->q6v5);450 451 return ret;452}453 454static void qcom_adsp_pil_handover(struct qcom_q6v5 *q6v5)455{456 struct qcom_adsp *adsp = container_of(q6v5, struct qcom_adsp, q6v5);457 458 clk_disable_unprepare(adsp->xo);459 qcom_rproc_pds_disable(adsp);460}461 462static int adsp_stop(struct rproc *rproc)463{464 struct qcom_adsp *adsp = rproc->priv;465 int handover;466 int ret;467 468 ret = qcom_q6v5_request_stop(&adsp->q6v5, adsp->sysmon);469 if (ret == -ETIMEDOUT)470 dev_err(adsp->dev, "timed out on wait\n");471 472 ret = adsp->shutdown(adsp);473 if (ret)474 dev_err(adsp->dev, "failed to shutdown: %d\n", ret);475 476 adsp_unmap_carveout(rproc);477 478 handover = qcom_q6v5_unprepare(&adsp->q6v5);479 if (handover)480 qcom_adsp_pil_handover(&adsp->q6v5);481 482 return ret;483}484 485static void *adsp_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)486{487 struct qcom_adsp *adsp = rproc->priv;488 int offset;489 490 offset = da - adsp->mem_reloc;491 if (offset < 0 || offset + len > adsp->mem_size)492 return NULL;493 494 return adsp->mem_region + offset;495}496 497static int adsp_parse_firmware(struct rproc *rproc, const struct firmware *fw)498{499 struct qcom_adsp *adsp = rproc->priv;500 int ret;501 502 ret = qcom_register_dump_segments(rproc, fw);503 if (ret) {504 dev_err(&rproc->dev, "Error in registering dump segments\n");505 return ret;506 }507 508 if (adsp->has_iommu) {509 ret = rproc_elf_load_rsc_table(rproc, fw);510 if (ret) {511 dev_err(&rproc->dev, "Error in loading resource table\n");512 return ret;513 }514 }515 return 0;516}517 518static unsigned long adsp_panic(struct rproc *rproc)519{520 struct qcom_adsp *adsp = rproc->priv;521 522 return qcom_q6v5_panic(&adsp->q6v5);523}524 525static const struct rproc_ops adsp_ops = {526 .start = adsp_start,527 .stop = adsp_stop,528 .da_to_va = adsp_da_to_va,529 .parse_fw = adsp_parse_firmware,530 .load = adsp_load,531 .panic = adsp_panic,532};533 534static int adsp_init_clock(struct qcom_adsp *adsp, const char **clk_ids)535{536 int num_clks = 0;537 int i, ret;538 539 adsp->xo = devm_clk_get(adsp->dev, "xo");540 if (IS_ERR(adsp->xo)) {541 ret = PTR_ERR(adsp->xo);542 if (ret != -EPROBE_DEFER)543 dev_err(adsp->dev, "failed to get xo clock");544 return ret;545 }546 547 for (i = 0; clk_ids[i]; i++)548 num_clks++;549 550 adsp->num_clks = num_clks;551 adsp->clks = devm_kcalloc(adsp->dev, adsp->num_clks,552 sizeof(*adsp->clks), GFP_KERNEL);553 if (!adsp->clks)554 return -ENOMEM;555 556 for (i = 0; i < adsp->num_clks; i++)557 adsp->clks[i].id = clk_ids[i];558 559 return devm_clk_bulk_get(adsp->dev, adsp->num_clks, adsp->clks);560}561 562static int adsp_init_reset(struct qcom_adsp *adsp)563{564 adsp->pdc_sync_reset = devm_reset_control_get_optional_exclusive(adsp->dev,565 "pdc_sync");566 if (IS_ERR(adsp->pdc_sync_reset)) {567 dev_err(adsp->dev, "failed to acquire pdc_sync reset\n");568 return PTR_ERR(adsp->pdc_sync_reset);569 }570 571 adsp->restart = devm_reset_control_get_optional_exclusive(adsp->dev, "restart");572 573 /* Fall back to the old "cc_lpass" if "restart" is absent */574 if (!adsp->restart)575 adsp->restart = devm_reset_control_get_exclusive(adsp->dev, "cc_lpass");576 577 if (IS_ERR(adsp->restart)) {578 dev_err(adsp->dev, "failed to acquire restart\n");579 return PTR_ERR(adsp->restart);580 }581 582 return 0;583}584 585static int adsp_init_mmio(struct qcom_adsp *adsp,586 struct platform_device *pdev)587{588 struct resource *efuse_region;589 struct device_node *syscon;590 int ret;591 592 adsp->qdsp6ss_base = devm_platform_ioremap_resource(pdev, 0);593 if (IS_ERR(adsp->qdsp6ss_base)) {594 dev_err(adsp->dev, "failed to map QDSP6SS registers\n");595 return PTR_ERR(adsp->qdsp6ss_base);596 }597 598 efuse_region = platform_get_resource(pdev, IORESOURCE_MEM, 1);599 if (!efuse_region) {600 adsp->lpass_efuse = NULL;601 dev_dbg(adsp->dev, "failed to get efuse memory region\n");602 } else {603 adsp->lpass_efuse = devm_ioremap_resource(&pdev->dev, efuse_region);604 if (IS_ERR(adsp->lpass_efuse)) {605 dev_err(adsp->dev, "failed to map efuse registers\n");606 return PTR_ERR(adsp->lpass_efuse);607 }608 }609 syscon = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);610 if (!syscon) {611 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");612 return -EINVAL;613 }614 615 adsp->halt_map = syscon_node_to_regmap(syscon);616 of_node_put(syscon);617 if (IS_ERR(adsp->halt_map))618 return PTR_ERR(adsp->halt_map);619 620 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",621 1, &adsp->halt_lpass);622 if (ret < 0) {623 dev_err(&pdev->dev, "no offset in syscon\n");624 return ret;625 }626 627 return 0;628}629 630static int adsp_alloc_memory_region(struct qcom_adsp *adsp)631{632 struct reserved_mem *rmem = NULL;633 struct device_node *node;634 635 node = of_parse_phandle(adsp->dev->of_node, "memory-region", 0);636 if (node)637 rmem = of_reserved_mem_lookup(node);638 of_node_put(node);639 640 if (!rmem) {641 dev_err(adsp->dev, "unable to resolve memory-region\n");642 return -EINVAL;643 }644 645 adsp->mem_phys = adsp->mem_reloc = rmem->base;646 adsp->mem_size = rmem->size;647 adsp->mem_region = devm_ioremap_wc(adsp->dev,648 adsp->mem_phys, adsp->mem_size);649 if (!adsp->mem_region) {650 dev_err(adsp->dev, "unable to map memory region: %pa+%zx\n",651 &rmem->base, adsp->mem_size);652 return -EBUSY;653 }654 655 return 0;656}657 658static int adsp_probe(struct platform_device *pdev)659{660 const struct adsp_pil_data *desc;661 const char *firmware_name;662 struct qcom_adsp *adsp;663 struct rproc *rproc;664 int ret;665 666 desc = of_device_get_match_data(&pdev->dev);667 if (!desc)668 return -EINVAL;669 670 firmware_name = desc->firmware_name;671 ret = of_property_read_string(pdev->dev.of_node, "firmware-name",672 &firmware_name);673 if (ret < 0 && ret != -EINVAL) {674 dev_err(&pdev->dev, "unable to read firmware-name\n");675 return ret;676 }677 678 rproc = devm_rproc_alloc(&pdev->dev, pdev->name, &adsp_ops,679 firmware_name, sizeof(*adsp));680 if (!rproc) {681 dev_err(&pdev->dev, "unable to allocate remoteproc\n");682 return -ENOMEM;683 }684 685 rproc->auto_boot = desc->auto_boot;686 rproc->has_iommu = desc->has_iommu;687 rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);688 689 adsp = rproc->priv;690 adsp->dev = &pdev->dev;691 adsp->rproc = rproc;692 adsp->info_name = desc->sysmon_name;693 adsp->has_iommu = desc->has_iommu;694 695 platform_set_drvdata(pdev, adsp);696 697 if (desc->is_wpss)698 adsp->shutdown = qcom_wpss_shutdown;699 else700 adsp->shutdown = qcom_adsp_shutdown;701 702 ret = adsp_alloc_memory_region(adsp);703 if (ret)704 return ret;705 706 ret = adsp_init_clock(adsp, desc->clk_ids);707 if (ret)708 return ret;709 710 ret = qcom_rproc_pds_attach(adsp, desc->pd_names, desc->num_pds);711 if (ret < 0) {712 dev_err(&pdev->dev, "Failed to attach proxy power domains\n");713 return ret;714 }715 716 ret = adsp_init_reset(adsp);717 if (ret)718 goto disable_pm;719 720 ret = adsp_init_mmio(adsp, pdev);721 if (ret)722 goto disable_pm;723 724 ret = qcom_q6v5_init(&adsp->q6v5, pdev, rproc, desc->crash_reason_smem,725 desc->load_state, qcom_adsp_pil_handover);726 if (ret)727 goto disable_pm;728 729 qcom_add_glink_subdev(rproc, &adsp->glink_subdev, desc->ssr_name);730 qcom_add_pdm_subdev(rproc, &adsp->pdm_subdev);731 qcom_add_ssr_subdev(rproc, &adsp->ssr_subdev, desc->ssr_name);732 adsp->sysmon = qcom_add_sysmon_subdev(rproc,733 desc->sysmon_name,734 desc->ssctl_id);735 if (IS_ERR(adsp->sysmon)) {736 ret = PTR_ERR(adsp->sysmon);737 goto disable_pm;738 }739 740 ret = rproc_add(rproc);741 if (ret)742 goto disable_pm;743 744 return 0;745 746disable_pm:747 qcom_rproc_pds_detach(adsp);748 749 return ret;750}751 752static void adsp_remove(struct platform_device *pdev)753{754 struct qcom_adsp *adsp = platform_get_drvdata(pdev);755 756 rproc_del(adsp->rproc);757 758 qcom_q6v5_deinit(&adsp->q6v5);759 qcom_remove_glink_subdev(adsp->rproc, &adsp->glink_subdev);760 qcom_remove_pdm_subdev(adsp->rproc, &adsp->pdm_subdev);761 qcom_remove_sysmon_subdev(adsp->sysmon);762 qcom_remove_ssr_subdev(adsp->rproc, &adsp->ssr_subdev);763 qcom_rproc_pds_detach(adsp);764}765 766static const struct adsp_pil_data adsp_resource_init = {767 .crash_reason_smem = 423,768 .firmware_name = "adsp.mdt",769 .ssr_name = "lpass",770 .sysmon_name = "adsp",771 .ssctl_id = 0x14,772 .is_wpss = false,773 .auto_boot = true,774 .clk_ids = (const char*[]) {775 "sway_cbcr", "lpass_ahbs_aon_cbcr", "lpass_ahbm_aon_cbcr",776 "qdsp6ss_xo", "qdsp6ss_sleep", "qdsp6ss_core", NULL777 },778 .num_clks = 7,779 .pd_names = (const char*[]) { "cx" },780 .num_pds = 1,781};782 783static const struct adsp_pil_data adsp_sc7280_resource_init = {784 .crash_reason_smem = 423,785 .firmware_name = "adsp.pbn",786 .load_state = "adsp",787 .ssr_name = "lpass",788 .sysmon_name = "adsp",789 .ssctl_id = 0x14,790 .has_iommu = true,791 .auto_boot = true,792 .clk_ids = (const char*[]) {793 "gcc_cfg_noc_lpass", NULL794 },795 .num_clks = 1,796};797 798static const struct adsp_pil_data cdsp_resource_init = {799 .crash_reason_smem = 601,800 .firmware_name = "cdsp.mdt",801 .ssr_name = "cdsp",802 .sysmon_name = "cdsp",803 .ssctl_id = 0x17,804 .is_wpss = false,805 .auto_boot = true,806 .clk_ids = (const char*[]) {807 "sway", "tbu", "bimc", "ahb_aon", "q6ss_slave", "q6ss_master",808 "q6_axim", NULL809 },810 .num_clks = 7,811 .pd_names = (const char*[]) { "cx" },812 .num_pds = 1,813};814 815static const struct adsp_pil_data wpss_resource_init = {816 .crash_reason_smem = 626,817 .firmware_name = "wpss.mdt",818 .ssr_name = "wpss",819 .sysmon_name = "wpss",820 .ssctl_id = 0x19,821 .is_wpss = true,822 .auto_boot = false,823 .load_state = "wpss",824 .clk_ids = (const char*[]) {825 "ahb_bdg", "ahb", "rscp", NULL826 },827 .num_clks = 3,828 .pd_names = (const char*[]) { "cx", "mx" },829 .num_pds = 2,830};831 832static const struct of_device_id adsp_of_match[] = {833 { .compatible = "qcom,qcs404-cdsp-pil", .data = &cdsp_resource_init },834 { .compatible = "qcom,sc7280-adsp-pil", .data = &adsp_sc7280_resource_init },835 { .compatible = "qcom,sc7280-wpss-pil", .data = &wpss_resource_init },836 { .compatible = "qcom,sdm845-adsp-pil", .data = &adsp_resource_init },837 { },838};839MODULE_DEVICE_TABLE(of, adsp_of_match);840 841static struct platform_driver adsp_pil_driver = {842 .probe = adsp_probe,843 .remove_new = adsp_remove,844 .driver = {845 .name = "qcom_q6v5_adsp",846 .of_match_table = adsp_of_match,847 },848};849 850module_platform_driver(adsp_pil_driver);851MODULE_DESCRIPTION("QTI SDM845 ADSP Peripheral Image Loader");852MODULE_LICENSE("GPL v2");853