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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * TI K3 R5F (MCU) Remote Processor driver4 *5 * Copyright (C) 2017-2022 Texas Instruments Incorporated - https://www.ti.com/6 * Suman Anna <s-anna@ti.com>7 */8 9#include <linux/dma-mapping.h>10#include <linux/err.h>11#include <linux/interrupt.h>12#include <linux/kernel.h>13#include <linux/mailbox_client.h>14#include <linux/module.h>15#include <linux/of.h>16#include <linux/of_address.h>17#include <linux/of_reserved_mem.h>18#include <linux/of_platform.h>19#include <linux/omap-mailbox.h>20#include <linux/platform_device.h>21#include <linux/pm_runtime.h>22#include <linux/remoteproc.h>23#include <linux/reset.h>24#include <linux/slab.h>25 26#include "omap_remoteproc.h"27#include "remoteproc_internal.h"28#include "ti_sci_proc.h"29 30/* This address can either be for ATCM or BTCM with the other at address 0x0 */31#define K3_R5_TCM_DEV_ADDR 0x4101000032 33/* R5 TI-SCI Processor Configuration Flags */34#define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x0000000135#define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x0000000236#define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x0000010037#define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x0000020038#define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x0000040039#define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x0000080040#define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x0000100041#define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x0000200042/* Available from J7200 SoCs onwards */43#define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x0000400044/* Applicable to only AM64x SoCs */45#define PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE 0x0000800046 47/* R5 TI-SCI Processor Control Flags */48#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x0000000149 50/* R5 TI-SCI Processor Status Flags */51#define PROC_BOOT_STATUS_FLAG_R5_WFE 0x0000000152#define PROC_BOOT_STATUS_FLAG_R5_WFI 0x0000000253#define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x0000000454#define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x0000010055/* Applicable to only AM64x SoCs */56#define PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY 0x0000020057 58/**59 * struct k3_r5_mem - internal memory structure60 * @cpu_addr: MPU virtual address of the memory region61 * @bus_addr: Bus address used to access the memory region62 * @dev_addr: Device address from remoteproc view63 * @size: Size of the memory region64 */65struct k3_r5_mem {66 void __iomem *cpu_addr;67 phys_addr_t bus_addr;68 u32 dev_addr;69 size_t size;70};71 72/*73 * All cluster mode values are not applicable on all SoCs. The following74 * are the modes supported on various SoCs:75 * Split mode : AM65x, J721E, J7200 and AM64x SoCs76 * LockStep mode : AM65x, J721E and J7200 SoCs77 * Single-CPU mode : AM64x SoCs only78 * Single-Core mode : AM62x, AM62A SoCs79 */80enum cluster_mode {81 CLUSTER_MODE_SPLIT = 0,82 CLUSTER_MODE_LOCKSTEP,83 CLUSTER_MODE_SINGLECPU,84 CLUSTER_MODE_SINGLECORE85};86 87/**88 * struct k3_r5_soc_data - match data to handle SoC variations89 * @tcm_is_double: flag to denote the larger unified TCMs in certain modes90 * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC91 * @single_cpu_mode: flag to denote if SoC/IP supports Single-CPU mode92 * @is_single_core: flag to denote if SoC/IP has only single core R593 */94struct k3_r5_soc_data {95 bool tcm_is_double;96 bool tcm_ecc_autoinit;97 bool single_cpu_mode;98 bool is_single_core;99};100 101/**102 * struct k3_r5_cluster - K3 R5F Cluster structure103 * @dev: cached device pointer104 * @mode: Mode to configure the Cluster - Split or LockStep105 * @cores: list of R5 cores within the cluster106 * @core_transition: wait queue to sync core state changes107 * @soc_data: SoC-specific feature data for a R5FSS108 */109struct k3_r5_cluster {110 struct device *dev;111 enum cluster_mode mode;112 struct list_head cores;113 wait_queue_head_t core_transition;114 const struct k3_r5_soc_data *soc_data;115};116 117/**118 * struct k3_r5_core - K3 R5 core structure119 * @elem: linked list item120 * @dev: cached device pointer121 * @rproc: rproc handle representing this core122 * @mem: internal memory regions data123 * @sram: on-chip SRAM memory regions data124 * @num_mems: number of internal memory regions125 * @num_sram: number of on-chip SRAM memory regions126 * @reset: reset control handle127 * @tsp: TI-SCI processor control handle128 * @ti_sci: TI-SCI handle129 * @ti_sci_id: TI-SCI device identifier130 * @atcm_enable: flag to control ATCM enablement131 * @btcm_enable: flag to control BTCM enablement132 * @loczrama: flag to dictate which TCM is at device address 0x0133 * @released_from_reset: flag to signal when core is out of reset134 */135struct k3_r5_core {136 struct list_head elem;137 struct device *dev;138 struct rproc *rproc;139 struct k3_r5_mem *mem;140 struct k3_r5_mem *sram;141 int num_mems;142 int num_sram;143 struct reset_control *reset;144 struct ti_sci_proc *tsp;145 const struct ti_sci_handle *ti_sci;146 u32 ti_sci_id;147 u32 atcm_enable;148 u32 btcm_enable;149 u32 loczrama;150 bool released_from_reset;151};152 153/**154 * struct k3_r5_rproc - K3 remote processor state155 * @dev: cached device pointer156 * @cluster: cached pointer to parent cluster structure157 * @mbox: mailbox channel handle158 * @client: mailbox client to request the mailbox channel159 * @rproc: rproc handle160 * @core: cached pointer to r5 core structure being used161 * @rmem: reserved memory regions data162 * @num_rmems: number of reserved memory regions163 */164struct k3_r5_rproc {165 struct device *dev;166 struct k3_r5_cluster *cluster;167 struct mbox_chan *mbox;168 struct mbox_client client;169 struct rproc *rproc;170 struct k3_r5_core *core;171 struct k3_r5_mem *rmem;172 int num_rmems;173};174 175/**176 * k3_r5_rproc_mbox_callback() - inbound mailbox message handler177 * @client: mailbox client pointer used for requesting the mailbox channel178 * @data: mailbox payload179 *180 * This handler is invoked by the OMAP mailbox driver whenever a mailbox181 * message is received. Usually, the mailbox payload simply contains182 * the index of the virtqueue that is kicked by the remote processor,183 * and we let remoteproc core handle it.184 *185 * In addition to virtqueue indices, we also have some out-of-band values186 * that indicate different events. Those values are deliberately very187 * large so they don't coincide with virtqueue indices.188 */189static void k3_r5_rproc_mbox_callback(struct mbox_client *client, void *data)190{191 struct k3_r5_rproc *kproc = container_of(client, struct k3_r5_rproc,192 client);193 struct device *dev = kproc->rproc->dev.parent;194 const char *name = kproc->rproc->name;195 u32 msg = omap_mbox_message(data);196 197 /* Do not forward message from a detached core */198 if (kproc->rproc->state == RPROC_DETACHED)199 return;200 201 dev_dbg(dev, "mbox msg: 0x%x\n", msg);202 203 switch (msg) {204 case RP_MBOX_CRASH:205 /*206 * remoteproc detected an exception, but error recovery is not207 * supported. So, just log this for now208 */209 dev_err(dev, "K3 R5F rproc %s crashed\n", name);210 break;211 case RP_MBOX_ECHO_REPLY:212 dev_info(dev, "received echo reply from %s\n", name);213 break;214 default:215 /* silently handle all other valid messages */216 if (msg >= RP_MBOX_READY && msg < RP_MBOX_END_MSG)217 return;218 if (msg > kproc->rproc->max_notifyid) {219 dev_dbg(dev, "dropping unknown message 0x%x", msg);220 return;221 }222 /* msg contains the index of the triggered vring */223 if (rproc_vq_interrupt(kproc->rproc, msg) == IRQ_NONE)224 dev_dbg(dev, "no message was found in vqid %d\n", msg);225 }226}227 228/* kick a virtqueue */229static void k3_r5_rproc_kick(struct rproc *rproc, int vqid)230{231 struct k3_r5_rproc *kproc = rproc->priv;232 struct device *dev = rproc->dev.parent;233 mbox_msg_t msg = (mbox_msg_t)vqid;234 int ret;235 236 /* Do not forward message to a detached core */237 if (kproc->rproc->state == RPROC_DETACHED)238 return;239 240 /* send the index of the triggered virtqueue in the mailbox payload */241 ret = mbox_send_message(kproc->mbox, (void *)msg);242 if (ret < 0)243 dev_err(dev, "failed to send mailbox message, status = %d\n",244 ret);245}246 247static int k3_r5_split_reset(struct k3_r5_core *core)248{249 int ret;250 251 ret = reset_control_assert(core->reset);252 if (ret) {253 dev_err(core->dev, "local-reset assert failed, ret = %d\n",254 ret);255 return ret;256 }257 258 ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,259 core->ti_sci_id);260 if (ret) {261 dev_err(core->dev, "module-reset assert failed, ret = %d\n",262 ret);263 if (reset_control_deassert(core->reset))264 dev_warn(core->dev, "local-reset deassert back failed\n");265 }266 267 return ret;268}269 270static int k3_r5_split_release(struct k3_r5_core *core)271{272 int ret;273 274 ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,275 core->ti_sci_id);276 if (ret) {277 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",278 ret);279 return ret;280 }281 282 ret = reset_control_deassert(core->reset);283 if (ret) {284 dev_err(core->dev, "local-reset deassert failed, ret = %d\n",285 ret);286 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,287 core->ti_sci_id))288 dev_warn(core->dev, "module-reset assert back failed\n");289 }290 291 return ret;292}293 294static int k3_r5_lockstep_reset(struct k3_r5_cluster *cluster)295{296 struct k3_r5_core *core;297 int ret;298 299 /* assert local reset on all applicable cores */300 list_for_each_entry(core, &cluster->cores, elem) {301 ret = reset_control_assert(core->reset);302 if (ret) {303 dev_err(core->dev, "local-reset assert failed, ret = %d\n",304 ret);305 core = list_prev_entry(core, elem);306 goto unroll_local_reset;307 }308 }309 310 /* disable PSC modules on all applicable cores */311 list_for_each_entry(core, &cluster->cores, elem) {312 ret = core->ti_sci->ops.dev_ops.put_device(core->ti_sci,313 core->ti_sci_id);314 if (ret) {315 dev_err(core->dev, "module-reset assert failed, ret = %d\n",316 ret);317 goto unroll_module_reset;318 }319 }320 321 return 0;322 323unroll_module_reset:324 list_for_each_entry_continue_reverse(core, &cluster->cores, elem) {325 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,326 core->ti_sci_id))327 dev_warn(core->dev, "module-reset assert back failed\n");328 }329 core = list_last_entry(&cluster->cores, struct k3_r5_core, elem);330unroll_local_reset:331 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {332 if (reset_control_deassert(core->reset))333 dev_warn(core->dev, "local-reset deassert back failed\n");334 }335 336 return ret;337}338 339static int k3_r5_lockstep_release(struct k3_r5_cluster *cluster)340{341 struct k3_r5_core *core;342 int ret;343 344 /* enable PSC modules on all applicable cores */345 list_for_each_entry_reverse(core, &cluster->cores, elem) {346 ret = core->ti_sci->ops.dev_ops.get_device(core->ti_sci,347 core->ti_sci_id);348 if (ret) {349 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",350 ret);351 core = list_next_entry(core, elem);352 goto unroll_module_reset;353 }354 }355 356 /* deassert local reset on all applicable cores */357 list_for_each_entry_reverse(core, &cluster->cores, elem) {358 ret = reset_control_deassert(core->reset);359 if (ret) {360 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",361 ret);362 goto unroll_local_reset;363 }364 }365 366 return 0;367 368unroll_local_reset:369 list_for_each_entry_continue(core, &cluster->cores, elem) {370 if (reset_control_assert(core->reset))371 dev_warn(core->dev, "local-reset assert back failed\n");372 }373 core = list_first_entry(&cluster->cores, struct k3_r5_core, elem);374unroll_module_reset:375 list_for_each_entry_from(core, &cluster->cores, elem) {376 if (core->ti_sci->ops.dev_ops.put_device(core->ti_sci,377 core->ti_sci_id))378 dev_warn(core->dev, "module-reset assert back failed\n");379 }380 381 return ret;382}383 384static inline int k3_r5_core_halt(struct k3_r5_core *core)385{386 return ti_sci_proc_set_control(core->tsp,387 PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0);388}389 390static inline int k3_r5_core_run(struct k3_r5_core *core)391{392 return ti_sci_proc_set_control(core->tsp,393 0, PROC_BOOT_CTRL_FLAG_R5_CORE_HALT);394}395 396static int k3_r5_rproc_request_mbox(struct rproc *rproc)397{398 struct k3_r5_rproc *kproc = rproc->priv;399 struct mbox_client *client = &kproc->client;400 struct device *dev = kproc->dev;401 int ret;402 403 client->dev = dev;404 client->tx_done = NULL;405 client->rx_callback = k3_r5_rproc_mbox_callback;406 client->tx_block = false;407 client->knows_txdone = false;408 409 kproc->mbox = mbox_request_channel(client, 0);410 if (IS_ERR(kproc->mbox))411 return dev_err_probe(dev, PTR_ERR(kproc->mbox),412 "mbox_request_channel failed\n");413 414 /*415 * Ping the remote processor, this is only for sanity-sake for now;416 * there is no functional effect whatsoever.417 *418 * Note that the reply will _not_ arrive immediately: this message419 * will wait in the mailbox fifo until the remote processor is booted.420 */421 ret = mbox_send_message(kproc->mbox, (void *)RP_MBOX_ECHO_REQUEST);422 if (ret < 0) {423 dev_err(dev, "mbox_send_message failed: %d\n", ret);424 mbox_free_channel(kproc->mbox);425 return ret;426 }427 428 return 0;429}430 431/*432 * The R5F cores have controls for both a reset and a halt/run. The code433 * execution from DDR requires the initial boot-strapping code to be run434 * from the internal TCMs. This function is used to release the resets on435 * applicable cores to allow loading into the TCMs. The .prepare() ops is436 * invoked by remoteproc core before any firmware loading, and is followed437 * by the .start() ops after loading to actually let the R5 cores run.438 *439 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to440 * execute code, but combines the TCMs from both cores. The resets for both441 * cores need to be released to make this possible, as the TCMs are in general442 * private to each core. Only Core0 needs to be unhalted for running the443 * cluster in this mode. The function uses the same reset logic as LockStep444 * mode for this (though the behavior is agnostic of the reset release order).445 * This callback is invoked only in remoteproc mode.446 */447static int k3_r5_rproc_prepare(struct rproc *rproc)448{449 struct k3_r5_rproc *kproc = rproc->priv;450 struct k3_r5_cluster *cluster = kproc->cluster;451 struct k3_r5_core *core = kproc->core;452 struct device *dev = kproc->dev;453 u32 ctrl = 0, cfg = 0, stat = 0;454 u64 boot_vec = 0;455 bool mem_init_dis;456 int ret;457 458 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl, &stat);459 if (ret < 0)460 return ret;461 mem_init_dis = !!(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS);462 463 /* Re-use LockStep-mode reset logic for Single-CPU mode */464 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||465 cluster->mode == CLUSTER_MODE_SINGLECPU) ?466 k3_r5_lockstep_release(cluster) : k3_r5_split_release(core);467 if (ret) {468 dev_err(dev, "unable to enable cores for TCM loading, ret = %d\n",469 ret);470 return ret;471 }472 473 /*474 * Newer IP revisions like on J7200 SoCs support h/w auto-initialization475 * of TCMs, so there is no need to perform the s/w memzero. This bit is476 * configurable through System Firmware, the default value does perform477 * auto-init, but account for it in case it is disabled478 */479 if (cluster->soc_data->tcm_ecc_autoinit && !mem_init_dis) {480 dev_dbg(dev, "leveraging h/w init for TCM memories\n");481 return 0;482 }483 484 /*485 * Zero out both TCMs unconditionally (access from v8 Arm core is not486 * affected by ATCM & BTCM enable configuration values) so that ECC487 * can be effective on all TCM addresses.488 */489 dev_dbg(dev, "zeroing out ATCM memory\n");490 memset(core->mem[0].cpu_addr, 0x00, core->mem[0].size);491 492 dev_dbg(dev, "zeroing out BTCM memory\n");493 memset(core->mem[1].cpu_addr, 0x00, core->mem[1].size);494 495 return 0;496}497 498/*499 * This function implements the .unprepare() ops and performs the complimentary500 * operations to that of the .prepare() ops. The function is used to assert the501 * resets on all applicable cores for the rproc device (depending on LockStep502 * or Split mode). This completes the second portion of powering down the R5F503 * cores. The cores themselves are only halted in the .stop() ops, and the504 * .unprepare() ops is invoked by the remoteproc core after the remoteproc is505 * stopped.506 *507 * The Single-CPU mode on applicable SoCs (eg: AM64x) combines the TCMs from508 * both cores. The access is made possible only with releasing the resets for509 * both cores, but with only Core0 unhalted. This function re-uses the same510 * reset assert logic as LockStep mode for this mode (though the behavior is511 * agnostic of the reset assert order). This callback is invoked only in512 * remoteproc mode.513 */514static int k3_r5_rproc_unprepare(struct rproc *rproc)515{516 struct k3_r5_rproc *kproc = rproc->priv;517 struct k3_r5_cluster *cluster = kproc->cluster;518 struct k3_r5_core *core = kproc->core;519 struct device *dev = kproc->dev;520 int ret;521 522 /* Re-use LockStep-mode reset logic for Single-CPU mode */523 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||524 cluster->mode == CLUSTER_MODE_SINGLECPU) ?525 k3_r5_lockstep_reset(cluster) : k3_r5_split_reset(core);526 if (ret)527 dev_err(dev, "unable to disable cores, ret = %d\n", ret);528 529 return ret;530}531 532/*533 * The R5F start sequence includes two different operations534 * 1. Configure the boot vector for R5F core(s)535 * 2. Unhalt/Run the R5F core(s)536 *537 * The sequence is different between LockStep and Split modes. The LockStep538 * mode requires the boot vector to be configured only for Core0, and then539 * unhalt both the cores to start the execution - Core1 needs to be unhalted540 * first followed by Core0. The Split-mode requires that Core0 to be maintained541 * always in a higher power state that Core1 (implying Core1 needs to be started542 * always only after Core0 is started).543 *544 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute545 * code, so only Core0 needs to be unhalted. The function uses the same logic546 * flow as Split-mode for this. This callback is invoked only in remoteproc547 * mode.548 */549static int k3_r5_rproc_start(struct rproc *rproc)550{551 struct k3_r5_rproc *kproc = rproc->priv;552 struct k3_r5_cluster *cluster = kproc->cluster;553 struct device *dev = kproc->dev;554 struct k3_r5_core *core0, *core;555 u32 boot_addr;556 int ret;557 558 boot_addr = rproc->bootaddr;559 /* TODO: add boot_addr sanity checking */560 dev_dbg(dev, "booting R5F core using boot addr = 0x%x\n", boot_addr);561 562 /* boot vector need not be programmed for Core1 in LockStep mode */563 core = kproc->core;564 ret = ti_sci_proc_set_config(core->tsp, boot_addr, 0, 0);565 if (ret)566 return ret;567 568 /* unhalt/run all applicable cores */569 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {570 list_for_each_entry_reverse(core, &cluster->cores, elem) {571 ret = k3_r5_core_run(core);572 if (ret)573 goto unroll_core_run;574 }575 } else {576 /* do not allow core 1 to start before core 0 */577 core0 = list_first_entry(&cluster->cores, struct k3_r5_core,578 elem);579 if (core != core0 && core0->rproc->state == RPROC_OFFLINE) {580 dev_err(dev, "%s: can not start core 1 before core 0\n",581 __func__);582 return -EPERM;583 }584 585 ret = k3_r5_core_run(core);586 if (ret)587 return ret;588 589 core->released_from_reset = true;590 wake_up_interruptible(&cluster->core_transition);591 }592 593 return 0;594 595unroll_core_run:596 list_for_each_entry_continue(core, &cluster->cores, elem) {597 if (k3_r5_core_halt(core))598 dev_warn(core->dev, "core halt back failed\n");599 }600 return ret;601}602 603/*604 * The R5F stop function includes the following operations605 * 1. Halt R5F core(s)606 *607 * The sequence is different between LockStep and Split modes, and the order608 * of cores the operations are performed are also in general reverse to that609 * of the start function. The LockStep mode requires each operation to be610 * performed first on Core0 followed by Core1. The Split-mode requires that611 * Core0 to be maintained always in a higher power state that Core1 (implying612 * Core1 needs to be stopped first before Core0).613 *614 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute615 * code, so only Core0 needs to be halted. The function uses the same logic616 * flow as Split-mode for this.617 *618 * Note that the R5F halt operation in general is not effective when the R5F619 * core is running, but is needed to make sure the core won't run after620 * deasserting the reset the subsequent time. The asserting of reset can621 * be done here, but is preferred to be done in the .unprepare() ops - this622 * maintains the symmetric behavior between the .start(), .stop(), .prepare()623 * and .unprepare() ops, and also balances them well between sysfs 'state'624 * flow and device bind/unbind or module removal. This callback is invoked625 * only in remoteproc mode.626 */627static int k3_r5_rproc_stop(struct rproc *rproc)628{629 struct k3_r5_rproc *kproc = rproc->priv;630 struct k3_r5_cluster *cluster = kproc->cluster;631 struct device *dev = kproc->dev;632 struct k3_r5_core *core1, *core = kproc->core;633 int ret;634 635 /* halt all applicable cores */636 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {637 list_for_each_entry(core, &cluster->cores, elem) {638 ret = k3_r5_core_halt(core);639 if (ret) {640 core = list_prev_entry(core, elem);641 goto unroll_core_halt;642 }643 }644 } else {645 /* do not allow core 0 to stop before core 1 */646 core1 = list_last_entry(&cluster->cores, struct k3_r5_core,647 elem);648 if (core != core1 && core1->rproc->state != RPROC_OFFLINE) {649 dev_err(dev, "%s: can not stop core 0 before core 1\n",650 __func__);651 ret = -EPERM;652 goto out;653 }654 655 ret = k3_r5_core_halt(core);656 if (ret)657 goto out;658 }659 660 return 0;661 662unroll_core_halt:663 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {664 if (k3_r5_core_run(core))665 dev_warn(core->dev, "core run back failed\n");666 }667out:668 return ret;669}670 671/*672 * Attach to a running R5F remote processor (IPC-only mode)673 *674 * The R5F attach callback is a NOP. The remote processor is already booted, and675 * all required resources have been acquired during probe routine, so there is676 * no need to issue any TI-SCI commands to boot the R5F cores in IPC-only mode.677 * This callback is invoked only in IPC-only mode and exists because678 * rproc_validate() checks for its existence.679 */680static int k3_r5_rproc_attach(struct rproc *rproc) { return 0; }681 682/*683 * Detach from a running R5F remote processor (IPC-only mode)684 *685 * The R5F detach callback is a NOP. The R5F cores are not stopped and will be686 * left in booted state in IPC-only mode. This callback is invoked only in687 * IPC-only mode and exists for sanity sake.688 */689static int k3_r5_rproc_detach(struct rproc *rproc) { return 0; }690 691/*692 * This function implements the .get_loaded_rsc_table() callback and is used693 * to provide the resource table for the booted R5F in IPC-only mode. The K3 R5F694 * firmwares follow a design-by-contract approach and are expected to have the695 * resource table at the base of the DDR region reserved for firmware usage.696 * This provides flexibility for the remote processor to be booted by different697 * bootloaders that may or may not have the ability to publish the resource table698 * address and size through a DT property. This callback is invoked only in699 * IPC-only mode.700 */701static struct resource_table *k3_r5_get_loaded_rsc_table(struct rproc *rproc,702 size_t *rsc_table_sz)703{704 struct k3_r5_rproc *kproc = rproc->priv;705 struct device *dev = kproc->dev;706 707 if (!kproc->rmem[0].cpu_addr) {708 dev_err(dev, "memory-region #1 does not exist, loaded rsc table can't be found");709 return ERR_PTR(-ENOMEM);710 }711 712 /*713 * NOTE: The resource table size is currently hard-coded to a maximum714 * of 256 bytes. The most common resource table usage for K3 firmwares715 * is to only have the vdev resource entry and an optional trace entry.716 * The exact size could be computed based on resource table address, but717 * the hard-coded value suffices to support the IPC-only mode.718 */719 *rsc_table_sz = 256;720 return (struct resource_table *)kproc->rmem[0].cpu_addr;721}722 723/*724 * Internal Memory translation helper725 *726 * Custom function implementing the rproc .da_to_va ops to provide address727 * translation (device address to kernel virtual address) for internal RAMs728 * present in a DSP or IPU device). The translated addresses can be used729 * either by the remoteproc core for loading, or by any rpmsg bus drivers.730 */731static void *k3_r5_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)732{733 struct k3_r5_rproc *kproc = rproc->priv;734 struct k3_r5_core *core = kproc->core;735 void __iomem *va = NULL;736 phys_addr_t bus_addr;737 u32 dev_addr, offset;738 size_t size;739 int i;740 741 if (len == 0)742 return NULL;743 744 /* handle both R5 and SoC views of ATCM and BTCM */745 for (i = 0; i < core->num_mems; i++) {746 bus_addr = core->mem[i].bus_addr;747 dev_addr = core->mem[i].dev_addr;748 size = core->mem[i].size;749 750 /* handle R5-view addresses of TCMs */751 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {752 offset = da - dev_addr;753 va = core->mem[i].cpu_addr + offset;754 return (__force void *)va;755 }756 757 /* handle SoC-view addresses of TCMs */758 if (da >= bus_addr && ((da + len) <= (bus_addr + size))) {759 offset = da - bus_addr;760 va = core->mem[i].cpu_addr + offset;761 return (__force void *)va;762 }763 }764 765 /* handle any SRAM regions using SoC-view addresses */766 for (i = 0; i < core->num_sram; i++) {767 dev_addr = core->sram[i].dev_addr;768 size = core->sram[i].size;769 770 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {771 offset = da - dev_addr;772 va = core->sram[i].cpu_addr + offset;773 return (__force void *)va;774 }775 }776 777 /* handle static DDR reserved memory regions */778 for (i = 0; i < kproc->num_rmems; i++) {779 dev_addr = kproc->rmem[i].dev_addr;780 size = kproc->rmem[i].size;781 782 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {783 offset = da - dev_addr;784 va = kproc->rmem[i].cpu_addr + offset;785 return (__force void *)va;786 }787 }788 789 return NULL;790}791 792static const struct rproc_ops k3_r5_rproc_ops = {793 .prepare = k3_r5_rproc_prepare,794 .unprepare = k3_r5_rproc_unprepare,795 .start = k3_r5_rproc_start,796 .stop = k3_r5_rproc_stop,797 .kick = k3_r5_rproc_kick,798 .da_to_va = k3_r5_rproc_da_to_va,799};800 801/*802 * Internal R5F Core configuration803 *804 * Each R5FSS has a cluster-level setting for configuring the processor805 * subsystem either in a safety/fault-tolerant LockStep mode or a performance806 * oriented Split mode on most SoCs. A fewer SoCs support a non-safety mode807 * as an alternate for LockStep mode that exercises only a single R5F core808 * called Single-CPU mode. Each R5F core has a number of settings to either809 * enable/disable each of the TCMs, control which TCM appears at the R5F core's810 * address 0x0. These settings need to be configured before the resets for the811 * corresponding core are released. These settings are all protected and managed812 * by the System Processor.813 *814 * This function is used to pre-configure these settings for each R5F core, and815 * the configuration is all done through various ti_sci_proc functions that816 * communicate with the System Processor. The function also ensures that both817 * the cores are halted before the .prepare() step.818 *819 * The function is called from k3_r5_cluster_rproc_init() and is invoked either820 * once (in LockStep mode or Single-CPU modes) or twice (in Split mode). Support821 * for LockStep-mode is dictated by an eFUSE register bit, and the config822 * settings retrieved from DT are adjusted accordingly as per the permitted823 * cluster mode. Another eFUSE register bit dictates if the R5F cluster only824 * supports a Single-CPU mode. All cluster level settings like Cluster mode and825 * TEINIT (exception handling state dictating ARM or Thumb mode) can only be set826 * and retrieved using Core0.827 *828 * The function behavior is different based on the cluster mode. The R5F cores829 * are configured independently as per their individual settings in Split mode.830 * They are identically configured in LockStep mode using the primary Core0831 * settings. However, some individual settings cannot be set in LockStep mode.832 * This is overcome by switching to Split-mode initially and then programming833 * both the cores with the same settings, before reconfiguing again for834 * LockStep mode.835 */836static int k3_r5_rproc_configure(struct k3_r5_rproc *kproc)837{838 struct k3_r5_cluster *cluster = kproc->cluster;839 struct device *dev = kproc->dev;840 struct k3_r5_core *core0, *core, *temp;841 u32 ctrl = 0, cfg = 0, stat = 0;842 u32 set_cfg = 0, clr_cfg = 0;843 u64 boot_vec = 0;844 bool lockstep_en;845 bool single_cpu;846 int ret;847 848 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);849 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||850 cluster->mode == CLUSTER_MODE_SINGLECPU ||851 cluster->mode == CLUSTER_MODE_SINGLECORE) {852 core = core0;853 } else {854 core = kproc->core;855 }856 857 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl,858 &stat);859 if (ret < 0)860 return ret;861 862 dev_dbg(dev, "boot_vector = 0x%llx, cfg = 0x%x ctrl = 0x%x stat = 0x%x\n",863 boot_vec, cfg, ctrl, stat);864 865 single_cpu = !!(stat & PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY);866 lockstep_en = !!(stat & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED);867 868 /* Override to single CPU mode if set in status flag */869 if (single_cpu && cluster->mode == CLUSTER_MODE_SPLIT) {870 dev_err(cluster->dev, "split-mode not permitted, force configuring for single-cpu mode\n");871 cluster->mode = CLUSTER_MODE_SINGLECPU;872 }873 874 /* Override to split mode if lockstep enable bit is not set in status flag */875 if (!lockstep_en && cluster->mode == CLUSTER_MODE_LOCKSTEP) {876 dev_err(cluster->dev, "lockstep mode not permitted, force configuring for split-mode\n");877 cluster->mode = CLUSTER_MODE_SPLIT;878 }879 880 /* always enable ARM mode and set boot vector to 0 */881 boot_vec = 0x0;882 if (core == core0) {883 clr_cfg = PROC_BOOT_CFG_FLAG_R5_TEINIT;884 /*885 * Single-CPU configuration bit can only be configured886 * on Core0 and system firmware will NACK any requests887 * with the bit configured, so program it only on888 * permitted cores889 */890 if (cluster->mode == CLUSTER_MODE_SINGLECPU ||891 cluster->mode == CLUSTER_MODE_SINGLECORE) {892 set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE;893 } else {894 /*895 * LockStep configuration bit is Read-only on Split-mode896 * _only_ devices and system firmware will NACK any897 * requests with the bit configured, so program it only898 * on permitted devices899 */900 if (lockstep_en)901 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;902 }903 }904 905 if (core->atcm_enable)906 set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;907 else908 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;909 910 if (core->btcm_enable)911 set_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;912 else913 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;914 915 if (core->loczrama)916 set_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;917 else918 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;919 920 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {921 /*922 * work around system firmware limitations to make sure both923 * cores are programmed symmetrically in LockStep. LockStep924 * and TEINIT config is only allowed with Core0.925 */926 list_for_each_entry(temp, &cluster->cores, elem) {927 ret = k3_r5_core_halt(temp);928 if (ret)929 goto out;930 931 if (temp != core) {932 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;933 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_TEINIT;934 }935 ret = ti_sci_proc_set_config(temp->tsp, boot_vec,936 set_cfg, clr_cfg);937 if (ret)938 goto out;939 }940 941 set_cfg = PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;942 clr_cfg = 0;943 ret = ti_sci_proc_set_config(core->tsp, boot_vec,944 set_cfg, clr_cfg);945 } else {946 ret = k3_r5_core_halt(core);947 if (ret)948 goto out;949 950 ret = ti_sci_proc_set_config(core->tsp, boot_vec,951 set_cfg, clr_cfg);952 }953 954out:955 return ret;956}957 958static int k3_r5_reserved_mem_init(struct k3_r5_rproc *kproc)959{960 struct device *dev = kproc->dev;961 struct device_node *np = dev_of_node(dev);962 struct device_node *rmem_np;963 struct reserved_mem *rmem;964 int num_rmems;965 int ret, i;966 967 num_rmems = of_property_count_elems_of_size(np, "memory-region",968 sizeof(phandle));969 if (num_rmems <= 0) {970 dev_err(dev, "device does not have reserved memory regions, ret = %d\n",971 num_rmems);972 return -EINVAL;973 }974 if (num_rmems < 2) {975 dev_err(dev, "device needs at least two memory regions to be defined, num = %d\n",976 num_rmems);977 return -EINVAL;978 }979 980 /* use reserved memory region 0 for vring DMA allocations */981 ret = of_reserved_mem_device_init_by_idx(dev, np, 0);982 if (ret) {983 dev_err(dev, "device cannot initialize DMA pool, ret = %d\n",984 ret);985 return ret;986 }987 988 num_rmems--;989 kproc->rmem = kcalloc(num_rmems, sizeof(*kproc->rmem), GFP_KERNEL);990 if (!kproc->rmem) {991 ret = -ENOMEM;992 goto release_rmem;993 }994 995 /* use remaining reserved memory regions for static carveouts */996 for (i = 0; i < num_rmems; i++) {997 rmem_np = of_parse_phandle(np, "memory-region", i + 1);998 if (!rmem_np) {999 ret = -EINVAL;1000 goto unmap_rmem;1001 }1002 1003 rmem = of_reserved_mem_lookup(rmem_np);1004 if (!rmem) {1005 of_node_put(rmem_np);1006 ret = -EINVAL;1007 goto unmap_rmem;1008 }1009 of_node_put(rmem_np);1010 1011 kproc->rmem[i].bus_addr = rmem->base;1012 /*1013 * R5Fs do not have an MMU, but have a Region Address Translator1014 * (RAT) module that provides a fixed entry translation between1015 * the 32-bit processor addresses to 64-bit bus addresses. The1016 * RAT is programmable only by the R5F cores. Support for RAT1017 * is currently not supported, so 64-bit address regions are not1018 * supported. The absence of MMUs implies that the R5F device1019 * addresses/supported memory regions are restricted to 32-bit1020 * bus addresses, and are identical1021 */1022 kproc->rmem[i].dev_addr = (u32)rmem->base;1023 kproc->rmem[i].size = rmem->size;1024 kproc->rmem[i].cpu_addr = ioremap_wc(rmem->base, rmem->size);1025 if (!kproc->rmem[i].cpu_addr) {1026 dev_err(dev, "failed to map reserved memory#%d at %pa of size %pa\n",1027 i + 1, &rmem->base, &rmem->size);1028 ret = -ENOMEM;1029 goto unmap_rmem;1030 }1031 1032 dev_dbg(dev, "reserved memory%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",1033 i + 1, &kproc->rmem[i].bus_addr,1034 kproc->rmem[i].size, kproc->rmem[i].cpu_addr,1035 kproc->rmem[i].dev_addr);1036 }1037 kproc->num_rmems = num_rmems;1038 1039 return 0;1040 1041unmap_rmem:1042 for (i--; i >= 0; i--)1043 iounmap(kproc->rmem[i].cpu_addr);1044 kfree(kproc->rmem);1045release_rmem:1046 of_reserved_mem_device_release(dev);1047 return ret;1048}1049 1050static void k3_r5_reserved_mem_exit(struct k3_r5_rproc *kproc)1051{1052 int i;1053 1054 for (i = 0; i < kproc->num_rmems; i++)1055 iounmap(kproc->rmem[i].cpu_addr);1056 kfree(kproc->rmem);1057 1058 of_reserved_mem_device_release(kproc->dev);1059}1060 1061/*1062 * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs,1063 * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both1064 * cores are usable in Split-mode, but only the Core0 TCMs can be used in1065 * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by1066 * leveraging the Core1 TCMs as well in certain modes where they would have1067 * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs, Single-CPU mode on1068 * AM64x SoCs). This is done by making a Core1 TCM visible immediately after the1069 * corresponding Core0 TCM. The SoC memory map uses the larger 64 KB sizes for1070 * the Core0 TCMs, and the dts representation reflects this increased size on1071 * supported SoCs. The Core0 TCM sizes therefore have to be adjusted to only1072 * half the original size in Split mode.1073 */1074static void k3_r5_adjust_tcm_sizes(struct k3_r5_rproc *kproc)1075{1076 struct k3_r5_cluster *cluster = kproc->cluster;1077 struct k3_r5_core *core = kproc->core;1078 struct device *cdev = core->dev;1079 struct k3_r5_core *core0;1080 1081 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||1082 cluster->mode == CLUSTER_MODE_SINGLECPU ||1083 cluster->mode == CLUSTER_MODE_SINGLECORE ||1084 !cluster->soc_data->tcm_is_double)1085 return;1086 1087 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);1088 if (core == core0) {1089 WARN_ON(core->mem[0].size != SZ_64K);1090 WARN_ON(core->mem[1].size != SZ_64K);1091 1092 core->mem[0].size /= 2;1093 core->mem[1].size /= 2;1094 1095 dev_dbg(cdev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n",1096 core->mem[0].size, core->mem[1].size);1097 }1098}1099 1100/*1101 * This function checks and configures a R5F core for IPC-only or remoteproc1102 * mode. The driver is configured to be in IPC-only mode for a R5F core when1103 * the core has been loaded and started by a bootloader. The IPC-only mode is1104 * detected by querying the System Firmware for reset, power on and halt status1105 * and ensuring that the core is running. Any incomplete steps at bootloader1106 * are validated and errored out.1107 *1108 * In IPC-only mode, the driver state flags for ATCM, BTCM and LOCZRAMA settings1109 * and cluster mode parsed originally from kernel DT are updated to reflect the1110 * actual values configured by bootloader. The driver internal device memory1111 * addresses for TCMs are also updated.1112 */1113static int k3_r5_rproc_configure_mode(struct k3_r5_rproc *kproc)1114{1115 struct k3_r5_cluster *cluster = kproc->cluster;1116 struct k3_r5_core *core = kproc->core;1117 struct device *cdev = core->dev;1118 bool r_state = false, c_state = false, lockstep_en = false, single_cpu = false;1119 u32 ctrl = 0, cfg = 0, stat = 0, halted = 0;1120 u64 boot_vec = 0;1121 u32 atcm_enable, btcm_enable, loczrama;1122 struct k3_r5_core *core0;1123 enum cluster_mode mode = cluster->mode;1124 int reset_ctrl_status;1125 int ret;1126 1127 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);1128 1129 ret = core->ti_sci->ops.dev_ops.is_on(core->ti_sci, core->ti_sci_id,1130 &r_state, &c_state);1131 if (ret) {1132 dev_err(cdev, "failed to get initial state, mode cannot be determined, ret = %d\n",1133 ret);1134 return ret;1135 }1136 if (r_state != c_state) {1137 dev_warn(cdev, "R5F core may have been powered on by a different host, programmed state (%d) != actual state (%d)\n",1138 r_state, c_state);1139 }1140 1141 reset_ctrl_status = reset_control_status(core->reset);1142 if (reset_ctrl_status < 0) {1143 dev_err(cdev, "failed to get initial local reset status, ret = %d\n",1144 reset_ctrl_status);1145 return reset_ctrl_status;1146 }1147 1148 /*1149 * Skip the waiting mechanism for sequential power-on of cores if the1150 * core has already been booted by another entity.1151 */1152 core->released_from_reset = c_state;1153 1154 ret = ti_sci_proc_get_status(core->tsp, &boot_vec, &cfg, &ctrl,1155 &stat);1156 if (ret < 0) {1157 dev_err(cdev, "failed to get initial processor status, ret = %d\n",1158 ret);1159 return ret;1160 }1161 atcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_ATCM_EN ? 1 : 0;1162 btcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_BTCM_EN ? 1 : 0;1163 loczrama = cfg & PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE ? 1 : 0;1164 single_cpu = cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ? 1 : 0;1165 lockstep_en = cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP ? 1 : 0;1166 1167 if (single_cpu && mode != CLUSTER_MODE_SINGLECORE)1168 mode = CLUSTER_MODE_SINGLECPU;1169 if (lockstep_en)1170 mode = CLUSTER_MODE_LOCKSTEP;1171 1172 halted = ctrl & PROC_BOOT_CTRL_FLAG_R5_CORE_HALT;1173 1174 /*1175 * IPC-only mode detection requires both local and module resets to1176 * be deasserted and R5F core to be unhalted. Local reset status is1177 * irrelevant if module reset is asserted (POR value has local reset1178 * deasserted), and is deemed as remoteproc mode1179 */1180 if (c_state && !reset_ctrl_status && !halted) {1181 dev_info(cdev, "configured R5F for IPC-only mode\n");1182 kproc->rproc->state = RPROC_DETACHED;1183 ret = 1;1184 /* override rproc ops with only required IPC-only mode ops */1185 kproc->rproc->ops->prepare = NULL;1186 kproc->rproc->ops->unprepare = NULL;1187 kproc->rproc->ops->start = NULL;1188 kproc->rproc->ops->stop = NULL;1189 kproc->rproc->ops->attach = k3_r5_rproc_attach;1190 kproc->rproc->ops->detach = k3_r5_rproc_detach;1191 kproc->rproc->ops->get_loaded_rsc_table =1192 k3_r5_get_loaded_rsc_table;1193 } else if (!c_state) {1194 dev_info(cdev, "configured R5F for remoteproc mode\n");1195 ret = 0;1196 } else {1197 dev_err(cdev, "mismatched mode: local_reset = %s, module_reset = %s, core_state = %s\n",1198 !reset_ctrl_status ? "deasserted" : "asserted",1199 c_state ? "deasserted" : "asserted",1200 halted ? "halted" : "unhalted");1201 ret = -EINVAL;1202 }1203 1204 /* fixup TCMs, cluster & core flags to actual values in IPC-only mode */1205 if (ret > 0) {1206 if (core == core0)1207 cluster->mode = mode;1208 core->atcm_enable = atcm_enable;1209 core->btcm_enable = btcm_enable;1210 core->loczrama = loczrama;1211 core->mem[0].dev_addr = loczrama ? 0 : K3_R5_TCM_DEV_ADDR;1212 core->mem[1].dev_addr = loczrama ? K3_R5_TCM_DEV_ADDR : 0;1213 }1214 1215 return ret;1216}1217 1218static int k3_r5_cluster_rproc_init(struct platform_device *pdev)1219{1220 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);1221 struct device *dev = &pdev->dev;1222 struct k3_r5_rproc *kproc;1223 struct k3_r5_core *core, *core1;1224 struct device *cdev;1225 const char *fw_name;1226 struct rproc *rproc;1227 int ret, ret1;1228 1229 core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);1230 list_for_each_entry(core, &cluster->cores, elem) {1231 cdev = core->dev;1232 ret = rproc_of_parse_firmware(cdev, 0, &fw_name);1233 if (ret) {1234 dev_err(dev, "failed to parse firmware-name property, ret = %d\n",1235 ret);1236 goto out;1237 }1238 1239 rproc = devm_rproc_alloc(cdev, dev_name(cdev), &k3_r5_rproc_ops,1240 fw_name, sizeof(*kproc));1241 if (!rproc) {1242 ret = -ENOMEM;1243 goto out;1244 }1245 1246 /* K3 R5s have a Region Address Translator (RAT) but no MMU */1247 rproc->has_iommu = false;1248 /* error recovery is not supported at present */1249 rproc->recovery_disabled = true;1250 1251 kproc = rproc->priv;1252 kproc->cluster = cluster;1253 kproc->core = core;1254 kproc->dev = cdev;1255 kproc->rproc = rproc;1256 core->rproc = rproc;1257 1258 ret = k3_r5_rproc_request_mbox(rproc);1259 if (ret)1260 return ret;1261 1262 ret = k3_r5_rproc_configure_mode(kproc);1263 if (ret < 0)1264 goto out;1265 if (ret)1266 goto init_rmem;1267 1268 ret = k3_r5_rproc_configure(kproc);1269 if (ret) {1270 dev_err(dev, "initial configure failed, ret = %d\n",1271 ret);1272 goto out;1273 }1274 1275init_rmem:1276 k3_r5_adjust_tcm_sizes(kproc);1277 1278 ret = k3_r5_reserved_mem_init(kproc);1279 if (ret) {1280 dev_err(dev, "reserved memory init failed, ret = %d\n",1281 ret);1282 goto out;1283 }1284 1285 ret = rproc_add(rproc);1286 if (ret) {1287 dev_err(dev, "rproc_add failed, ret = %d\n", ret);1288 goto err_add;1289 }1290 1291 /* create only one rproc in lockstep, single-cpu or1292 * single core mode1293 */1294 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||1295 cluster->mode == CLUSTER_MODE_SINGLECPU ||1296 cluster->mode == CLUSTER_MODE_SINGLECORE)1297 break;1298 1299 /*1300 * R5 cores require to be powered on sequentially, core01301 * should be in higher power state than core1 in a cluster1302 * So, wait for current core to power up before proceeding1303 * to next core and put timeout of 2sec for each core.1304 *1305 * This waiting mechanism is necessary because1306 * rproc_auto_boot_callback() for core1 can be called before1307 * core0 due to thread execution order.1308 */1309 ret = wait_event_interruptible_timeout(cluster->core_transition,1310 core->released_from_reset,1311 msecs_to_jiffies(2000));1312 if (ret <= 0) {1313 dev_err(dev,1314 "Timed out waiting for %s core to power up!\n",1315 rproc->name);1316 goto err_powerup;1317 }1318 }1319 1320 return 0;1321 1322err_split:1323 if (rproc->state == RPROC_ATTACHED) {1324 ret1 = rproc_detach(rproc);1325 if (ret1) {1326 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n",1327 ret1);1328 return ret1;1329 }1330 }1331 1332err_powerup:1333 rproc_del(rproc);1334err_add:1335 k3_r5_reserved_mem_exit(kproc);1336out:1337 /* undo core0 upon any failures on core1 in split-mode */1338 if (cluster->mode == CLUSTER_MODE_SPLIT && core == core1) {1339 core = list_prev_entry(core, elem);1340 rproc = core->rproc;1341 kproc = rproc->priv;1342 goto err_split;1343 }1344 return ret;1345}1346 1347static void k3_r5_cluster_rproc_exit(void *data)1348{1349 struct k3_r5_cluster *cluster = platform_get_drvdata(data);1350 struct k3_r5_rproc *kproc;1351 struct k3_r5_core *core;1352 struct rproc *rproc;1353 int ret;1354 1355 /*1356 * lockstep mode and single-cpu modes have only one rproc associated1357 * with first core, whereas split-mode has two rprocs associated with1358 * each core, and requires that core1 be powered down first1359 */1360 core = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||1361 cluster->mode == CLUSTER_MODE_SINGLECPU) ?1362 list_first_entry(&cluster->cores, struct k3_r5_core, elem) :1363 list_last_entry(&cluster->cores, struct k3_r5_core, elem);1364 1365 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {1366 rproc = core->rproc;1367 kproc = rproc->priv;1368 1369 if (rproc->state == RPROC_ATTACHED) {1370 ret = rproc_detach(rproc);1371 if (ret) {1372 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n", ret);1373 return;1374 }1375 }1376 1377 mbox_free_channel(kproc->mbox);1378 1379 rproc_del(rproc);1380 1381 k3_r5_reserved_mem_exit(kproc);1382 }1383}1384 1385static int k3_r5_core_of_get_internal_memories(struct platform_device *pdev,1386 struct k3_r5_core *core)1387{1388 static const char * const mem_names[] = {"atcm", "btcm"};1389 struct device *dev = &pdev->dev;1390 struct resource *res;1391 int num_mems;1392 int i;1393 1394 num_mems = ARRAY_SIZE(mem_names);1395 core->mem = devm_kcalloc(dev, num_mems, sizeof(*core->mem), GFP_KERNEL);1396 if (!core->mem)1397 return -ENOMEM;1398 1399 for (i = 0; i < num_mems; i++) {1400 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,1401 mem_names[i]);1402 if (!res) {1403 dev_err(dev, "found no memory resource for %s\n",1404 mem_names[i]);1405 return -EINVAL;1406 }1407 if (!devm_request_mem_region(dev, res->start,1408 resource_size(res),1409 dev_name(dev))) {1410 dev_err(dev, "could not request %s region for resource\n",1411 mem_names[i]);1412 return -EBUSY;1413 }1414 1415 /*1416 * TCMs are designed in general to support RAM-like backing1417 * memories. So, map these as Normal Non-Cached memories. This1418 * also avoids/fixes any potential alignment faults due to1419 * unaligned data accesses when using memcpy() or memset()1420 * functions (normally seen with device type memory).1421 */1422 core->mem[i].cpu_addr = devm_ioremap_wc(dev, res->start,1423 resource_size(res));1424 if (!core->mem[i].cpu_addr) {1425 dev_err(dev, "failed to map %s memory\n", mem_names[i]);1426 return -ENOMEM;1427 }1428 core->mem[i].bus_addr = res->start;1429 1430 /*1431 * TODO:1432 * The R5F cores can place ATCM & BTCM anywhere in its address1433 * based on the corresponding Region Registers in the System1434 * Control coprocessor. For now, place ATCM and BTCM at1435 * addresses 0 and 0x41010000 (same as the bus address on AM65x1436 * SoCs) based on loczrama setting1437 */1438 if (!strcmp(mem_names[i], "atcm")) {1439 core->mem[i].dev_addr = core->loczrama ?1440 0 : K3_R5_TCM_DEV_ADDR;1441 } else {1442 core->mem[i].dev_addr = core->loczrama ?1443 K3_R5_TCM_DEV_ADDR : 0;1444 }1445 core->mem[i].size = resource_size(res);1446 1447 dev_dbg(dev, "memory %5s: bus addr %pa size 0x%zx va %pK da 0x%x\n",1448 mem_names[i], &core->mem[i].bus_addr,1449 core->mem[i].size, core->mem[i].cpu_addr,1450 core->mem[i].dev_addr);1451 }1452 core->num_mems = num_mems;1453 1454 return 0;1455}1456 1457static int k3_r5_core_of_get_sram_memories(struct platform_device *pdev,1458 struct k3_r5_core *core)1459{1460 struct device_node *np = pdev->dev.of_node;1461 struct device *dev = &pdev->dev;1462 struct device_node *sram_np;1463 struct resource res;1464 int num_sram;1465 int i, ret;1466 1467 num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle));1468 if (num_sram <= 0) {1469 dev_dbg(dev, "device does not use reserved on-chip memories, num_sram = %d\n",1470 num_sram);1471 return 0;1472 }1473 1474 core->sram = devm_kcalloc(dev, num_sram, sizeof(*core->sram), GFP_KERNEL);1475 if (!core->sram)1476 return -ENOMEM;1477 1478 for (i = 0; i < num_sram; i++) {1479 sram_np = of_parse_phandle(np, "sram", i);1480 if (!sram_np)1481 return -EINVAL;1482 1483 if (!of_device_is_available(sram_np)) {1484 of_node_put(sram_np);1485 return -EINVAL;1486 }1487 1488 ret = of_address_to_resource(sram_np, 0, &res);1489 of_node_put(sram_np);1490 if (ret)1491 return -EINVAL;1492 1493 core->sram[i].bus_addr = res.start;1494 core->sram[i].dev_addr = res.start;1495 core->sram[i].size = resource_size(&res);1496 core->sram[i].cpu_addr = devm_ioremap_wc(dev, res.start,1497 resource_size(&res));1498 if (!core->sram[i].cpu_addr) {1499 dev_err(dev, "failed to parse and map sram%d memory at %pad\n",1500 i, &res.start);1501 return -ENOMEM;1502 }1503 1504 dev_dbg(dev, "memory sram%d: bus addr %pa size 0x%zx va %pK da 0x%x\n",1505 i, &core->sram[i].bus_addr,1506 core->sram[i].size, core->sram[i].cpu_addr,1507 core->sram[i].dev_addr);1508 }1509 core->num_sram = num_sram;1510 1511 return 0;1512}1513 1514static int k3_r5_core_of_init(struct platform_device *pdev)1515{1516 struct device *dev = &pdev->dev;1517 struct device_node *np = dev_of_node(dev);1518 struct k3_r5_core *core;1519 int ret;1520 1521 if (!devres_open_group(dev, k3_r5_core_of_init, GFP_KERNEL))1522 return -ENOMEM;1523 1524 core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);1525 if (!core) {1526 ret = -ENOMEM;1527 goto err;1528 }1529 1530 core->dev = dev;1531 /*1532 * Use SoC Power-on-Reset values as default if no DT properties are1533 * used to dictate the TCM configurations1534 */1535 core->atcm_enable = 0;1536 core->btcm_enable = 1;1537 core->loczrama = 1;1538 1539 ret = of_property_read_u32(np, "ti,atcm-enable", &core->atcm_enable);1540 if (ret < 0 && ret != -EINVAL) {1541 dev_err(dev, "invalid format for ti,atcm-enable, ret = %d\n",1542 ret);1543 goto err;1544 }1545 1546 ret = of_property_read_u32(np, "ti,btcm-enable", &core->btcm_enable);1547 if (ret < 0 && ret != -EINVAL) {1548 dev_err(dev, "invalid format for ti,btcm-enable, ret = %d\n",1549 ret);1550 goto err;1551 }1552 1553 ret = of_property_read_u32(np, "ti,loczrama", &core->loczrama);1554 if (ret < 0 && ret != -EINVAL) {1555 dev_err(dev, "invalid format for ti,loczrama, ret = %d\n", ret);1556 goto err;1557 }1558 1559 core->ti_sci = devm_ti_sci_get_by_phandle(dev, "ti,sci");1560 if (IS_ERR(core->ti_sci)) {1561 ret = PTR_ERR(core->ti_sci);1562 if (ret != -EPROBE_DEFER) {1563 dev_err(dev, "failed to get ti-sci handle, ret = %d\n",1564 ret);1565 }1566 core->ti_sci = NULL;1567 goto err;1568 }1569 1570 ret = of_property_read_u32(np, "ti,sci-dev-id", &core->ti_sci_id);1571 if (ret) {1572 dev_err(dev, "missing 'ti,sci-dev-id' property\n");1573 goto err;1574 }1575 1576 core->reset = devm_reset_control_get_exclusive(dev, NULL);1577 if (IS_ERR_OR_NULL(core->reset)) {1578 ret = PTR_ERR_OR_ZERO(core->reset);1579 if (!ret)1580 ret = -ENODEV;1581 if (ret != -EPROBE_DEFER) {1582 dev_err(dev, "failed to get reset handle, ret = %d\n",1583 ret);1584 }1585 goto err;1586 }1587 1588 core->tsp = ti_sci_proc_of_get_tsp(dev, core->ti_sci);1589 if (IS_ERR(core->tsp)) {1590 ret = PTR_ERR(core->tsp);1591 dev_err(dev, "failed to construct ti-sci proc control, ret = %d\n",1592 ret);1593 goto err;1594 }1595 1596 ret = k3_r5_core_of_get_internal_memories(pdev, core);1597 if (ret) {1598 dev_err(dev, "failed to get internal memories, ret = %d\n",1599 ret);1600 goto err;1601 }1602 1603 ret = k3_r5_core_of_get_sram_memories(pdev, core);1604 if (ret) {1605 dev_err(dev, "failed to get sram memories, ret = %d\n", ret);1606 goto err;1607 }1608 1609 ret = ti_sci_proc_request(core->tsp);1610 if (ret < 0) {1611 dev_err(dev, "ti_sci_proc_request failed, ret = %d\n", ret);1612 goto err;1613 }1614 1615 platform_set_drvdata(pdev, core);1616 devres_close_group(dev, k3_r5_core_of_init);1617 1618 return 0;1619 1620err:1621 devres_release_group(dev, k3_r5_core_of_init);1622 return ret;1623}1624 1625/*1626 * free the resources explicitly since driver model is not being used1627 * for the child R5F devices1628 */1629static void k3_r5_core_of_exit(struct platform_device *pdev)1630{1631 struct k3_r5_core *core = platform_get_drvdata(pdev);1632 struct device *dev = &pdev->dev;1633 int ret;1634 1635 ret = ti_sci_proc_release(core->tsp);1636 if (ret)1637 dev_err(dev, "failed to release proc, ret = %d\n", ret);1638 1639 platform_set_drvdata(pdev, NULL);1640 devres_release_group(dev, k3_r5_core_of_init);1641}1642 1643static void k3_r5_cluster_of_exit(void *data)1644{1645 struct k3_r5_cluster *cluster = platform_get_drvdata(data);1646 struct platform_device *cpdev;1647 struct k3_r5_core *core, *temp;1648 1649 list_for_each_entry_safe_reverse(core, temp, &cluster->cores, elem) {1650 list_del(&core->elem);1651 cpdev = to_platform_device(core->dev);1652 k3_r5_core_of_exit(cpdev);1653 }1654}1655 1656static int k3_r5_cluster_of_init(struct platform_device *pdev)1657{1658 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);1659 struct device *dev = &pdev->dev;1660 struct device_node *np = dev_of_node(dev);1661 struct platform_device *cpdev;1662 struct device_node *child;1663 struct k3_r5_core *core;1664 int ret;1665 1666 for_each_available_child_of_node(np, child) {1667 cpdev = of_find_device_by_node(child);1668 if (!cpdev) {1669 ret = -ENODEV;1670 dev_err(dev, "could not get R5 core platform device\n");1671 of_node_put(child);1672 goto fail;1673 }1674 1675 ret = k3_r5_core_of_init(cpdev);1676 if (ret) {1677 dev_err(dev, "k3_r5_core_of_init failed, ret = %d\n",1678 ret);1679 put_device(&cpdev->dev);1680 of_node_put(child);1681 goto fail;1682 }1683 1684 core = platform_get_drvdata(cpdev);1685 put_device(&cpdev->dev);1686 list_add_tail(&core->elem, &cluster->cores);1687 }1688 1689 return 0;1690 1691fail:1692 k3_r5_cluster_of_exit(pdev);1693 return ret;1694}1695 1696static int k3_r5_probe(struct platform_device *pdev)1697{1698 struct device *dev = &pdev->dev;1699 struct device_node *np = dev_of_node(dev);1700 struct k3_r5_cluster *cluster;1701 const struct k3_r5_soc_data *data;1702 int ret;1703 int num_cores;1704 1705 data = of_device_get_match_data(&pdev->dev);1706 if (!data) {1707 dev_err(dev, "SoC-specific data is not defined\n");1708 return -ENODEV;1709 }1710 1711 cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL);1712 if (!cluster)1713 return -ENOMEM;1714 1715 cluster->dev = dev;1716 cluster->soc_data = data;1717 INIT_LIST_HEAD(&cluster->cores);1718 init_waitqueue_head(&cluster->core_transition);1719 1720 ret = of_property_read_u32(np, "ti,cluster-mode", &cluster->mode);1721 if (ret < 0 && ret != -EINVAL) {1722 dev_err(dev, "invalid format for ti,cluster-mode, ret = %d\n",1723 ret);1724 return ret;1725 }1726 1727 if (ret == -EINVAL) {1728 /*1729 * default to most common efuse configurations - Split-mode on AM64x1730 * and LockStep-mode on all others1731 * default to most common efuse configurations -1732 * Split-mode on AM64x1733 * Single core on AM62x1734 * LockStep-mode on all others1735 */1736 if (!data->is_single_core)1737 cluster->mode = data->single_cpu_mode ?1738 CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP;1739 else1740 cluster->mode = CLUSTER_MODE_SINGLECORE;1741 }1742 1743 if ((cluster->mode == CLUSTER_MODE_SINGLECPU && !data->single_cpu_mode) ||1744 (cluster->mode == CLUSTER_MODE_SINGLECORE && !data->is_single_core)) {1745 dev_err(dev, "Cluster mode = %d is not supported on this SoC\n", cluster->mode);1746 return -EINVAL;1747 }1748 1749 num_cores = of_get_available_child_count(np);1750 if (num_cores != 2 && !data->is_single_core) {1751 dev_err(dev, "MCU cluster requires both R5F cores to be enabled but num_cores is set to = %d\n",1752 num_cores);1753 return -ENODEV;1754 }1755 1756 if (num_cores != 1 && data->is_single_core) {1757 dev_err(dev, "SoC supports only single core R5 but num_cores is set to %d\n",1758 num_cores);1759 return -ENODEV;1760 }1761 1762 platform_set_drvdata(pdev, cluster);1763 1764 ret = devm_of_platform_populate(dev);1765 if (ret) {1766 dev_err(dev, "devm_of_platform_populate failed, ret = %d\n",1767 ret);1768 return ret;1769 }1770 1771 ret = k3_r5_cluster_of_init(pdev);1772 if (ret) {1773 dev_err(dev, "k3_r5_cluster_of_init failed, ret = %d\n", ret);1774 return ret;1775 }1776 1777 ret = devm_add_action_or_reset(dev, k3_r5_cluster_of_exit, pdev);1778 if (ret)1779 return ret;1780 1781 ret = k3_r5_cluster_rproc_init(pdev);1782 if (ret) {1783 dev_err(dev, "k3_r5_cluster_rproc_init failed, ret = %d\n",1784 ret);1785 return ret;1786 }1787 1788 ret = devm_add_action_or_reset(dev, k3_r5_cluster_rproc_exit, pdev);1789 if (ret)1790 return ret;1791 1792 return 0;1793}1794 1795static const struct k3_r5_soc_data am65_j721e_soc_data = {1796 .tcm_is_double = false,1797 .tcm_ecc_autoinit = false,1798 .single_cpu_mode = false,1799 .is_single_core = false,1800};1801 1802static const struct k3_r5_soc_data j7200_j721s2_soc_data = {1803 .tcm_is_double = true,1804 .tcm_ecc_autoinit = true,1805 .single_cpu_mode = false,1806 .is_single_core = false,1807};1808 1809static const struct k3_r5_soc_data am64_soc_data = {1810 .tcm_is_double = true,1811 .tcm_ecc_autoinit = true,1812 .single_cpu_mode = true,1813 .is_single_core = false,1814};1815 1816static const struct k3_r5_soc_data am62_soc_data = {1817 .tcm_is_double = false,1818 .tcm_ecc_autoinit = true,1819 .single_cpu_mode = false,1820 .is_single_core = true,1821};1822 1823static const struct of_device_id k3_r5_of_match[] = {1824 { .compatible = "ti,am654-r5fss", .data = &am65_j721e_soc_data, },1825 { .compatible = "ti,j721e-r5fss", .data = &am65_j721e_soc_data, },1826 { .compatible = "ti,j7200-r5fss", .data = &j7200_j721s2_soc_data, },1827 { .compatible = "ti,am64-r5fss", .data = &am64_soc_data, },1828 { .compatible = "ti,am62-r5fss", .data = &am62_soc_data, },1829 { .compatible = "ti,j721s2-r5fss", .data = &j7200_j721s2_soc_data, },1830 { /* sentinel */ },1831};1832MODULE_DEVICE_TABLE(of, k3_r5_of_match);1833 1834static struct platform_driver k3_r5_rproc_driver = {1835 .probe = k3_r5_probe,1836 .driver = {1837 .name = "k3_r5_rproc",1838 .of_match_table = k3_r5_of_match,1839 },1840};1841 1842module_platform_driver(k3_r5_rproc_driver);1843 1844MODULE_LICENSE("GPL v2");1845MODULE_DESCRIPTION("TI K3 R5F remote processor driver");1846MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");1847