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1# SPDX-License-Identifier: GPL-2.0-only2config ARCH_HAS_RESET_CONTROLLER3 bool4 5menuconfig RESET_CONTROLLER6 bool "Reset Controller Support"7 default y if ARCH_HAS_RESET_CONTROLLER8 help9 Generic Reset Controller support.10 11 This framework is designed to abstract reset handling of devices12 via GPIOs or SoC-internal reset controller modules.13 14 If unsure, say no.15 16if RESET_CONTROLLER17 18config RESET_A10SR19 tristate "Altera Arria10 System Resource Reset"20 depends on MFD_ALTERA_A10SR || COMPILE_TEST21 help22 This option enables support for the external reset functions for23 peripheral PHYs on the Altera Arria10 System Resource Chip.24 25config RESET_ATH7926 bool "AR71xx Reset Driver" if COMPILE_TEST27 default ATH7928 help29 This enables the ATH79 reset controller driver that supports the30 AR71xx SoC reset controller.31 32config RESET_AXS10X33 bool "AXS10x Reset Driver" if COMPILE_TEST34 default ARC_PLAT_AXS10X35 help36 This enables the reset controller driver for AXS10x.37 38config RESET_BCM634539 bool "BCM6345 Reset Controller"40 depends on BMIPS_GENERIC || COMPILE_TEST41 default BMIPS_GENERIC42 help43 This enables the reset controller driver for BCM6345 SoCs.44 45config RESET_BERLIN46 tristate "Berlin Reset Driver"47 depends on ARCH_BERLIN || COMPILE_TEST48 default m if ARCH_BERLIN49 help50 This enables the reset controller driver for Marvell Berlin SoCs.51 52config RESET_BRCMSTB53 tristate "Broadcom STB reset controller"54 depends on ARCH_BRCMSTB || COMPILE_TEST55 default ARCH_BRCMSTB56 help57 This enables the reset controller driver for Broadcom STB SoCs using58 a SUN_TOP_CTRL_SW_INIT style controller.59 60config RESET_BRCMSTB_RESCAL61 tristate "Broadcom STB RESCAL reset controller"62 depends on HAS_IOMEM63 depends on ARCH_BRCMSTB || COMPILE_TEST64 default ARCH_BRCMSTB65 help66 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on67 BCM7216.68 69config RESET_EYEQ70 bool "Mobileye EyeQ reset controller"71 depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST72 select AUXILIARY_BUS73 default MACH_EYEQ5 || MACH_EYEQ6H74 help75 This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L76 and EyeQ6H SoCs.77 78 It has one or more domains, with a varying number of resets in each.79 Registers are located in a shared register region called OLB. EyeQ6H80 has multiple reset instances.81 82config RESET_GPIO83 tristate "GPIO reset controller"84 depends on GPIOLIB85 help86 This enables a generic reset controller for resets attached via87 GPIOs. Typically for OF platforms this driver expects "reset-gpios"88 property.89 90 If compiled as module, it will be called reset-gpio.91 92config RESET_HSDK93 bool "Synopsys HSDK Reset Driver"94 depends on HAS_IOMEM95 depends on ARC_SOC_HSDK || COMPILE_TEST96 help97 This enables the reset controller driver for HSDK board.98 99config RESET_IMX7100 tristate "i.MX7/8 Reset Driver"101 depends on HAS_IOMEM102 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST103 default y if SOC_IMX7D104 select MFD_SYSCON105 help106 This enables the reset controller driver for i.MX7 SoCs.107 108config RESET_IMX8MP_AUDIOMIX109 tristate "i.MX8MP AudioMix Reset Driver"110 depends on ARCH_MXC || COMPILE_TEST111 select AUXILIARY_BUS112 default CLK_IMX8MP113 help114 This enables the reset controller driver for i.MX8MP AudioMix115 116config RESET_INTEL_GW117 bool "Intel Reset Controller Driver"118 depends on X86 || COMPILE_TEST119 depends on OF && HAS_IOMEM120 select REGMAP_MMIO121 help122 This enables the reset controller driver for Intel Gateway SoCs.123 Say Y to control the reset signals provided by reset controller.124 Otherwise, say N.125 126config RESET_K210127 bool "Reset controller driver for Canaan Kendryte K210 SoC"128 depends on (SOC_CANAAN_K210 || COMPILE_TEST) && OF129 select MFD_SYSCON130 default SOC_CANAAN_K210131 help132 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.133 Say Y if you want to control reset signals provided by this134 controller.135 136config RESET_LANTIQ137 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST138 default SOC_TYPE_XWAY139 help140 This enables the reset controller driver for Lantiq / Intel XWAY SoCs.141 142config RESET_LPC18XX143 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST144 default ARCH_LPC18XX145 help146 This enables the reset controller driver for NXP LPC18xx/43xx SoCs.147 148config RESET_MCHP_SPARX5149 bool "Microchip Sparx5 reset driver"150 depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST151 default y if SPARX5_SWITCH152 select MFD_SYSCON153 help154 This driver supports switch core reset for the Microchip Sparx5 SoC.155 156config RESET_MESON157 tristate "Meson Reset Driver"158 depends on ARCH_MESON || COMPILE_TEST159 default ARCH_MESON160 help161 This enables the reset driver for Amlogic Meson SoCs.162 163config RESET_MESON_AUDIO_ARB164 tristate "Meson Audio Memory Arbiter Reset Driver"165 depends on ARCH_MESON || COMPILE_TEST166 help167 This enables the reset driver for Audio Memory Arbiter of168 Amlogic's A113 based SoCs169 170config RESET_NPCM171 bool "NPCM BMC Reset Driver" if COMPILE_TEST172 default ARCH_NPCM173 help174 This enables the reset controller driver for Nuvoton NPCM175 BMC SoCs.176 177config RESET_NUVOTON_MA35D1178 bool "Nuvoton MA35D1 Reset Driver"179 depends on ARCH_MA35 || COMPILE_TEST180 default ARCH_MA35181 help182 This enables the reset controller driver for Nuvoton MA35D1 SoC.183 184config RESET_PISTACHIO185 bool "Pistachio Reset Driver"186 depends on MIPS || COMPILE_TEST187 help188 This enables the reset driver for ImgTec Pistachio SoCs.189 190config RESET_POLARFIRE_SOC191 bool "Microchip PolarFire SoC (MPFS) Reset Driver"192 depends on MCHP_CLK_MPFS193 select AUXILIARY_BUS194 default MCHP_CLK_MPFS195 help196 This driver supports peripheral reset for the Microchip PolarFire SoC197 198config RESET_QCOM_AOSS199 tristate "Qcom AOSS Reset Driver"200 depends on ARCH_QCOM || COMPILE_TEST201 help202 This enables the AOSS (always on subsystem) reset driver203 for Qualcomm SDM845 SoCs. Say Y if you want to control204 reset signals provided by AOSS for Modem, Venus, ADSP,205 GPU, Camera, Wireless, Display subsystem. Otherwise, say N.206 207config RESET_QCOM_PDC208 tristate "Qualcomm PDC Reset Driver"209 depends on ARCH_QCOM || COMPILE_TEST210 help211 This enables the PDC (Power Domain Controller) reset driver212 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want213 to control reset signals provided by PDC for Modem, Compute,214 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.215 216config RESET_RASPBERRYPI217 tristate "Raspberry Pi 4 Firmware Reset Driver"218 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)219 default USB_XHCI_PCI220 help221 Raspberry Pi 4's co-processor controls some of the board's HW222 initialization process, but it's up to Linux to trigger it when223 relevant. This driver provides a reset controller capable of224 interfacing with RPi4's co-processor and model these firmware225 initialization routines as reset lines.226 227config RESET_RZG2L_USBPHY_CTRL228 tristate "Renesas RZ/G2L USBPHY control driver"229 depends on ARCH_RZG2L || COMPILE_TEST230 help231 Support for USBPHY Control found on RZ/G2L family. It mainly232 controls reset and power down of the USB/PHY.233 234config RESET_SCMI235 tristate "Reset driver controlled via ARM SCMI interface"236 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST237 default ARM_SCMI_PROTOCOL238 help239 This driver provides support for reset signal/domains that are240 controlled by firmware that implements the SCMI interface.241 242 This driver uses SCMI Message Protocol to interact with the243 firmware controlling all the reset signals.244 245config RESET_SIMPLE246 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT247 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_SOPHGO || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC248 depends on HAS_IOMEM249 help250 This enables a simple reset controller driver for reset lines that251 that can be asserted and deasserted by toggling bits in a contiguous,252 exclusive register space.253 254 Currently this driver supports:255 - Altera SoCFPGAs256 - ASPEED BMC SoCs257 - Bitmain BM1880 SoC258 - Realtek SoCs259 - RCC reset controller in STM32 MCUs260 - Allwinner SoCs261 - SiFive FU740 SoCs262 - Sophgo SoCs263 264config RESET_SOCFPGA265 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)266 default ARM && ARCH_INTEL_SOCFPGA267 select RESET_SIMPLE268 help269 This enables the reset driver for the SoCFPGA ARMv7 platforms. This270 driver gets initialized early during platform init calls.271 272config RESET_SUNPLUS273 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST274 default ARCH_SUNPLUS275 help276 This enables the reset driver support for Sunplus SoCs.277 The reset lines that can be asserted and deasserted by toggling bits278 in a contiguous, exclusive register space. The register is HIWORD_MASKED,279 which means each register holds 16 reset lines.280 281config RESET_SUNXI282 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI283 default ARCH_SUNXI284 select RESET_SIMPLE285 help286 This enables the reset driver for Allwinner SoCs.287 288config RESET_TI_SCI289 tristate "TI System Control Interface (TI-SCI) reset driver"290 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)291 help292 This enables the reset driver support over TI System Control Interface293 available on some new TI's SoCs. If you wish to use reset resources294 managed by the TI System Controller, say Y here. Otherwise, say N.295 296config RESET_TI_SYSCON297 tristate "TI SYSCON Reset Driver"298 depends on HAS_IOMEM299 select MFD_SYSCON300 help301 This enables the reset driver support for TI devices with302 memory-mapped reset registers as part of a syscon device node. If303 you wish to use the reset framework for such memory-mapped devices,304 say Y here. Otherwise, say N.305 306config RESET_TI_TPS380X307 tristate "TI TPS380x Reset Driver"308 select GPIOLIB309 help310 This enables the reset driver support for TI TPS380x devices. If311 you wish to use the reset framework for such devices, say Y here.312 Otherwise, say N.313 314config RESET_TN48M_CPLD315 tristate "Delta Networks TN48M switch CPLD reset controller"316 depends on MFD_TN48M_CPLD || COMPILE_TEST317 default MFD_TN48M_CPLD318 help319 This enables the reset controller driver for the Delta TN48M CPLD.320 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X321 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and322 Microchip PD69200 PoE PSE controller.323 324 This driver can also be built as a module. If so, the module will be325 called reset-tn48m.326 327config RESET_UNIPHIER328 tristate "Reset controller driver for UniPhier SoCs"329 depends on ARCH_UNIPHIER || COMPILE_TEST330 depends on OF && MFD_SYSCON331 default ARCH_UNIPHIER332 help333 Support for reset controllers on UniPhier SoCs.334 Say Y if you want to control reset signals provided by System Control335 block, Media I/O block, Peripheral Block.336 337config RESET_UNIPHIER_GLUE338 tristate "Reset driver in glue layer for UniPhier SoCs"339 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF340 default ARCH_UNIPHIER341 select RESET_SIMPLE342 help343 Support for peripheral core reset included in its own glue layer344 on UniPhier SoCs. Say Y if you want to control reset signals345 provided by the glue layer.346 347config RESET_ZYNQ348 bool "ZYNQ Reset Driver" if COMPILE_TEST349 default ARCH_ZYNQ350 help351 This enables the reset controller driver for Xilinx Zynq SoCs.352 353config RESET_ZYNQMP354 bool "ZYNQMP Reset Driver" if COMPILE_TEST355 default ARCH_ZYNQMP356 help357 This enables the reset controller driver for Xilinx ZynqMP SoCs.358 359source "drivers/reset/starfive/Kconfig"360source "drivers/reset/sti/Kconfig"361source "drivers/reset/hisilicon/Kconfig"362source "drivers/reset/tegra/Kconfig"363 364endif365