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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * PolarFire SoC (MPFS) Peripheral Clock Reset Controller4 *5 * Author: Conor Dooley <conor.dooley@microchip.com>6 * Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.7 *8 */9#include <linux/auxiliary_bus.h>10#include <linux/delay.h>11#include <linux/io.h>12#include <linux/module.h>13#include <linux/of.h>14#include <linux/platform_device.h>15#include <linux/slab.h>16#include <linux/reset-controller.h>17#include <dt-bindings/clock/microchip,mpfs-clock.h>18#include <soc/microchip/mpfs.h>19 20/*21 * The ENVM reset is the lowest bit in the register & I am using the CLK_FOO22 * defines in the dt to make things easier to configure - so this is accounting23 * for the offset of 3 there.24 */25#define MPFS_PERIPH_OFFSET CLK_ENVM26#define MPFS_NUM_RESETS 30u27#define MPFS_SLEEP_MIN_US 10028#define MPFS_SLEEP_MAX_US 20029 30/* block concurrent access to the soft reset register */31static DEFINE_SPINLOCK(mpfs_reset_lock);32 33struct mpfs_reset {34 void __iomem *base;35 struct reset_controller_dev rcdev;36};37 38static inline struct mpfs_reset *to_mpfs_reset(struct reset_controller_dev *rcdev)39{40 return container_of(rcdev, struct mpfs_reset, rcdev);41}42 43/*44 * Peripheral clock resets45 */46static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)47{48 struct mpfs_reset *rst = to_mpfs_reset(rcdev);49 unsigned long flags;50 u32 reg;51 52 spin_lock_irqsave(&mpfs_reset_lock, flags);53 54 reg = readl(rst->base);55 reg |= BIT(id);56 writel(reg, rst->base);57 58 spin_unlock_irqrestore(&mpfs_reset_lock, flags);59 60 return 0;61}62 63static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)64{65 struct mpfs_reset *rst = to_mpfs_reset(rcdev);66 unsigned long flags;67 u32 reg;68 69 spin_lock_irqsave(&mpfs_reset_lock, flags);70 71 reg = readl(rst->base);72 reg &= ~BIT(id);73 writel(reg, rst->base);74 75 spin_unlock_irqrestore(&mpfs_reset_lock, flags);76 77 return 0;78}79 80static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)81{82 struct mpfs_reset *rst = to_mpfs_reset(rcdev);83 u32 reg = readl(rst->base);84 85 /*86 * It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit87 * is never hit.88 */89 return (reg & BIT(id));90}91 92static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id)93{94 mpfs_assert(rcdev, id);95 96 usleep_range(MPFS_SLEEP_MIN_US, MPFS_SLEEP_MAX_US);97 98 mpfs_deassert(rcdev, id);99 100 return 0;101}102 103static const struct reset_control_ops mpfs_reset_ops = {104 .reset = mpfs_reset,105 .assert = mpfs_assert,106 .deassert = mpfs_deassert,107 .status = mpfs_status,108};109 110static int mpfs_reset_xlate(struct reset_controller_dev *rcdev,111 const struct of_phandle_args *reset_spec)112{113 unsigned int index = reset_spec->args[0];114 115 /*116 * CLK_RESERVED does not map to a clock, but it does map to a reset,117 * so it has to be accounted for here. It is the reset for the fabric,118 * so if this reset gets called - do not reset it.119 */120 if (index == CLK_RESERVED) {121 dev_err(rcdev->dev, "Resetting the fabric is not supported\n");122 return -EINVAL;123 }124 125 if (index < MPFS_PERIPH_OFFSET || index >= (MPFS_PERIPH_OFFSET + rcdev->nr_resets)) {126 dev_err(rcdev->dev, "Invalid reset index %u\n", index);127 return -EINVAL;128 }129 130 return index - MPFS_PERIPH_OFFSET;131}132 133static int mpfs_reset_probe(struct auxiliary_device *adev,134 const struct auxiliary_device_id *id)135{136 struct device *dev = &adev->dev;137 struct reset_controller_dev *rcdev;138 struct mpfs_reset *rst;139 140 rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);141 if (!rst)142 return -ENOMEM;143 144 rst->base = (void __iomem *)adev->dev.platform_data;145 146 rcdev = &rst->rcdev;147 rcdev->dev = dev;148 rcdev->dev->parent = dev->parent;149 rcdev->ops = &mpfs_reset_ops;150 rcdev->of_node = dev->parent->of_node;151 rcdev->of_reset_n_cells = 1;152 rcdev->of_xlate = mpfs_reset_xlate;153 rcdev->nr_resets = MPFS_NUM_RESETS;154 155 return devm_reset_controller_register(dev, rcdev);156}157 158static void mpfs_reset_unregister_adev(void *_adev)159{160 struct auxiliary_device *adev = _adev;161 162 auxiliary_device_delete(adev);163 auxiliary_device_uninit(adev);164}165 166static void mpfs_reset_adev_release(struct device *dev)167{168 struct auxiliary_device *adev = to_auxiliary_dev(dev);169 170 kfree(adev);171}172 173static struct auxiliary_device *mpfs_reset_adev_alloc(struct device *clk_dev)174{175 struct auxiliary_device *adev;176 int ret;177 178 adev = kzalloc(sizeof(*adev), GFP_KERNEL);179 if (!adev)180 return ERR_PTR(-ENOMEM);181 182 adev->name = "reset-mpfs";183 adev->dev.parent = clk_dev;184 adev->dev.release = mpfs_reset_adev_release;185 adev->id = 666u;186 187 ret = auxiliary_device_init(adev);188 if (ret) {189 kfree(adev);190 return ERR_PTR(ret);191 }192 193 return adev;194}195 196int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base)197{198 struct auxiliary_device *adev;199 int ret;200 201 adev = mpfs_reset_adev_alloc(clk_dev);202 if (IS_ERR(adev))203 return PTR_ERR(adev);204 205 ret = auxiliary_device_add(adev);206 if (ret) {207 auxiliary_device_uninit(adev);208 return ret;209 }210 211 adev->dev.platform_data = (__force void *)base;212 213 return devm_add_action_or_reset(clk_dev, mpfs_reset_unregister_adev, adev);214}215EXPORT_SYMBOL_NS_GPL(mpfs_reset_controller_register, MCHP_CLK_MPFS);216 217static const struct auxiliary_device_id mpfs_reset_ids[] = {218 {219 .name = "reset_mpfs.reset-mpfs",220 },221 { }222};223MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids);224 225static struct auxiliary_driver mpfs_reset_driver = {226 .probe = mpfs_reset_probe,227 .id_table = mpfs_reset_ids,228};229 230module_auxiliary_driver(mpfs_reset_driver);231 232MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");233MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");234MODULE_IMPORT_NS(MCHP_CLK_MPFS);235