405 lines · c
1// SPDX-License-Identifier: GPL-2.0+2//3// Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.4 5#include <linux/io.h>6#include <linux/rtc.h>7#include <linux/module.h>8#include <linux/slab.h>9#include <linux/interrupt.h>10#include <linux/platform_device.h>11#include <linux/pm_wakeirq.h>12#include <linux/clk.h>13#include <linux/of.h>14 15#define RTC_INPUT_CLK_32768HZ (0x00 << 5)16#define RTC_INPUT_CLK_32000HZ (0x01 << 5)17#define RTC_INPUT_CLK_38400HZ (0x02 << 5)18 19#define RTC_SW_BIT (1 << 0)20#define RTC_ALM_BIT (1 << 2)21#define RTC_1HZ_BIT (1 << 4)22#define RTC_2HZ_BIT (1 << 7)23#define RTC_SAM0_BIT (1 << 8)24#define RTC_SAM1_BIT (1 << 9)25#define RTC_SAM2_BIT (1 << 10)26#define RTC_SAM3_BIT (1 << 11)27#define RTC_SAM4_BIT (1 << 12)28#define RTC_SAM5_BIT (1 << 13)29#define RTC_SAM6_BIT (1 << 14)30#define RTC_SAM7_BIT (1 << 15)31#define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \32 RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \33 RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)34 35#define RTC_ENABLE_BIT (1 << 7)36 37#define MAX_PIE_NUM 938#define MAX_PIE_FREQ 51239 40#define MXC_RTC_TIME 041#define MXC_RTC_ALARM 142 43#define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */44#define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */45#define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */46#define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */47#define RTC_RTCCTL 0x10 /* 32bit rtc control reg */48#define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */49#define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */50#define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */51#define RTC_DAYR 0x20 /* 32bit rtc days counter reg */52#define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */53#define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */54#define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */55#define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */56 57enum imx_rtc_type {58 IMX1_RTC,59 IMX21_RTC,60};61 62struct rtc_plat_data {63 struct rtc_device *rtc;64 void __iomem *ioaddr;65 int irq;66 struct clk *clk_ref;67 struct clk *clk_ipg;68 struct rtc_time g_rtc_alarm;69 enum imx_rtc_type devtype;70};71 72static const struct of_device_id imx_rtc_dt_ids[] = {73 { .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },74 { .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },75 {}76};77MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);78 79static inline int is_imx1_rtc(struct rtc_plat_data *data)80{81 return data->devtype == IMX1_RTC;82}83 84/*85 * This function is used to obtain the RTC time or the alarm value in86 * second.87 */88static time64_t get_alarm_or_time(struct device *dev, int time_alarm)89{90 struct rtc_plat_data *pdata = dev_get_drvdata(dev);91 void __iomem *ioaddr = pdata->ioaddr;92 u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;93 94 switch (time_alarm) {95 case MXC_RTC_TIME:96 day = readw(ioaddr + RTC_DAYR);97 hr_min = readw(ioaddr + RTC_HOURMIN);98 sec = readw(ioaddr + RTC_SECOND);99 break;100 case MXC_RTC_ALARM:101 day = readw(ioaddr + RTC_DAYALARM);102 hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;103 sec = readw(ioaddr + RTC_ALRM_SEC);104 break;105 }106 107 hr = hr_min >> 8;108 min = hr_min & 0xff;109 110 return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;111}112 113/*114 * This function sets the RTC alarm value or the time value.115 */116static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)117{118 u32 tod, day, hr, min, sec, temp;119 struct rtc_plat_data *pdata = dev_get_drvdata(dev);120 void __iomem *ioaddr = pdata->ioaddr;121 122 day = div_s64_rem(time, 86400, &tod);123 124 /* time is within a day now */125 hr = tod / 3600;126 tod -= hr * 3600;127 128 /* time is within an hour now */129 min = tod / 60;130 sec = tod - min * 60;131 132 temp = (hr << 8) + min;133 134 switch (time_alarm) {135 case MXC_RTC_TIME:136 writew(day, ioaddr + RTC_DAYR);137 writew(sec, ioaddr + RTC_SECOND);138 writew(temp, ioaddr + RTC_HOURMIN);139 break;140 case MXC_RTC_ALARM:141 writew(day, ioaddr + RTC_DAYALARM);142 writew(sec, ioaddr + RTC_ALRM_SEC);143 writew(temp, ioaddr + RTC_ALRM_HM);144 break;145 }146}147 148/*149 * This function updates the RTC alarm registers and then clears all the150 * interrupt status bits.151 */152static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)153{154 time64_t time;155 struct rtc_plat_data *pdata = dev_get_drvdata(dev);156 void __iomem *ioaddr = pdata->ioaddr;157 158 time = rtc_tm_to_time64(alrm);159 160 /* clear all the interrupt status bits */161 writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);162 set_alarm_or_time(dev, MXC_RTC_ALARM, time);163}164 165static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,166 unsigned int enabled)167{168 struct rtc_plat_data *pdata = dev_get_drvdata(dev);169 void __iomem *ioaddr = pdata->ioaddr;170 u32 reg;171 unsigned long flags;172 173 spin_lock_irqsave(&pdata->rtc->irq_lock, flags);174 reg = readw(ioaddr + RTC_RTCIENR);175 176 if (enabled)177 reg |= bit;178 else179 reg &= ~bit;180 181 writew(reg, ioaddr + RTC_RTCIENR);182 spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);183}184 185/* This function is the RTC interrupt service routine. */186static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)187{188 struct platform_device *pdev = dev_id;189 struct rtc_plat_data *pdata = platform_get_drvdata(pdev);190 void __iomem *ioaddr = pdata->ioaddr;191 u32 status;192 u32 events = 0;193 194 spin_lock(&pdata->rtc->irq_lock);195 status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);196 /* clear interrupt sources */197 writew(status, ioaddr + RTC_RTCISR);198 199 /* update irq data & counter */200 if (status & RTC_ALM_BIT) {201 events |= (RTC_AF | RTC_IRQF);202 /* RTC alarm should be one-shot */203 mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);204 }205 206 if (status & PIT_ALL_ON)207 events |= (RTC_PF | RTC_IRQF);208 209 rtc_update_irq(pdata->rtc, 1, events);210 spin_unlock(&pdata->rtc->irq_lock);211 212 return IRQ_HANDLED;213}214 215static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)216{217 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);218 return 0;219}220 221/*222 * This function reads the current RTC time into tm in Gregorian date.223 */224static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)225{226 time64_t val;227 228 /* Avoid roll-over from reading the different registers */229 do {230 val = get_alarm_or_time(dev, MXC_RTC_TIME);231 } while (val != get_alarm_or_time(dev, MXC_RTC_TIME));232 233 rtc_time64_to_tm(val, tm);234 235 return 0;236}237 238/*239 * This function sets the internal RTC time based on tm in Gregorian date.240 */241static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)242{243 time64_t time = rtc_tm_to_time64(tm);244 245 /* Avoid roll-over from reading the different registers */246 do {247 set_alarm_or_time(dev, MXC_RTC_TIME, time);248 } while (time != get_alarm_or_time(dev, MXC_RTC_TIME));249 250 return 0;251}252 253/*254 * This function reads the current alarm value into the passed in 'alrm'255 * argument. It updates the alrm's pending field value based on the whether256 * an alarm interrupt occurs or not.257 */258static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)259{260 struct rtc_plat_data *pdata = dev_get_drvdata(dev);261 void __iomem *ioaddr = pdata->ioaddr;262 263 rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);264 alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;265 266 return 0;267}268 269/*270 * This function sets the RTC alarm based on passed in alrm.271 */272static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)273{274 struct rtc_plat_data *pdata = dev_get_drvdata(dev);275 276 rtc_update_alarm(dev, &alrm->time);277 278 memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));279 mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);280 281 return 0;282}283 284/* RTC layer */285static const struct rtc_class_ops mxc_rtc_ops = {286 .read_time = mxc_rtc_read_time,287 .set_time = mxc_rtc_set_time,288 .read_alarm = mxc_rtc_read_alarm,289 .set_alarm = mxc_rtc_set_alarm,290 .alarm_irq_enable = mxc_rtc_alarm_irq_enable,291};292 293static int mxc_rtc_probe(struct platform_device *pdev)294{295 struct rtc_device *rtc;296 struct rtc_plat_data *pdata = NULL;297 u32 reg;298 unsigned long rate;299 int ret;300 301 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);302 if (!pdata)303 return -ENOMEM;304 305 pdata->devtype = (uintptr_t)of_device_get_match_data(&pdev->dev);306 307 pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);308 if (IS_ERR(pdata->ioaddr))309 return PTR_ERR(pdata->ioaddr);310 311 rtc = devm_rtc_allocate_device(&pdev->dev);312 if (IS_ERR(rtc))313 return PTR_ERR(rtc);314 315 pdata->rtc = rtc;316 rtc->ops = &mxc_rtc_ops;317 if (is_imx1_rtc(pdata)) {318 struct rtc_time tm;319 320 /* 9bit days + hours minutes seconds */321 rtc->range_max = (1 << 9) * 86400 - 1;322 323 /*324 * Set the start date as beginning of the current year. This can325 * be overridden using device tree.326 */327 rtc_time64_to_tm(ktime_get_real_seconds(), &tm);328 rtc->start_secs = mktime64(tm.tm_year, 1, 1, 0, 0, 0);329 rtc->set_start_time = true;330 } else {331 /* 16bit days + hours minutes seconds */332 rtc->range_max = (1 << 16) * 86400ULL - 1;333 }334 335 pdata->clk_ipg = devm_clk_get_enabled(&pdev->dev, "ipg");336 if (IS_ERR(pdata->clk_ipg)) {337 dev_err(&pdev->dev, "unable to get ipg clock!\n");338 return PTR_ERR(pdata->clk_ipg);339 }340 341 pdata->clk_ref = devm_clk_get_enabled(&pdev->dev, "ref");342 if (IS_ERR(pdata->clk_ref)) {343 dev_err(&pdev->dev, "unable to get ref clock!\n");344 return PTR_ERR(pdata->clk_ref);345 }346 347 rate = clk_get_rate(pdata->clk_ref);348 349 if (rate == 32768)350 reg = RTC_INPUT_CLK_32768HZ;351 else if (rate == 32000)352 reg = RTC_INPUT_CLK_32000HZ;353 else if (rate == 38400)354 reg = RTC_INPUT_CLK_38400HZ;355 else {356 dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);357 return -EINVAL;358 }359 360 reg |= RTC_ENABLE_BIT;361 writew(reg, (pdata->ioaddr + RTC_RTCCTL));362 if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {363 dev_err(&pdev->dev, "hardware module can't be enabled!\n");364 return -EIO;365 }366 367 platform_set_drvdata(pdev, pdata);368 369 /* Configure and enable the RTC */370 pdata->irq = platform_get_irq(pdev, 0);371 372 if (pdata->irq >= 0 &&373 devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,374 IRQF_SHARED, pdev->name, pdev) < 0) {375 dev_warn(&pdev->dev, "interrupt not available.\n");376 pdata->irq = -1;377 }378 379 if (pdata->irq >= 0) {380 device_init_wakeup(&pdev->dev, 1);381 ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);382 if (ret)383 dev_err(&pdev->dev, "failed to enable irq wake\n");384 }385 386 ret = devm_rtc_register_device(rtc);387 388 return ret;389}390 391static struct platform_driver mxc_rtc_driver = {392 .driver = {393 .name = "mxc_rtc",394 .of_match_table = imx_rtc_dt_ids,395 },396 .probe = mxc_rtc_probe,397};398 399module_platform_driver(mxc_rtc_driver)400 401MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");402MODULE_DESCRIPTION("RTC driver for Freescale MXC");403MODULE_LICENSE("GPL");404 405