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1// SPDX-License-Identifier: GPL-2.02/*3 * Texas Instruments K3 RTC driver4 *5 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/6 */7 8#include <linux/clk.h>9#include <linux/delay.h>10#include <linux/mod_devicetable.h>11#include <linux/module.h>12#include <linux/of.h>13#include <linux/platform_device.h>14#include <linux/sys_soc.h>15#include <linux/property.h>16#include <linux/regmap.h>17#include <linux/rtc.h>18 19/* Registers */20#define REG_K3RTC_S_CNT_LSW 0x0821#define REG_K3RTC_S_CNT_MSW 0x0c22#define REG_K3RTC_COMP 0x1023#define REG_K3RTC_ON_OFF_S_CNT_LSW 0x2024#define REG_K3RTC_ON_OFF_S_CNT_MSW 0x2425#define REG_K3RTC_SCRATCH0 0x3026#define REG_K3RTC_SCRATCH7 0x4c27#define REG_K3RTC_GENERAL_CTL 0x5028#define REG_K3RTC_IRQSTATUS_RAW_SYS 0x5429#define REG_K3RTC_IRQSTATUS_SYS 0x5830#define REG_K3RTC_IRQENABLE_SET_SYS 0x5c31#define REG_K3RTC_IRQENABLE_CLR_SYS 0x6032#define REG_K3RTC_SYNCPEND 0x6833#define REG_K3RTC_KICK0 0x7034#define REG_K3RTC_KICK1 0x7435 36/* Freeze when lsw is read and unfreeze when msw is read */37#define K3RTC_CNT_FMODE_S_CNT_VALUE (0x2 << 24)38 39/* Magic values for lock/unlock */40#define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b1341#define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e042 43/* Multiplier for ppb conversions */44#define K3RTC_PPB_MULT (1000000000LL)45/* Min and max values supported with 'offset' interface (swapped sign) */46#define K3RTC_MIN_OFFSET (-277761)47#define K3RTC_MAX_OFFSET (277778)48 49static const struct regmap_config ti_k3_rtc_regmap_config = {50 .name = "peripheral-registers",51 .reg_bits = 32,52 .val_bits = 32,53 .reg_stride = 4,54 .max_register = REG_K3RTC_KICK1,55};56 57enum ti_k3_rtc_fields {58 K3RTC_KICK0,59 K3RTC_KICK1,60 K3RTC_S_CNT_LSW,61 K3RTC_S_CNT_MSW,62 K3RTC_O32K_OSC_DEP_EN,63 K3RTC_UNLOCK,64 K3RTC_CNT_FMODE,65 K3RTC_PEND,66 K3RTC_RELOAD_FROM_BBD,67 K3RTC_COMP,68 69 K3RTC_ALM_S_CNT_LSW,70 K3RTC_ALM_S_CNT_MSW,71 K3RTC_IRQ_STATUS_RAW,72 K3RTC_IRQ_STATUS,73 K3RTC_IRQ_ENABLE_SET,74 K3RTC_IRQ_ENABLE_CLR,75 76 K3RTC_IRQ_STATUS_ALT,77 K3RTC_IRQ_ENABLE_CLR_ALT,78 79 K3_RTC_MAX_FIELDS80};81 82static const struct reg_field ti_rtc_reg_fields[] = {83 [K3RTC_KICK0] = REG_FIELD(REG_K3RTC_KICK0, 0, 31),84 [K3RTC_KICK1] = REG_FIELD(REG_K3RTC_KICK1, 0, 31),85 [K3RTC_S_CNT_LSW] = REG_FIELD(REG_K3RTC_S_CNT_LSW, 0, 31),86 [K3RTC_S_CNT_MSW] = REG_FIELD(REG_K3RTC_S_CNT_MSW, 0, 15),87 [K3RTC_O32K_OSC_DEP_EN] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 21, 21),88 [K3RTC_UNLOCK] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 23, 23),89 [K3RTC_CNT_FMODE] = REG_FIELD(REG_K3RTC_GENERAL_CTL, 24, 25),90 [K3RTC_PEND] = REG_FIELD(REG_K3RTC_SYNCPEND, 0, 1),91 [K3RTC_RELOAD_FROM_BBD] = REG_FIELD(REG_K3RTC_SYNCPEND, 31, 31),92 [K3RTC_COMP] = REG_FIELD(REG_K3RTC_COMP, 0, 31),93 94 /* We use on to off as alarm trigger */95 [K3RTC_ALM_S_CNT_LSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_LSW, 0, 31),96 [K3RTC_ALM_S_CNT_MSW] = REG_FIELD(REG_K3RTC_ON_OFF_S_CNT_MSW, 0, 15),97 [K3RTC_IRQ_STATUS_RAW] = REG_FIELD(REG_K3RTC_IRQSTATUS_RAW_SYS, 0, 0),98 [K3RTC_IRQ_STATUS] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 0, 0),99 [K3RTC_IRQ_ENABLE_SET] = REG_FIELD(REG_K3RTC_IRQENABLE_SET_SYS, 0, 0),100 [K3RTC_IRQ_ENABLE_CLR] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 0, 0),101 /* Off to on is alternate */102 [K3RTC_IRQ_STATUS_ALT] = REG_FIELD(REG_K3RTC_IRQSTATUS_SYS, 1, 1),103 [K3RTC_IRQ_ENABLE_CLR_ALT] = REG_FIELD(REG_K3RTC_IRQENABLE_CLR_SYS, 1, 1),104};105 106/**107 * struct ti_k3_rtc - Private data for ti-k3-rtc108 * @irq: IRQ109 * @sync_timeout_us: data sync timeout period in uSec110 * @rate_32k: 32k clock rate in Hz111 * @rtc_dev: rtc device112 * @regmap: rtc mmio regmap113 * @r_fields: rtc register fields114 */115struct ti_k3_rtc {116 unsigned int irq;117 u32 sync_timeout_us;118 unsigned long rate_32k;119 struct rtc_device *rtc_dev;120 struct regmap *regmap;121 struct regmap_field *r_fields[K3_RTC_MAX_FIELDS];122};123 124static int k3rtc_field_read(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f)125{126 int ret;127 int val;128 129 ret = regmap_field_read(priv->r_fields[f], &val);130 /*131 * We shouldn't be seeing regmap fail on us for mmio reads132 * This is possible if clock context fails, but that isn't the case for us133 */134 if (WARN_ON_ONCE(ret))135 return ret;136 return val;137}138 139static void k3rtc_field_write(struct ti_k3_rtc *priv, enum ti_k3_rtc_fields f, u32 val)140{141 regmap_field_write(priv->r_fields[f], val);142}143 144/**145 * k3rtc_fence - Ensure a register sync took place between the two domains146 * @priv: pointer to priv data147 *148 * Return: 0 if the sync took place, else returns -ETIMEDOUT149 */150static int k3rtc_fence(struct ti_k3_rtc *priv)151{152 int ret;153 154 ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_PEND], ret,155 !ret, 2, priv->sync_timeout_us);156 157 return ret;158}159 160static inline int k3rtc_check_unlocked(struct ti_k3_rtc *priv)161{162 int ret;163 164 ret = k3rtc_field_read(priv, K3RTC_UNLOCK);165 if (ret < 0)166 return ret;167 168 return (ret) ? 0 : 1;169}170 171static int k3rtc_unlock_rtc(struct ti_k3_rtc *priv)172{173 int ret;174 175 ret = k3rtc_check_unlocked(priv);176 if (!ret)177 return ret;178 179 k3rtc_field_write(priv, K3RTC_KICK0, K3RTC_KICK0_UNLOCK_VALUE);180 k3rtc_field_write(priv, K3RTC_KICK1, K3RTC_KICK1_UNLOCK_VALUE);181 182 /* Skip fence since we are going to check the unlock bit as fence */183 ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_UNLOCK], ret,184 ret, 2, priv->sync_timeout_us);185 186 return ret;187}188 189/*190 * This is the list of SoCs affected by TI's i2327 errata causing the RTC191 * state-machine to break if not unlocked fast enough during boot. These192 * SoCs must have the bootloader unlock this device very early in the193 * boot-flow before we (Linux) can use this device.194 */195static const struct soc_device_attribute has_erratum_i2327[] = {196 { .family = "AM62X", .revision = "SR1.0" },197 { /* sentinel */ }198};199 200static int k3rtc_configure(struct device *dev)201{202 int ret;203 struct ti_k3_rtc *priv = dev_get_drvdata(dev);204 205 /*206 * HWBUG: The compare state machine is broken if the RTC module207 * is NOT unlocked in under one second of boot - which is pretty long208 * time from the perspective of Linux driver (module load, u-boot209 * shell all can take much longer than this.210 *211 * In such occurrence, it is assumed that the RTC module is unusable212 */213 if (soc_device_match(has_erratum_i2327)) {214 ret = k3rtc_check_unlocked(priv);215 /* If there is an error OR if we are locked, return error */216 if (ret) {217 dev_err(dev,218 HW_ERR "Erratum i2327 unlock QUIRK! Cannot operate!!\n");219 return -EFAULT;220 }221 } else {222 /* May need to explicitly unlock first time */223 ret = k3rtc_unlock_rtc(priv);224 if (ret) {225 dev_err(dev, "Failed to unlock(%d)!\n", ret);226 return ret;227 }228 }229 230 /* Enable Shadow register sync on 32k clock boundary */231 k3rtc_field_write(priv, K3RTC_O32K_OSC_DEP_EN, 0x1);232 233 /*234 * Wait at least clock sync time before proceeding further programming.235 * This ensures that the 32k based sync is active.236 */237 usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 5);238 239 /* We need to ensure fence here to make sure sync here */240 ret = k3rtc_fence(priv);241 if (ret) {242 dev_err(dev,243 "Failed fence osc_dep enable(%d) - is 32k clk working?!\n", ret);244 return ret;245 }246 247 /*248 * FMODE setting: Reading lower seconds will freeze value on higher249 * seconds. This also implies that we must *ALWAYS* read lower seconds250 * prior to reading higher seconds251 */252 k3rtc_field_write(priv, K3RTC_CNT_FMODE, K3RTC_CNT_FMODE_S_CNT_VALUE);253 254 /* Clear any spurious IRQ sources if any */255 k3rtc_field_write(priv, K3RTC_IRQ_STATUS_ALT, 0x1);256 k3rtc_field_write(priv, K3RTC_IRQ_STATUS, 0x1);257 /* Disable all IRQs */258 k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR_ALT, 0x1);259 k3rtc_field_write(priv, K3RTC_IRQ_ENABLE_CLR, 0x1);260 261 /* And.. Let us Sync the writes in */262 return k3rtc_fence(priv);263}264 265static int ti_k3_rtc_read_time(struct device *dev, struct rtc_time *tm)266{267 struct ti_k3_rtc *priv = dev_get_drvdata(dev);268 u32 seconds_lo, seconds_hi;269 270 seconds_lo = k3rtc_field_read(priv, K3RTC_S_CNT_LSW);271 seconds_hi = k3rtc_field_read(priv, K3RTC_S_CNT_MSW);272 273 rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, tm);274 275 return 0;276}277 278static int ti_k3_rtc_set_time(struct device *dev, struct rtc_time *tm)279{280 struct ti_k3_rtc *priv = dev_get_drvdata(dev);281 time64_t seconds;282 283 seconds = rtc_tm_to_time64(tm);284 285 /*286 * Read operation on LSW will freeze the RTC, so to update287 * the time, we cannot use field operations. Just write since the288 * reserved bits are ignored.289 */290 regmap_write(priv->regmap, REG_K3RTC_S_CNT_LSW, seconds);291 regmap_write(priv->regmap, REG_K3RTC_S_CNT_MSW, seconds >> 32);292 293 return k3rtc_fence(priv);294}295 296static int ti_k3_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)297{298 struct ti_k3_rtc *priv = dev_get_drvdata(dev);299 u32 reg;300 u32 offset = enabled ? K3RTC_IRQ_ENABLE_SET : K3RTC_IRQ_ENABLE_CLR;301 302 reg = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET);303 if ((enabled && reg) || (!enabled && !reg))304 return 0;305 306 k3rtc_field_write(priv, offset, 0x1);307 308 /*309 * Ensure the write sync is through - NOTE: it should be OK to have310 * ISR to fire as we are checking sync (which should be done in a 32k311 * cycle or so).312 */313 return k3rtc_fence(priv);314}315 316static int ti_k3_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)317{318 struct ti_k3_rtc *priv = dev_get_drvdata(dev);319 u32 seconds_lo, seconds_hi;320 321 seconds_lo = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_LSW);322 seconds_hi = k3rtc_field_read(priv, K3RTC_ALM_S_CNT_MSW);323 324 rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, &alarm->time);325 326 alarm->enabled = k3rtc_field_read(priv, K3RTC_IRQ_ENABLE_SET);327 328 return 0;329}330 331static int ti_k3_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)332{333 struct ti_k3_rtc *priv = dev_get_drvdata(dev);334 time64_t seconds;335 int ret;336 337 seconds = rtc_tm_to_time64(&alarm->time);338 339 k3rtc_field_write(priv, K3RTC_ALM_S_CNT_LSW, seconds);340 k3rtc_field_write(priv, K3RTC_ALM_S_CNT_MSW, (seconds >> 32));341 342 /* Make sure the alarm time is synced in */343 ret = k3rtc_fence(priv);344 if (ret) {345 dev_err(dev, "Failed to fence(%d)! Potential config issue?\n", ret);346 return ret;347 }348 349 /* Alarm IRQ enable will do a sync */350 return ti_k3_rtc_alarm_irq_enable(dev, alarm->enabled);351}352 353static int ti_k3_rtc_read_offset(struct device *dev, long *offset)354{355 struct ti_k3_rtc *priv = dev_get_drvdata(dev);356 u32 ticks_per_hr = priv->rate_32k * 3600;357 int comp;358 s64 tmp;359 360 comp = k3rtc_field_read(priv, K3RTC_COMP);361 362 /* Convert from RTC calibration register format to ppb format */363 tmp = comp * (s64)K3RTC_PPB_MULT;364 if (tmp < 0)365 tmp -= ticks_per_hr / 2LL;366 else367 tmp += ticks_per_hr / 2LL;368 tmp = div_s64(tmp, ticks_per_hr);369 370 /* Offset value operates in negative way, so swap sign */371 *offset = (long)-tmp;372 373 return 0;374}375 376static int ti_k3_rtc_set_offset(struct device *dev, long offset)377{378 struct ti_k3_rtc *priv = dev_get_drvdata(dev);379 u32 ticks_per_hr = priv->rate_32k * 3600;380 int comp;381 s64 tmp;382 383 /* Make sure offset value is within supported range */384 if (offset < K3RTC_MIN_OFFSET || offset > K3RTC_MAX_OFFSET)385 return -ERANGE;386 387 /* Convert from ppb format to RTC calibration register format */388 tmp = offset * (s64)ticks_per_hr;389 if (tmp < 0)390 tmp -= K3RTC_PPB_MULT / 2LL;391 else392 tmp += K3RTC_PPB_MULT / 2LL;393 tmp = div_s64(tmp, K3RTC_PPB_MULT);394 395 /* Offset value operates in negative way, so swap sign */396 comp = (int)-tmp;397 398 k3rtc_field_write(priv, K3RTC_COMP, comp);399 400 return k3rtc_fence(priv);401}402 403static irqreturn_t ti_k3_rtc_interrupt(s32 irq, void *dev_id)404{405 struct device *dev = dev_id;406 struct ti_k3_rtc *priv = dev_get_drvdata(dev);407 u32 reg;408 int ret;409 410 /*411 * IRQ assertion can be very fast, however, the IRQ Status clear412 * de-assert depends on 32k clock edge in the 32k domain413 * If we clear the status prior to the first 32k clock edge,414 * the status bit is cleared, but the IRQ stays re-asserted.415 *416 * To prevent this condition, we need to wait for clock sync time.417 * We can either do that by polling the 32k observability signal for418 * a toggle OR we could just sleep and let the processor do other419 * stuff.420 */421 usleep_range(priv->sync_timeout_us, priv->sync_timeout_us + 2);422 423 /* Lets make sure that this is a valid interrupt */424 reg = k3rtc_field_read(priv, K3RTC_IRQ_STATUS);425 426 if (!reg) {427 u32 raw = k3rtc_field_read(priv, K3RTC_IRQ_STATUS_RAW);428 429 dev_err(dev,430 HW_ERR431 "Erratum i2327/IRQ trig: status: 0x%08x / 0x%08x\n", reg, raw);432 return IRQ_NONE;433 }434 435 /*436 * Write 1 to clear status reg437 * We cannot use a field operation here due to a potential race between438 * 32k domain and vbus domain.439 */440 regmap_write(priv->regmap, REG_K3RTC_IRQSTATUS_SYS, 0x1);441 442 /* Sync the write in */443 ret = k3rtc_fence(priv);444 if (ret) {445 dev_err(dev, "Failed to fence irq status clr(%d)!\n", ret);446 return IRQ_NONE;447 }448 449 /*450 * Force the 32k status to be reloaded back in to ensure status is451 * reflected back correctly.452 */453 k3rtc_field_write(priv, K3RTC_RELOAD_FROM_BBD, 0x1);454 455 /* Ensure the write sync is through */456 ret = k3rtc_fence(priv);457 if (ret) {458 dev_err(dev, "Failed to fence reload from bbd(%d)!\n", ret);459 return IRQ_NONE;460 }461 462 /* Now we ensure that the status bit is cleared */463 ret = regmap_field_read_poll_timeout(priv->r_fields[K3RTC_IRQ_STATUS],464 ret, !ret, 2, priv->sync_timeout_us);465 if (ret) {466 dev_err(dev, "Time out waiting for status clear\n");467 return IRQ_NONE;468 }469 470 /* Notify RTC core on event */471 rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF);472 473 return IRQ_HANDLED;474}475 476static const struct rtc_class_ops ti_k3_rtc_ops = {477 .read_time = ti_k3_rtc_read_time,478 .set_time = ti_k3_rtc_set_time,479 .read_alarm = ti_k3_rtc_read_alarm,480 .set_alarm = ti_k3_rtc_set_alarm,481 .read_offset = ti_k3_rtc_read_offset,482 .set_offset = ti_k3_rtc_set_offset,483 .alarm_irq_enable = ti_k3_rtc_alarm_irq_enable,484};485 486static int ti_k3_rtc_scratch_read(void *priv_data, unsigned int offset,487 void *val, size_t bytes)488{489 struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data;490 491 return regmap_bulk_read(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4);492}493 494static int ti_k3_rtc_scratch_write(void *priv_data, unsigned int offset,495 void *val, size_t bytes)496{497 struct ti_k3_rtc *priv = (struct ti_k3_rtc *)priv_data;498 int ret;499 500 ret = regmap_bulk_write(priv->regmap, REG_K3RTC_SCRATCH0 + offset, val, bytes / 4);501 if (ret)502 return ret;503 504 return k3rtc_fence(priv);505}506 507static struct nvmem_config ti_k3_rtc_nvmem_config = {508 .name = "ti_k3_rtc_scratch",509 .word_size = 4,510 .stride = 4,511 .size = REG_K3RTC_SCRATCH7 - REG_K3RTC_SCRATCH0 + 4,512 .reg_read = ti_k3_rtc_scratch_read,513 .reg_write = ti_k3_rtc_scratch_write,514};515 516static int k3rtc_get_32kclk(struct device *dev, struct ti_k3_rtc *priv)517{518 struct clk *clk;519 520 clk = devm_clk_get_enabled(dev, "osc32k");521 if (IS_ERR(clk))522 return PTR_ERR(clk);523 524 priv->rate_32k = clk_get_rate(clk);525 526 /* Make sure we are exact 32k clock. Else, try to compensate delay */527 if (priv->rate_32k != 32768)528 dev_warn(dev, "Clock rate %ld is not 32768! Could misbehave!\n",529 priv->rate_32k);530 531 /*532 * Sync timeout should be two 32k clk sync cycles = ~61uS. We double533 * it to comprehend intermediate bus segment and cpu frequency534 * deltas535 */536 priv->sync_timeout_us = (u32)(DIV_ROUND_UP_ULL(1000000, priv->rate_32k) * 4);537 538 return 0;539}540 541static int k3rtc_get_vbusclk(struct device *dev, struct ti_k3_rtc *priv)542{543 struct clk *clk;544 545 /* Note: VBUS isn't a context clock, it is needed for hardware operation */546 clk = devm_clk_get_enabled(dev, "vbus");547 if (IS_ERR(clk))548 return PTR_ERR(clk);549 550 return 0;551}552 553static int ti_k3_rtc_probe(struct platform_device *pdev)554{555 struct device *dev = &pdev->dev;556 struct ti_k3_rtc *priv;557 void __iomem *rtc_base;558 int ret;559 560 priv = devm_kzalloc(dev, sizeof(struct ti_k3_rtc), GFP_KERNEL);561 if (!priv)562 return -ENOMEM;563 564 rtc_base = devm_platform_ioremap_resource(pdev, 0);565 if (IS_ERR(rtc_base))566 return PTR_ERR(rtc_base);567 568 priv->regmap = devm_regmap_init_mmio(dev, rtc_base, &ti_k3_rtc_regmap_config);569 if (IS_ERR(priv->regmap))570 return PTR_ERR(priv->regmap);571 572 ret = devm_regmap_field_bulk_alloc(dev, priv->regmap, priv->r_fields,573 ti_rtc_reg_fields, K3_RTC_MAX_FIELDS);574 if (ret)575 return ret;576 577 ret = k3rtc_get_32kclk(dev, priv);578 if (ret)579 return ret;580 ret = k3rtc_get_vbusclk(dev, priv);581 if (ret)582 return ret;583 584 ret = platform_get_irq(pdev, 0);585 if (ret < 0)586 return ret;587 priv->irq = (unsigned int)ret;588 589 priv->rtc_dev = devm_rtc_allocate_device(dev);590 if (IS_ERR(priv->rtc_dev))591 return PTR_ERR(priv->rtc_dev);592 593 priv->rtc_dev->ops = &ti_k3_rtc_ops;594 priv->rtc_dev->range_max = (1ULL << 48) - 1; /* 48Bit seconds */595 ti_k3_rtc_nvmem_config.priv = priv;596 597 ret = devm_request_threaded_irq(dev, priv->irq, NULL,598 ti_k3_rtc_interrupt,599 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,600 dev_name(dev), dev);601 if (ret) {602 dev_err(dev, "Could not request IRQ: %d\n", ret);603 return ret;604 }605 606 platform_set_drvdata(pdev, priv);607 608 ret = k3rtc_configure(dev);609 if (ret)610 return ret;611 612 if (device_property_present(dev, "wakeup-source"))613 device_init_wakeup(dev, true);614 else615 device_set_wakeup_capable(dev, true);616 617 ret = devm_rtc_register_device(priv->rtc_dev);618 if (ret)619 return ret;620 621 return devm_rtc_nvmem_register(priv->rtc_dev, &ti_k3_rtc_nvmem_config);622}623 624static const struct of_device_id ti_k3_rtc_of_match_table[] = {625 {.compatible = "ti,am62-rtc" },626 {}627};628MODULE_DEVICE_TABLE(of, ti_k3_rtc_of_match_table);629 630static int __maybe_unused ti_k3_rtc_suspend(struct device *dev)631{632 struct ti_k3_rtc *priv = dev_get_drvdata(dev);633 634 if (device_may_wakeup(dev))635 return enable_irq_wake(priv->irq);636 637 return 0;638}639 640static int __maybe_unused ti_k3_rtc_resume(struct device *dev)641{642 struct ti_k3_rtc *priv = dev_get_drvdata(dev);643 644 if (device_may_wakeup(dev))645 disable_irq_wake(priv->irq);646 return 0;647}648 649static SIMPLE_DEV_PM_OPS(ti_k3_rtc_pm_ops, ti_k3_rtc_suspend, ti_k3_rtc_resume);650 651static struct platform_driver ti_k3_rtc_driver = {652 .probe = ti_k3_rtc_probe,653 .driver = {654 .name = "rtc-ti-k3",655 .of_match_table = ti_k3_rtc_of_match_table,656 .pm = &ti_k3_rtc_pm_ops,657 },658};659module_platform_driver(ti_k3_rtc_driver);660 661MODULE_LICENSE("GPL");662MODULE_DESCRIPTION("TI K3 RTC driver");663MODULE_AUTHOR("Nishanth Menon");664