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1// SPDX-License-Identifier: GPL-2.02/*3 * RTC driver for tps6594 PMIC4 *5 * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/6 */7 8#include <linux/bcd.h>9#include <linux/errno.h>10#include <linux/init.h>11#include <linux/interrupt.h>12#include <linux/kernel.h>13#include <linux/limits.h>14#include <linux/math64.h>15#include <linux/module.h>16#include <linux/platform_device.h>17#include <linux/mod_devicetable.h>18#include <linux/property.h>19#include <linux/rtc.h>20#include <linux/types.h>21#include <linux/units.h>22 23#include <linux/mfd/tps6594.h>24 25// Total number of RTC registers needed to set time26#define NUM_TIME_REGS (TPS6594_REG_RTC_WEEKS - TPS6594_REG_RTC_SECONDS + 1)27 28// Total number of RTC alarm registers29#define NUM_TIME_ALARM_REGS (NUM_TIME_REGS - 1)30 31/*32 * Min and max values supported by 'offset' interface (swapped sign).33 * After conversion, the values do not exceed the range [-32767, 33767]34 * which COMP_REG must conform to.35 */36#define MIN_OFFSET (-277774)37#define MAX_OFFSET (277774)38 39// Number of ticks per hour40#define TICKS_PER_HOUR (32768 * 3600)41 42// Multiplier for ppb conversions43#define PPB_MULT NANO44 45struct tps6594_rtc {46 struct rtc_device *rtc_dev;47 int irq;48};49 50static int tps6594_rtc_alarm_irq_enable(struct device *dev,51 unsigned int enabled)52{53 struct tps6594 *tps = dev_get_drvdata(dev->parent);54 u8 val;55 56 val = enabled ? TPS6594_BIT_IT_ALARM : 0;57 58 return regmap_update_bits(tps->regmap, TPS6594_REG_RTC_INTERRUPTS,59 TPS6594_BIT_IT_ALARM, val);60}61 62/* Pulse GET_TIME field of RTC_CTRL_1 to store a timestamp in shadow registers. */63static int tps6594_rtc_shadow_timestamp(struct device *dev, struct tps6594 *tps)64{65 int ret;66 67 /*68 * Set GET_TIME to 0. Next time we set GET_TIME to 1 we will be sure to store69 * an up-to-date timestamp.70 */71 ret = regmap_clear_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,72 TPS6594_BIT_GET_TIME);73 if (ret < 0)74 return ret;75 76 /*77 * Copy content of RTC registers to shadow registers or latches to read78 * a coherent timestamp.79 */80 return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,81 TPS6594_BIT_GET_TIME);82}83 84static int tps6594_rtc_read_time(struct device *dev, struct rtc_time *tm)85{86 unsigned char rtc_data[NUM_TIME_REGS];87 struct tps6594 *tps = dev_get_drvdata(dev->parent);88 int ret;89 90 // Check if RTC is running.91 ret = regmap_test_bits(tps->regmap, TPS6594_REG_RTC_STATUS,92 TPS6594_BIT_RUN);93 if (ret < 0)94 return ret;95 if (ret == 0)96 return -EINVAL;97 98 ret = tps6594_rtc_shadow_timestamp(dev, tps);99 if (ret < 0)100 return ret;101 102 // Read shadowed RTC registers.103 ret = regmap_bulk_read(tps->regmap, TPS6594_REG_RTC_SECONDS, rtc_data,104 NUM_TIME_REGS);105 if (ret < 0)106 return ret;107 108 tm->tm_sec = bcd2bin(rtc_data[0]);109 tm->tm_min = bcd2bin(rtc_data[1]);110 tm->tm_hour = bcd2bin(rtc_data[2]);111 tm->tm_mday = bcd2bin(rtc_data[3]);112 tm->tm_mon = bcd2bin(rtc_data[4]) - 1;113 tm->tm_year = bcd2bin(rtc_data[5]) + 100;114 tm->tm_wday = bcd2bin(rtc_data[6]);115 116 return 0;117}118 119static int tps6594_rtc_set_time(struct device *dev, struct rtc_time *tm)120{121 unsigned char rtc_data[NUM_TIME_REGS];122 struct tps6594 *tps = dev_get_drvdata(dev->parent);123 int ret;124 125 rtc_data[0] = bin2bcd(tm->tm_sec);126 rtc_data[1] = bin2bcd(tm->tm_min);127 rtc_data[2] = bin2bcd(tm->tm_hour);128 rtc_data[3] = bin2bcd(tm->tm_mday);129 rtc_data[4] = bin2bcd(tm->tm_mon + 1);130 rtc_data[5] = bin2bcd(tm->tm_year - 100);131 rtc_data[6] = bin2bcd(tm->tm_wday);132 133 // Stop RTC while updating the RTC time registers.134 ret = regmap_clear_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,135 TPS6594_BIT_STOP_RTC);136 if (ret < 0)137 return ret;138 139 // Update all the time registers in one shot.140 ret = regmap_bulk_write(tps->regmap, TPS6594_REG_RTC_SECONDS, rtc_data,141 NUM_TIME_REGS);142 if (ret < 0)143 return ret;144 145 // Start back RTC.146 return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,147 TPS6594_BIT_STOP_RTC);148}149 150static int tps6594_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)151{152 unsigned char alarm_data[NUM_TIME_ALARM_REGS];153 u32 int_val;154 struct tps6594 *tps = dev_get_drvdata(dev->parent);155 int ret;156 157 ret = regmap_bulk_read(tps->regmap, TPS6594_REG_ALARM_SECONDS,158 alarm_data, NUM_TIME_ALARM_REGS);159 if (ret < 0)160 return ret;161 162 alm->time.tm_sec = bcd2bin(alarm_data[0]);163 alm->time.tm_min = bcd2bin(alarm_data[1]);164 alm->time.tm_hour = bcd2bin(alarm_data[2]);165 alm->time.tm_mday = bcd2bin(alarm_data[3]);166 alm->time.tm_mon = bcd2bin(alarm_data[4]) - 1;167 alm->time.tm_year = bcd2bin(alarm_data[5]) + 100;168 169 ret = regmap_read(tps->regmap, TPS6594_REG_RTC_INTERRUPTS, &int_val);170 if (ret < 0)171 return ret;172 173 alm->enabled = int_val & TPS6594_BIT_IT_ALARM;174 175 return 0;176}177 178static int tps6594_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)179{180 unsigned char alarm_data[NUM_TIME_ALARM_REGS];181 struct tps6594 *tps = dev_get_drvdata(dev->parent);182 int ret;183 184 // Disable alarm irq before changing the alarm timestamp.185 ret = tps6594_rtc_alarm_irq_enable(dev, 0);186 if (ret)187 return ret;188 189 alarm_data[0] = bin2bcd(alm->time.tm_sec);190 alarm_data[1] = bin2bcd(alm->time.tm_min);191 alarm_data[2] = bin2bcd(alm->time.tm_hour);192 alarm_data[3] = bin2bcd(alm->time.tm_mday);193 alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);194 alarm_data[5] = bin2bcd(alm->time.tm_year - 100);195 196 // Update all the alarm registers in one shot.197 ret = regmap_bulk_write(tps->regmap, TPS6594_REG_ALARM_SECONDS,198 alarm_data, NUM_TIME_ALARM_REGS);199 if (ret < 0)200 return ret;201 202 if (alm->enabled)203 ret = tps6594_rtc_alarm_irq_enable(dev, 1);204 205 return ret;206}207 208static int tps6594_rtc_set_calibration(struct device *dev, int calibration)209{210 struct tps6594 *tps = dev_get_drvdata(dev->parent);211 __le16 value;212 int ret;213 214 /*215 * TPS6594 uses two's complement 16 bit value for compensation of RTC216 * crystal inaccuracies. One time every hour when seconds counter217 * increments from 0 to 1 compensation value will be added to internal218 * RTC counter value.219 *220 * Valid range for compensation value: [-32767 .. 32767].221 */222 if (calibration < S16_MIN + 1 || calibration > S16_MAX)223 return -ERANGE;224 225 value = cpu_to_le16(calibration);226 227 // Update all the compensation registers in one shot.228 ret = regmap_bulk_write(tps->regmap, TPS6594_REG_RTC_COMP_LSB, &value,229 sizeof(value));230 if (ret < 0)231 return ret;232 233 // Enable automatic compensation.234 return regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,235 TPS6594_BIT_AUTO_COMP);236}237 238static int tps6594_rtc_get_calibration(struct device *dev, int *calibration)239{240 struct tps6594 *tps = dev_get_drvdata(dev->parent);241 unsigned int ctrl;242 __le16 value;243 int ret;244 245 ret = regmap_read(tps->regmap, TPS6594_REG_RTC_CTRL_1, &ctrl);246 if (ret < 0)247 return ret;248 249 // If automatic compensation is not enabled report back zero.250 if (!(ctrl & TPS6594_BIT_AUTO_COMP)) {251 *calibration = 0;252 return 0;253 }254 255 ret = regmap_bulk_read(tps->regmap, TPS6594_REG_RTC_COMP_LSB, &value,256 sizeof(value));257 if (ret < 0)258 return ret;259 260 *calibration = le16_to_cpu(value);261 262 return 0;263}264 265static int tps6594_rtc_read_offset(struct device *dev, long *offset)266{267 int calibration;268 s64 tmp;269 int ret;270 271 ret = tps6594_rtc_get_calibration(dev, &calibration);272 if (ret < 0)273 return ret;274 275 // Convert from RTC calibration register format to ppb format.276 tmp = calibration * PPB_MULT;277 278 if (tmp < 0)279 tmp -= TICKS_PER_HOUR / 2LL;280 else281 tmp += TICKS_PER_HOUR / 2LL;282 tmp = div_s64(tmp, TICKS_PER_HOUR);283 284 /*285 * SAFETY:286 * Computatiion is the reverse operation of the one done in287 * `tps6594_rtc_set_offset`. The safety remarks applie here too.288 */289 290 /*291 * Offset value operates in negative way, so swap sign.292 * See 8.3.10.5, (32768 - COMP_REG).293 */294 *offset = (long)-tmp;295 296 return 0;297}298 299static int tps6594_rtc_set_offset(struct device *dev, long offset)300{301 int calibration;302 s64 tmp;303 304 // Make sure offset value is within supported range.305 if (offset < MIN_OFFSET || offset > MAX_OFFSET)306 return -ERANGE;307 308 // Convert from ppb format to RTC calibration register format.309 310 tmp = offset * TICKS_PER_HOUR;311 if (tmp < 0)312 tmp -= PPB_MULT / 2LL;313 else314 tmp += PPB_MULT / 2LL;315 tmp = div_s64(tmp, PPB_MULT);316 317 /*318 * SAFETY:319 * - tmp = offset * TICK_PER_HOUR :320 * `offset` can't be more than 277774, so `tmp` can't exceed 277774000000000321 * which is lower than the maximum value in an `s64` (2^63-1). No overflow here.322 *323 * - tmp += TICK_PER_HOUR / 2LL :324 * tmp will have a maximum value of 277774117964800 which is still inferior to 2^63-1.325 */326 327 // Offset value operates in negative way, so swap sign.328 calibration = (int)-tmp;329 330 return tps6594_rtc_set_calibration(dev, calibration);331}332 333static irqreturn_t tps6594_rtc_interrupt(int irq, void *data)334{335 struct device *dev = data;336 struct tps6594 *tps = dev_get_drvdata(dev->parent);337 struct tps6594_rtc *rtc = dev_get_drvdata(dev);338 int ret;339 u32 rtc_reg;340 341 ret = regmap_read(tps->regmap, TPS6594_REG_RTC_STATUS, &rtc_reg);342 if (ret)343 return IRQ_NONE;344 345 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);346 347 return IRQ_HANDLED;348}349 350static const struct rtc_class_ops tps6594_rtc_ops = {351 .read_time = tps6594_rtc_read_time,352 .set_time = tps6594_rtc_set_time,353 .read_alarm = tps6594_rtc_read_alarm,354 .set_alarm = tps6594_rtc_set_alarm,355 .alarm_irq_enable = tps6594_rtc_alarm_irq_enable,356 .read_offset = tps6594_rtc_read_offset,357 .set_offset = tps6594_rtc_set_offset,358};359 360static int tps6594_rtc_probe(struct platform_device *pdev)361{362 struct tps6594 *tps = dev_get_drvdata(pdev->dev.parent);363 struct device *dev = &pdev->dev;364 struct tps6594_rtc *rtc;365 int irq;366 int ret;367 368 rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);369 if (!rtc)370 return -ENOMEM;371 372 rtc->rtc_dev = devm_rtc_allocate_device(dev);373 if (IS_ERR(rtc->rtc_dev))374 return PTR_ERR(rtc->rtc_dev);375 376 // Enable crystal oscillator.377 ret = regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_2,378 TPS6594_BIT_XTAL_EN);379 if (ret < 0)380 return ret;381 382 ret = regmap_test_bits(tps->regmap, TPS6594_REG_RTC_STATUS,383 TPS6594_BIT_RUN);384 if (ret < 0)385 return ret;386 // RTC not running.387 if (ret == 0) {388 ret = regmap_set_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,389 TPS6594_BIT_STOP_RTC);390 if (ret < 0)391 return ret;392 393 /*394 * On some boards, a 40 ms delay is needed before BIT_RUN is set.395 * 80 ms should provide sufficient margin.396 */397 mdelay(80);398 399 /*400 * RTC should be running now. Check if this is the case.401 * If not it might be a missing oscillator.402 */403 ret = regmap_test_bits(tps->regmap, TPS6594_REG_RTC_STATUS,404 TPS6594_BIT_RUN);405 if (ret < 0)406 return ret;407 if (ret == 0)408 return -ENODEV;409 410 // Stop RTC until first call to `tps6594_rtc_set_time`.411 ret = regmap_clear_bits(tps->regmap, TPS6594_REG_RTC_CTRL_1,412 TPS6594_BIT_STOP_RTC);413 if (ret < 0)414 return ret;415 }416 417 platform_set_drvdata(pdev, rtc);418 419 irq = platform_get_irq_byname(pdev, TPS6594_IRQ_NAME_ALARM);420 if (irq < 0)421 return dev_err_probe(dev, irq, "Failed to get irq\n");422 423 rtc->irq = irq;424 425 ret = devm_request_threaded_irq(dev, irq, NULL, tps6594_rtc_interrupt,426 IRQF_ONESHOT, TPS6594_IRQ_NAME_ALARM,427 dev);428 if (ret < 0)429 return dev_err_probe(dev, ret,430 "Failed to request_threaded_irq\n");431 432 ret = device_init_wakeup(dev, true);433 if (ret < 0)434 return dev_err_probe(dev, ret,435 "Failed to init rtc as wakeup source\n");436 437 rtc->rtc_dev->ops = &tps6594_rtc_ops;438 rtc->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;439 rtc->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;440 441 return devm_rtc_register_device(rtc->rtc_dev);442}443 444static int tps6594_rtc_resume(struct device *dev)445{446 struct tps6594 *tps = dev_get_drvdata(dev->parent);447 struct tps6594_rtc *rtc = dev_get_drvdata(dev);448 int ret;449 450 ret = regmap_test_bits(tps->regmap, TPS6594_REG_INT_STARTUP,451 TPS6594_BIT_RTC_INT);452 if (ret < 0) {453 dev_err(dev, "failed to read REG_INT_STARTUP: %d\n", ret);454 goto out;455 }456 457 if (ret > 0) {458 /*459 * If the alarm bit is set, it means that the IRQ has been460 * fired. But, the kernel may not have woke up yet when it461 * happened. So, we have to clear it.462 */463 ret = regmap_write(tps->regmap, TPS6594_REG_RTC_STATUS,464 TPS6594_BIT_ALARM);465 if (ret < 0)466 dev_err(dev, "error clearing alarm bit: %d", ret);467 468 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);469 }470out:471 disable_irq_wake(rtc->irq);472 473 return 0;474}475 476static int tps6594_rtc_suspend(struct device *dev)477{478 struct tps6594_rtc *rtc = dev_get_drvdata(dev);479 480 enable_irq_wake(rtc->irq);481 482 return 0;483}484 485static DEFINE_SIMPLE_DEV_PM_OPS(tps6594_rtc_pm_ops, tps6594_rtc_suspend, tps6594_rtc_resume);486 487static const struct platform_device_id tps6594_rtc_id_table[] = {488 { "tps6594-rtc", },489 {}490};491MODULE_DEVICE_TABLE(platform, tps6594_rtc_id_table);492 493static struct platform_driver tps6594_rtc_driver = {494 .probe = tps6594_rtc_probe,495 .driver = {496 .name = "tps6594-rtc",497 .pm = pm_sleep_ptr(&tps6594_rtc_pm_ops),498 },499 .id_table = tps6594_rtc_id_table,500};501 502module_platform_driver(tps6594_rtc_driver);503MODULE_AUTHOR("Esteban Blanc <eblanc@baylibre.com>");504MODULE_DESCRIPTION("TPS6594 RTC driver");505MODULE_LICENSE("GPL");506