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1/*2 * DO NOT EDIT - This file is automatically generated3 * from the following source files:4 *5 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $6 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $7 */8typedef int (ahd_reg_print_t)(u_int, u_int *, u_int);9typedef struct ahd_reg_parse_entry {10 char *name;11 uint8_t value;12 uint8_t mask;13} ahd_reg_parse_entry_t;14 15#if AIC_DEBUG_REGISTERS16ahd_reg_print_t ahd_intstat_print;17#else18#define ahd_intstat_print(regvalue, cur_col, wrap) \19 ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap)20#endif21 22#if AIC_DEBUG_REGISTERS23ahd_reg_print_t ahd_hs_mailbox_print;24#else25#define ahd_hs_mailbox_print(regvalue, cur_col, wrap) \26 ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap)27#endif28 29#if AIC_DEBUG_REGISTERS30ahd_reg_print_t ahd_seqintstat_print;31#else32#define ahd_seqintstat_print(regvalue, cur_col, wrap) \33 ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap)34#endif35 36#if AIC_DEBUG_REGISTERS37ahd_reg_print_t ahd_intctl_print;38#else39#define ahd_intctl_print(regvalue, cur_col, wrap) \40 ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap)41#endif42 43#if AIC_DEBUG_REGISTERS44ahd_reg_print_t ahd_dfcntrl_print;45#else46#define ahd_dfcntrl_print(regvalue, cur_col, wrap) \47 ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap)48#endif49 50#if AIC_DEBUG_REGISTERS51ahd_reg_print_t ahd_dfstatus_print;52#else53#define ahd_dfstatus_print(regvalue, cur_col, wrap) \54 ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap)55#endif56 57#if AIC_DEBUG_REGISTERS58ahd_reg_print_t ahd_sg_cache_shadow_print;59#else60#define ahd_sg_cache_shadow_print(regvalue, cur_col, wrap) \61 ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap)62#endif63 64#if AIC_DEBUG_REGISTERS65ahd_reg_print_t ahd_scsiseq0_print;66#else67#define ahd_scsiseq0_print(regvalue, cur_col, wrap) \68 ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap)69#endif70 71#if AIC_DEBUG_REGISTERS72ahd_reg_print_t ahd_scsiseq1_print;73#else74#define ahd_scsiseq1_print(regvalue, cur_col, wrap) \75 ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap)76#endif77 78#if AIC_DEBUG_REGISTERS79ahd_reg_print_t ahd_dffstat_print;80#else81#define ahd_dffstat_print(regvalue, cur_col, wrap) \82 ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap)83#endif84 85#if AIC_DEBUG_REGISTERS86ahd_reg_print_t ahd_scsisigi_print;87#else88#define ahd_scsisigi_print(regvalue, cur_col, wrap) \89 ahd_print_register(NULL, 0, "SCSISIGI", 0x41, regvalue, cur_col, wrap)90#endif91 92#if AIC_DEBUG_REGISTERS93ahd_reg_print_t ahd_scsiphase_print;94#else95#define ahd_scsiphase_print(regvalue, cur_col, wrap) \96 ahd_print_register(NULL, 0, "SCSIPHASE", 0x42, regvalue, cur_col, wrap)97#endif98 99#if AIC_DEBUG_REGISTERS100ahd_reg_print_t ahd_scsibus_print;101#else102#define ahd_scsibus_print(regvalue, cur_col, wrap) \103 ahd_print_register(NULL, 0, "SCSIBUS", 0x46, regvalue, cur_col, wrap)104#endif105 106#if AIC_DEBUG_REGISTERS107ahd_reg_print_t ahd_selid_print;108#else109#define ahd_selid_print(regvalue, cur_col, wrap) \110 ahd_print_register(NULL, 0, "SELID", 0x49, regvalue, cur_col, wrap)111#endif112 113#if AIC_DEBUG_REGISTERS114ahd_reg_print_t ahd_simode0_print;115#else116#define ahd_simode0_print(regvalue, cur_col, wrap) \117 ahd_print_register(NULL, 0, "SIMODE0", 0x4b, regvalue, cur_col, wrap)118#endif119 120#if AIC_DEBUG_REGISTERS121ahd_reg_print_t ahd_sstat0_print;122#else123#define ahd_sstat0_print(regvalue, cur_col, wrap) \124 ahd_print_register(NULL, 0, "SSTAT0", 0x4b, regvalue, cur_col, wrap)125#endif126 127#if AIC_DEBUG_REGISTERS128ahd_reg_print_t ahd_sstat1_print;129#else130#define ahd_sstat1_print(regvalue, cur_col, wrap) \131 ahd_print_register(NULL, 0, "SSTAT1", 0x4c, regvalue, cur_col, wrap)132#endif133 134#if AIC_DEBUG_REGISTERS135ahd_reg_print_t ahd_sstat2_print;136#else137#define ahd_sstat2_print(regvalue, cur_col, wrap) \138 ahd_print_register(NULL, 0, "SSTAT2", 0x4d, regvalue, cur_col, wrap)139#endif140 141#if AIC_DEBUG_REGISTERS142ahd_reg_print_t ahd_perrdiag_print;143#else144#define ahd_perrdiag_print(regvalue, cur_col, wrap) \145 ahd_print_register(NULL, 0, "PERRDIAG", 0x4e, regvalue, cur_col, wrap)146#endif147 148#if AIC_DEBUG_REGISTERS149ahd_reg_print_t ahd_soffcnt_print;150#else151#define ahd_soffcnt_print(regvalue, cur_col, wrap) \152 ahd_print_register(NULL, 0, "SOFFCNT", 0x4f, regvalue, cur_col, wrap)153#endif154 155#if AIC_DEBUG_REGISTERS156ahd_reg_print_t ahd_lqistat0_print;157#else158#define ahd_lqistat0_print(regvalue, cur_col, wrap) \159 ahd_print_register(NULL, 0, "LQISTAT0", 0x50, regvalue, cur_col, wrap)160#endif161 162#if AIC_DEBUG_REGISTERS163ahd_reg_print_t ahd_lqistat1_print;164#else165#define ahd_lqistat1_print(regvalue, cur_col, wrap) \166 ahd_print_register(NULL, 0, "LQISTAT1", 0x51, regvalue, cur_col, wrap)167#endif168 169#if AIC_DEBUG_REGISTERS170ahd_reg_print_t ahd_lqistat2_print;171#else172#define ahd_lqistat2_print(regvalue, cur_col, wrap) \173 ahd_print_register(NULL, 0, "LQISTAT2", 0x52, regvalue, cur_col, wrap)174#endif175 176#if AIC_DEBUG_REGISTERS177ahd_reg_print_t ahd_sstat3_print;178#else179#define ahd_sstat3_print(regvalue, cur_col, wrap) \180 ahd_print_register(NULL, 0, "SSTAT3", 0x53, regvalue, cur_col, wrap)181#endif182 183#if AIC_DEBUG_REGISTERS184ahd_reg_print_t ahd_lqostat0_print;185#else186#define ahd_lqostat0_print(regvalue, cur_col, wrap) \187 ahd_print_register(NULL, 0, "LQOSTAT0", 0x54, regvalue, cur_col, wrap)188#endif189 190#if AIC_DEBUG_REGISTERS191ahd_reg_print_t ahd_lqostat1_print;192#else193#define ahd_lqostat1_print(regvalue, cur_col, wrap) \194 ahd_print_register(NULL, 0, "LQOSTAT1", 0x55, regvalue, cur_col, wrap)195#endif196 197#if AIC_DEBUG_REGISTERS198ahd_reg_print_t ahd_lqostat2_print;199#else200#define ahd_lqostat2_print(regvalue, cur_col, wrap) \201 ahd_print_register(NULL, 0, "LQOSTAT2", 0x56, regvalue, cur_col, wrap)202#endif203 204#if AIC_DEBUG_REGISTERS205ahd_reg_print_t ahd_simode1_print;206#else207#define ahd_simode1_print(regvalue, cur_col, wrap) \208 ahd_print_register(NULL, 0, "SIMODE1", 0x57, regvalue, cur_col, wrap)209#endif210 211#if AIC_DEBUG_REGISTERS212ahd_reg_print_t ahd_dffsxfrctl_print;213#else214#define ahd_dffsxfrctl_print(regvalue, cur_col, wrap) \215 ahd_print_register(NULL, 0, "DFFSXFRCTL", 0x5a, regvalue, cur_col, wrap)216#endif217 218#if AIC_DEBUG_REGISTERS219ahd_reg_print_t ahd_seqintsrc_print;220#else221#define ahd_seqintsrc_print(regvalue, cur_col, wrap) \222 ahd_print_register(NULL, 0, "SEQINTSRC", 0x5b, regvalue, cur_col, wrap)223#endif224 225#if AIC_DEBUG_REGISTERS226ahd_reg_print_t ahd_seqimode_print;227#else228#define ahd_seqimode_print(regvalue, cur_col, wrap) \229 ahd_print_register(NULL, 0, "SEQIMODE", 0x5c, regvalue, cur_col, wrap)230#endif231 232#if AIC_DEBUG_REGISTERS233ahd_reg_print_t ahd_mdffstat_print;234#else235#define ahd_mdffstat_print(regvalue, cur_col, wrap) \236 ahd_print_register(NULL, 0, "MDFFSTAT", 0x5d, regvalue, cur_col, wrap)237#endif238 239#if AIC_DEBUG_REGISTERS240ahd_reg_print_t ahd_seloid_print;241#else242#define ahd_seloid_print(regvalue, cur_col, wrap) \243 ahd_print_register(NULL, 0, "SELOID", 0x6b, regvalue, cur_col, wrap)244#endif245 246#if AIC_DEBUG_REGISTERS247ahd_reg_print_t ahd_sg_state_print;248#else249#define ahd_sg_state_print(regvalue, cur_col, wrap) \250 ahd_print_register(NULL, 0, "SG_STATE", 0xa6, regvalue, cur_col, wrap)251#endif252 253#if AIC_DEBUG_REGISTERS254ahd_reg_print_t ahd_ccscbctl_print;255#else256#define ahd_ccscbctl_print(regvalue, cur_col, wrap) \257 ahd_print_register(NULL, 0, "CCSCBCTL", 0xad, regvalue, cur_col, wrap)258#endif259 260#if AIC_DEBUG_REGISTERS261ahd_reg_print_t ahd_ccsgctl_print;262#else263#define ahd_ccsgctl_print(regvalue, cur_col, wrap) \264 ahd_print_register(NULL, 0, "CCSGCTL", 0xad, regvalue, cur_col, wrap)265#endif266 267#if AIC_DEBUG_REGISTERS268ahd_reg_print_t ahd_seqctl0_print;269#else270#define ahd_seqctl0_print(regvalue, cur_col, wrap) \271 ahd_print_register(NULL, 0, "SEQCTL0", 0xd6, regvalue, cur_col, wrap)272#endif273 274#if AIC_DEBUG_REGISTERS275ahd_reg_print_t ahd_seqintctl_print;276#else277#define ahd_seqintctl_print(regvalue, cur_col, wrap) \278 ahd_print_register(NULL, 0, "SEQINTCTL", 0xd9, regvalue, cur_col, wrap)279#endif280 281#if AIC_DEBUG_REGISTERS282ahd_reg_print_t ahd_sram_base_print;283#else284#define ahd_sram_base_print(regvalue, cur_col, wrap) \285 ahd_print_register(NULL, 0, "SRAM_BASE", 0x100, regvalue, cur_col, wrap)286#endif287 288#if AIC_DEBUG_REGISTERS289ahd_reg_print_t ahd_qfreeze_count_print;290#else291#define ahd_qfreeze_count_print(regvalue, cur_col, wrap) \292 ahd_print_register(NULL, 0, "QFREEZE_COUNT", 0x132, regvalue, cur_col, wrap)293#endif294 295#if AIC_DEBUG_REGISTERS296ahd_reg_print_t ahd_kernel_qfreeze_count_print;297#else298#define ahd_kernel_qfreeze_count_print(regvalue, cur_col, wrap) \299 ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT", 0x134, regvalue, cur_col, wrap)300#endif301 302#if AIC_DEBUG_REGISTERS303ahd_reg_print_t ahd_saved_mode_print;304#else305#define ahd_saved_mode_print(regvalue, cur_col, wrap) \306 ahd_print_register(NULL, 0, "SAVED_MODE", 0x136, regvalue, cur_col, wrap)307#endif308 309#if AIC_DEBUG_REGISTERS310ahd_reg_print_t ahd_seq_flags_print;311#else312#define ahd_seq_flags_print(regvalue, cur_col, wrap) \313 ahd_print_register(NULL, 0, "SEQ_FLAGS", 0x139, regvalue, cur_col, wrap)314#endif315 316#if AIC_DEBUG_REGISTERS317ahd_reg_print_t ahd_lastphase_print;318#else319#define ahd_lastphase_print(regvalue, cur_col, wrap) \320 ahd_print_register(NULL, 0, "LASTPHASE", 0x13c, regvalue, cur_col, wrap)321#endif322 323#if AIC_DEBUG_REGISTERS324ahd_reg_print_t ahd_seq_flags2_print;325#else326#define ahd_seq_flags2_print(regvalue, cur_col, wrap) \327 ahd_print_register(NULL, 0, "SEQ_FLAGS2", 0x14d, regvalue, cur_col, wrap)328#endif329 330#if AIC_DEBUG_REGISTERS331ahd_reg_print_t ahd_mk_message_scb_print;332#else333#define ahd_mk_message_scb_print(regvalue, cur_col, wrap) \334 ahd_print_register(NULL, 0, "MK_MESSAGE_SCB", 0x160, regvalue, cur_col, wrap)335#endif336 337#if AIC_DEBUG_REGISTERS338ahd_reg_print_t ahd_mk_message_scsiid_print;339#else340#define ahd_mk_message_scsiid_print(regvalue, cur_col, wrap) \341 ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID", 0x162, regvalue, cur_col, wrap)342#endif343 344#if AIC_DEBUG_REGISTERS345ahd_reg_print_t ahd_scb_base_print;346#else347#define ahd_scb_base_print(regvalue, cur_col, wrap) \348 ahd_print_register(NULL, 0, "SCB_BASE", 0x180, regvalue, cur_col, wrap)349#endif350 351#if AIC_DEBUG_REGISTERS352ahd_reg_print_t ahd_scb_control_print;353#else354#define ahd_scb_control_print(regvalue, cur_col, wrap) \355 ahd_print_register(NULL, 0, "SCB_CONTROL", 0x192, regvalue, cur_col, wrap)356#endif357 358#if AIC_DEBUG_REGISTERS359ahd_reg_print_t ahd_scb_scsiid_print;360#else361#define ahd_scb_scsiid_print(regvalue, cur_col, wrap) \362 ahd_print_register(NULL, 0, "SCB_SCSIID", 0x193, regvalue, cur_col, wrap)363#endif364 365 366#define MODE_PTR 0x00367#define DST_MODE 0x70368#define SRC_MODE 0x07369 370#define INTSTAT 0x01371#define INT_PEND 0xff372#define HWERRINT 0x80373#define BRKADRINT 0x40374#define SWTMINT 0x20375#define PCIINT 0x10376#define SCSIINT 0x08377#define SEQINT 0x04378#define CMDCMPLT 0x02379#define SPLTINT 0x01380 381#define SEQINTCODE 0x02382#define BAD_SCB_STATUS 0x1a383#define SAW_HWERR 0x19384#define TRACEPOINT3 0x18385#define TRACEPOINT2 0x17386#define TRACEPOINT1 0x16387#define TRACEPOINT0 0x15388#define TASKMGMT_CMD_CMPLT_OKAY 0x14389#define TASKMGMT_FUNC_COMPLETE 0x13390#define ENTERING_NONPACK 0x12391#define CFG4OVERRUN 0x11392#define STATUS_OVERRUN 0x10393#define CFG4ISTAT_INTR 0x0f394#define INVALID_SEQINT 0x0e395#define ILLEGAL_PHASE 0x0d396#define DUMP_CARD_STATE 0x0c397#define MISSED_BUSFREE 0x0b398#define MKMSG_FAILED 0x0a399#define DATA_OVERRUN 0x09400#define BAD_STATUS 0x08401#define HOST_MSG_LOOP 0x07402#define PDATA_REINIT 0x06403#define IGN_WIDE_RES 0x05404#define NO_MATCH 0x04405#define PROTO_VIOLATION 0x03406#define SEND_REJECT 0x02407#define BAD_PHASE 0x01408#define NO_SEQINT 0x00409 410#define CLRINT 0x03411#define CLRHWERRINT 0x80412#define CLRBRKADRINT 0x40413#define CLRSWTMINT 0x20414#define CLRPCIINT 0x10415#define CLRSCSIINT 0x08416#define CLRSEQINT 0x04417#define CLRCMDINT 0x02418#define CLRSPLTINT 0x01419 420#define CLRERR 0x04421#define CLRCIOPARERR 0x80422#define CLRCIOACCESFAIL 0x40423#define CLRMPARERR 0x20424#define CLRDPARERR 0x10425#define CLRSQPARERR 0x08426#define CLRILLOPCODE 0x04427#define CLRDSCTMOUT 0x02428 429#define ERROR 0x04430#define CIOPARERR 0x80431#define CIOACCESFAIL 0x40432#define MPARERR 0x20433#define DPARERR 0x10434#define SQPARERR 0x08435#define ILLOPCODE 0x04436#define DSCTMOUT 0x02437 438#define HCNTRL 0x05439#define SEQ_RESET 0x80440#define POWRDN 0x40441#define SWINT 0x10442#define SWTIMER_START_B 0x08443#define PAUSE 0x04444#define INTEN 0x02445#define CHIPRST 0x01446#define CHIPRSTACK 0x01447 448#define HNSCB_QOFF 0x06449 450#define HESCB_QOFF 0x08451 452#define HS_MAILBOX 0x0b453#define HOST_TQINPOS 0x80454#define ENINT_COALESCE 0x40455 456#define SEQINTSTAT 0x0c457#define SEQ_SWTMRTO 0x10458#define SEQ_SEQINT 0x08459#define SEQ_SCSIINT 0x04460#define SEQ_PCIINT 0x02461#define SEQ_SPLTINT 0x01462 463#define CLRSEQINTSTAT 0x0c464#define CLRSEQ_SWTMRTO 0x10465#define CLRSEQ_SEQINT 0x08466#define CLRSEQ_SCSIINT 0x04467#define CLRSEQ_PCIINT 0x02468#define CLRSEQ_SPLTINT 0x01469 470#define SWTIMER 0x0e471 472#define SNSCB_QOFF 0x10473 474#define SESCB_QOFF 0x12475 476#define SDSCB_QOFF 0x14477 478#define QOFF_CTLSTA 0x16479#define EMPTY_SCB_AVAIL 0x80480#define NEW_SCB_AVAIL 0x40481#define SDSCB_ROLLOVR 0x20482#define HS_MAILBOX_ACT 0x10483#define SCB_QSIZE 0x0f484#define SCB_QSIZE_16384 0x0c485#define SCB_QSIZE_8192 0x0b486#define SCB_QSIZE_4096 0x0a487#define SCB_QSIZE_2048 0x09488#define SCB_QSIZE_1024 0x08489#define SCB_QSIZE_512 0x07490#define SCB_QSIZE_256 0x06491#define SCB_QSIZE_128 0x05492#define SCB_QSIZE_64 0x04493#define SCB_QSIZE_32 0x03494#define SCB_QSIZE_16 0x02495#define SCB_QSIZE_8 0x01496#define SCB_QSIZE_4 0x00497 498#define INTCTL 0x18499#define SWTMINTMASK 0x80500#define SWTMINTEN 0x40501#define SWTIMER_START 0x20502#define AUTOCLRCMDINT 0x10503#define PCIINTEN 0x08504#define SCSIINTEN 0x04505#define SEQINTEN 0x02506#define SPLTINTEN 0x01507 508#define DFCNTRL 0x19509#define SCSIENWRDIS 0x40510#define SCSIENACK 0x20511#define DIRECTIONACK 0x04512#define FIFOFLUSHACK 0x02513#define DIRECTIONEN 0x01514 515#define DSCOMMAND0 0x19516#define CACHETHEN 0x80517#define DPARCKEN 0x40518#define MPARCKEN 0x20519#define EXTREQLCK 0x10520#define DISABLE_TWATE 0x02521#define CIOPARCKEN 0x01522 523#define DFSTATUS 0x1a524#define PRELOAD_AVAIL 0x80525#define PKT_PRELOAD_AVAIL 0x40526#define MREQPEND 0x10527#define HDONE 0x08528#define DFTHRESH 0x04529#define FIFOFULL 0x02530#define FIFOEMP 0x01531 532#define ARBCTL 0x1b533#define RESET_HARB 0x80534#define RETRY_SWEN 0x08535#define USE_TIME 0x07536 537#define SG_CACHE_SHADOW 0x1b538#define ODD_SEG 0x04539#define LAST_SEG 0x02540#define LAST_SEG_DONE 0x01541 542#define SG_CACHE_PRE 0x1b543 544#define TYPEPTR 0x20545 546#define LQIN 0x20547 548#define TAGPTR 0x21549 550#define LUNPTR 0x22551 552#define DATALENPTR 0x23553 554#define STATLENPTR 0x24555 556#define CMDLENPTR 0x25557 558#define ATTRPTR 0x26559 560#define FLAGPTR 0x27561 562#define CMDPTR 0x28563 564#define QNEXTPTR 0x29565 566#define IDPTR 0x2a567 568#define ABRTBYTEPTR 0x2b569 570#define ABRTBITPTR 0x2c571 572#define MAXCMDBYTES 0x2d573 574#define MAXCMD2RCV 0x2e575 576#define SHORTTHRESH 0x2f577 578#define LUNLEN 0x30579#define TLUNLEN 0xf0580#define ILUNLEN 0x0f581 582#define CDBLIMIT 0x31583 584#define MAXCMD 0x32585 586#define MAXCMDCNT 0x33587 588#define LQRSVD01 0x34589 590#define LQRSVD16 0x35591 592#define LQRSVD17 0x36593 594#define CMDRSVD0 0x37595 596#define LQCTL0 0x38597#define LQITARGCLT 0xc0598#define LQIINITGCLT 0x30599#define LQ0TARGCLT 0x0c600#define LQ0INITGCLT 0x03601 602#define LQCTL1 0x38603#define PCI2PCI 0x04604#define SINGLECMD 0x02605#define ABORTPENDING 0x01606 607#define LQCTL2 0x39608#define LQIRETRY 0x80609#define LQICONTINUE 0x40610#define LQITOIDLE 0x20611#define LQIPAUSE 0x10612#define LQORETRY 0x08613#define LQOCONTINUE 0x04614#define LQOTOIDLE 0x02615#define LQOPAUSE 0x01616 617#define SCSBIST0 0x39618#define GSBISTERR 0x40619#define GSBISTDONE 0x20620#define GSBISTRUN 0x10621#define OSBISTERR 0x04622#define OSBISTDONE 0x02623#define OSBISTRUN 0x01624 625#define SCSISEQ0 0x3a626#define TEMODEO 0x80627#define ENSELO 0x40628#define ENARBO 0x20629#define FORCEBUSFREE 0x10630#define SCSIRSTO 0x01631 632#define SCSBIST1 0x3a633#define NTBISTERR 0x04634#define NTBISTDONE 0x02635#define NTBISTRUN 0x01636 637#define SCSISEQ1 0x3b638 639#define BUSINITID 0x3c640 641#define SXFRCTL0 0x3c642#define DFON 0x80643#define DFPEXP 0x40644#define BIOSCANCELEN 0x10645#define SPIOEN 0x08646 647#define DLCOUNT 0x3c648 649#define SXFRCTL1 0x3d650#define BITBUCKET 0x80651#define ENSACHK 0x40652#define ENSPCHK 0x20653#define STIMESEL 0x18654#define ENSTIMER 0x04655#define ACTNEGEN 0x02656#define STPWEN 0x01657 658#define BUSTARGID 0x3e659 660#define SXFRCTL2 0x3e661#define AUTORSTDIS 0x10662#define CMDDMAEN 0x08663#define ASU 0x07664 665#define DFFSTAT 0x3f666#define CURRFIFO 0x03667#define FIFO1FREE 0x20668#define FIFO0FREE 0x10669#define CURRFIFO_NONE 0x03670#define CURRFIFO_1 0x01671#define CURRFIFO_0 0x00672 673#define MULTARGID 0x40674 675#define SCSISIGO 0x40676#define CDO 0x80677#define IOO 0x40678#define MSGO 0x20679#define ATNO 0x10680#define SELO 0x08681#define BSYO 0x04682#define REQO 0x02683#define ACKO 0x01684 685#define SCSISIGI 0x41686#define ATNI 0x10687#define SELI 0x08688#define BSYI 0x04689#define REQI 0x02690#define ACKI 0x01691 692#define SCSIPHASE 0x42693#define STATUS_PHASE 0x20694#define COMMAND_PHASE 0x10695#define MSG_IN_PHASE 0x08696#define MSG_OUT_PHASE 0x04697#define DATA_PHASE_MASK 0x03698#define DATA_IN_PHASE 0x02699#define DATA_OUT_PHASE 0x01700 701#define SCSIDAT0_IMG 0x43702 703#define SCSIDAT 0x44704 705#define SCSIBUS 0x46706 707#define TARGIDIN 0x48708#define CLKOUT 0x80709#define TARGID 0x0f710 711#define SELID 0x49712#define SELID_MASK 0xf0713#define ONEBIT 0x08714 715#define OPTIONMODE 0x4a716#define OPTIONMODE_DEFAULTS 0x02717#define BIOSCANCTL 0x80718#define AUTOACKEN 0x40719#define BIASCANCTL 0x20720#define BUSFREEREV 0x10721#define ENDGFORMCHK 0x04722#define AUTO_MSGOUT_DE 0x02723 724#define SBLKCTL 0x4a725#define DIAGLEDEN 0x80726#define DIAGLEDON 0x40727#define ENAB40 0x08728#define ENAB20 0x04729#define SELWIDE 0x02730 731#define SIMODE0 0x4b732#define ENSELDO 0x40733#define ENSELDI 0x20734#define ENSELINGO 0x10735#define ENIOERR 0x08736#define ENOVERRUN 0x04737#define ENSPIORDY 0x02738#define ENARBDO 0x01739 740#define SSTAT0 0x4b741#define TARGET 0x80742#define SELDO 0x40743#define SELDI 0x20744#define SELINGO 0x10745#define IOERR 0x08746#define OVERRUN 0x04747#define SPIORDY 0x02748#define ARBDO 0x01749 750#define CLRSINT0 0x4b751#define CLRSELDO 0x40752#define CLRSELDI 0x20753#define CLRSELINGO 0x10754#define CLRIOERR 0x08755#define CLROVERRUN 0x04756#define CLRSPIORDY 0x02757#define CLRARBDO 0x01758 759#define SSTAT1 0x4c760#define SELTO 0x80761#define ATNTARG 0x40762#define SCSIRSTI 0x20763#define PHASEMIS 0x10764#define BUSFREE 0x08765#define SCSIPERR 0x04766#define STRB2FAST 0x02767#define REQINIT 0x01768 769#define CLRSINT1 0x4c770#define CLRSELTIMEO 0x80771#define CLRATNO 0x40772#define CLRSCSIRSTI 0x20773#define CLRBUSFREE 0x08774#define CLRSCSIPERR 0x04775#define CLRSTRB2FAST 0x02776#define CLRREQINIT 0x01777 778#define SIMODE2 0x4d779#define ENWIDE_RES 0x04780#define ENSDONE 0x02781#define ENDMADONE 0x01782 783#define SSTAT2 0x4d784#define BUSFREETIME 0xc0785#define NONPACKREQ 0x20786#define EXP_ACTIVE 0x10787#define BSYX 0x08788#define WIDE_RES 0x04789#define SDONE 0x02790#define DMADONE 0x01791#define BUSFREE_DFF1 0xc0792#define BUSFREE_DFF0 0x80793#define BUSFREE_LQO 0x40794 795#define CLRSINT2 0x4d796#define CLRNONPACKREQ 0x20797#define CLRWIDE_RES 0x04798#define CLRSDONE 0x02799#define CLRDMADONE 0x01800 801#define PERRDIAG 0x4e802#define HIZERO 0x80803#define HIPERR 0x40804#define PREVPHASE 0x20805#define PARITYERR 0x10806#define AIPERR 0x08807#define CRCERR 0x04808#define DGFORMERR 0x02809#define DTERR 0x01810 811#define LQISTATE 0x4e812 813#define LQOSTATE 0x4f814 815#define SOFFCNT 0x4f816 817#define LQISTAT0 0x50818#define LQIATNQAS 0x20819#define LQICRCT1 0x10820#define LQICRCT2 0x08821#define LQIBADLQT 0x04822#define LQIATNLQ 0x02823#define LQIATNCMD 0x01824 825#define LQIMODE0 0x50826#define ENLQIATNQASK 0x20827#define ENLQICRCT1 0x10828#define ENLQICRCT2 0x08829#define ENLQIBADLQT 0x04830#define ENLQIATNLQ 0x02831#define ENLQIATNCMD 0x01832 833#define CLRLQIINT0 0x50834#define CLRLQIATNQAS 0x20835#define CLRLQICRCT1 0x10836#define CLRLQICRCT2 0x08837#define CLRLQIBADLQT 0x04838#define CLRLQIATNLQ 0x02839#define CLRLQIATNCMD 0x01840 841#define LQIMODE1 0x51842#define ENLQIPHASE_LQ 0x80843#define ENLQIPHASE_NLQ 0x40844#define ENLIQABORT 0x20845#define ENLQICRCI_LQ 0x10846#define ENLQICRCI_NLQ 0x08847#define ENLQIBADLQI 0x04848#define ENLQIOVERI_LQ 0x02849#define ENLQIOVERI_NLQ 0x01850 851#define LQISTAT1 0x51852#define LQIPHASE_LQ 0x80853#define LQIPHASE_NLQ 0x40854#define LQIABORT 0x20855#define LQICRCI_LQ 0x10856#define LQICRCI_NLQ 0x08857#define LQIBADLQI 0x04858#define LQIOVERI_LQ 0x02859#define LQIOVERI_NLQ 0x01860 861#define CLRLQIINT1 0x51862#define CLRLQIPHASE_LQ 0x80863#define CLRLQIPHASE_NLQ 0x40864#define CLRLIQABORT 0x20865#define CLRLQICRCI_LQ 0x10866#define CLRLQICRCI_NLQ 0x08867#define CLRLQIBADLQI 0x04868#define CLRLQIOVERI_LQ 0x02869#define CLRLQIOVERI_NLQ 0x01870 871#define LQISTAT2 0x52872#define PACKETIZED 0x80873#define LQIPHASE_OUTPKT 0x40874#define LQIWORKONLQ 0x20875#define LQIWAITFIFO 0x10876#define LQISTOPPKT 0x08877#define LQISTOPLQ 0x04878#define LQISTOPCMD 0x02879#define LQIGSAVAIL 0x01880 881#define SIMODE3 0x53882#define ENNTRAMPERR 0x02883#define ENOSRAMPERR 0x01884 885#define SSTAT3 0x53886#define NTRAMPERR 0x02887#define OSRAMPERR 0x01888 889#define CLRSINT3 0x53890#define CLRNTRAMPERR 0x02891#define CLROSRAMPERR 0x01892 893#define CLRLQOINT0 0x54894#define CLRLQOTARGSCBPERR 0x10895#define CLRLQOSTOPT2 0x08896#define CLRLQOATNLQ 0x04897#define CLRLQOATNPKT 0x02898#define CLRLQOTCRC 0x01899 900#define LQOSTAT0 0x54901#define LQOTARGSCBPERR 0x10902#define LQOSTOPT2 0x08903#define LQOATNLQ 0x04904#define LQOATNPKT 0x02905#define LQOTCRC 0x01906 907#define LQOMODE0 0x54908#define ENLQOTARGSCBPERR 0x10909#define ENLQOSTOPT2 0x08910#define ENLQOATNLQ 0x04911#define ENLQOATNPKT 0x02912#define ENLQOTCRC 0x01913 914#define LQOMODE1 0x55915#define ENLQOINITSCBPERR 0x10916#define ENLQOSTOPI2 0x08917#define ENLQOBADQAS 0x04918#define ENLQOBUSFREE 0x02919#define ENLQOPHACHGINPKT 0x01920 921#define CLRLQOINT1 0x55922#define CLRLQOINITSCBPERR 0x10923#define CLRLQOSTOPI2 0x08924#define CLRLQOBADQAS 0x04925#define CLRLQOBUSFREE 0x02926#define CLRLQOPHACHGINPKT 0x01927 928#define LQOSTAT1 0x55929#define LQOINITSCBPERR 0x10930#define LQOSTOPI2 0x08931#define LQOBADQAS 0x04932#define LQOBUSFREE 0x02933#define LQOPHACHGINPKT 0x01934 935#define LQOSTAT2 0x56936#define LQOPKT 0xe0937#define LQOWAITFIFO 0x10938#define LQOPHACHGOUTPKT 0x02939#define LQOSTOP0 0x01940 941#define OS_SPACE_CNT 0x56942 943#define SIMODE1 0x57944#define ENSELTIMO 0x80945#define ENATNTARG 0x40946#define ENSCSIRST 0x20947#define ENPHASEMIS 0x10948#define ENBUSFREE 0x08949#define ENSCSIPERR 0x04950#define ENSTRB2FAST 0x02951#define ENREQINIT 0x01952 953#define GSFIFO 0x58954 955#define DFFSXFRCTL 0x5a956#define DFFBITBUCKET 0x08957#define CLRSHCNT 0x04958#define CLRCHN 0x02959#define RSTCHN 0x01960 961#define LQOSCSCTL 0x5a962#define LQOH2A_VERSION 0x80963#define LQOBUSETDLY 0x40964#define LQONOHOLDLACK 0x02965#define LQONOCHKOVER 0x01966 967#define NEXTSCB 0x5a968 969#define CLRSEQINTSRC 0x5b970#define CLRCTXTDONE 0x40971#define CLRSAVEPTRS 0x20972#define CLRCFG4DATA 0x10973#define CLRCFG4ISTAT 0x08974#define CLRCFG4TSTAT 0x04975#define CLRCFG4ICMD 0x02976#define CLRCFG4TCMD 0x01977 978#define SEQINTSRC 0x5b979#define CTXTDONE 0x40980#define SAVEPTRS 0x20981#define CFG4DATA 0x10982#define CFG4ISTAT 0x08983#define CFG4TSTAT 0x04984#define CFG4ICMD 0x02985#define CFG4TCMD 0x01986 987#define SEQIMODE 0x5c988#define ENCTXTDONE 0x40989#define ENSAVEPTRS 0x20990#define ENCFG4DATA 0x10991#define ENCFG4ISTAT 0x08992#define ENCFG4TSTAT 0x04993#define ENCFG4ICMD 0x02994#define ENCFG4TCMD 0x01995 996#define CURRSCB 0x5c997 998#define CRCCONTROL 0x5d999#define CRCVALCHKEN 0x401000 1001#define MDFFSTAT 0x5d1002#define SHCNTNEGATIVE 0x401003#define SHCNTMINUS1 0x201004#define LASTSDONE 0x101005#define SHVALID 0x081006#define DLZERO 0x041007#define DATAINFIFO 0x021008#define FIFOFREE 0x011009 1010#define DFFTAG 0x5e1011 1012#define SCSITEST 0x5e1013#define CNTRTEST 0x081014#define SEL_TXPLL_DEBUG 0x041015 1016#define LASTSCB 0x5e1017 1018#define IOPDNCTL 0x5f1019#define DISABLE_OE 0x801020#define PDN_IDIST 0x041021#define PDN_DIFFSENSE 0x011022 1023#define DGRPCRCI 0x601024 1025#define NEGOADDR 0x601026 1027#define SHADDR 0x601028 1029#define NEGPERIOD 0x611030 1031#define NEGOFFSET 0x621032 1033#define PACKCRCI 0x621034 1035#define NEGPPROPTS 0x631036#define PPROPT_PACE 0x081037#define PPROPT_QAS 0x041038#define PPROPT_DT 0x021039#define PPROPT_IUT 0x011040 1041#define NEGCONOPTS 0x641042#define ENSNAPSHOT 0x401043#define RTI_WRTDIS 0x201044#define RTI_OVRDTRN 0x101045#define ENSLOWCRC 0x081046#define ENAUTOATNI 0x041047#define ENAUTOATNO 0x021048#define WIDEXFER 0x011049 1050#define ANNEXCOL 0x651051 1052#define ANNEXDAT 0x661053 1054#define SCSCHKN 0x661055#define BIDICHKDIS 0x801056#define STSELSKIDDIS 0x401057#define CURRFIFODEF 0x201058#define WIDERESEN 0x101059#define SDONEMSKDIS 0x081060#define DFFACTCLR 0x041061#define SHVALIDSTDIS 0x021062#define LSTSGCLRDIS 0x011063 1064#define IOWNID 0x671065 1066#define PLL960CTL0 0x681067 1068#define SHCNT 0x681069 1070#define PLL960CTL1 0x691071 1072#define TOWNID 0x691073 1074#define PLL960CNT0 0x6a1075 1076#define XSIG 0x6a1077 1078#define SELOID 0x6b1079 1080#define FAIRNESS 0x6c1081 1082#define PLL400CTL0 0x6c1083#define PLL_VCOSEL 0x801084#define PLL_PWDN 0x401085#define PLL_NS 0x301086#define PLL_ENLUD 0x081087#define PLL_ENLPF 0x041088#define PLL_DLPF 0x021089#define PLL_ENFBM 0x011090 1091#define PLL400CTL1 0x6d1092#define PLL_CNTEN 0x801093#define PLL_CNTCLR 0x401094#define PLL_RST 0x011095 1096#define UNFAIRNESS 0x6e1097 1098#define PLL400CNT0 0x6e1099 1100#define HADDR 0x701101 1102#define HODMAADR 0x701103 1104#define PLLDELAY 0x701105#define SPLIT_DROP_REQ 0x801106 1107#define HCNT 0x781108 1109#define HODMACNT 0x781110 1111#define HODMAEN 0x7a1112 1113#define SGHADDR 0x7c1114 1115#define SCBHADDR 0x7c1116 1117#define SGHCNT 0x841118 1119#define SCBHCNT 0x841120 1121#define DFF_THRSH 0x881122#define WR_DFTHRSH 0x701123#define RD_DFTHRSH 0x071124#define WR_DFTHRSH_MAX 0x701125#define WR_DFTHRSH_90 0x601126#define WR_DFTHRSH_85 0x501127#define WR_DFTHRSH_75 0x401128#define WR_DFTHRSH_63 0x301129#define WR_DFTHRSH_50 0x201130#define WR_DFTHRSH_25 0x101131#define RD_DFTHRSH_MAX 0x071132#define RD_DFTHRSH_90 0x061133#define RD_DFTHRSH_85 0x051134#define RD_DFTHRSH_75 0x041135#define RD_DFTHRSH_63 0x031136#define RD_DFTHRSH_50 0x021137#define RD_DFTHRSH_25 0x011138#define RD_DFTHRSH_MIN 0x001139#define WR_DFTHRSH_MIN 0x001140 1141#define ROMADDR 0x8a1142 1143#define ROMCNTRL 0x8d1144#define ROMOP 0xe01145#define ROMSPD 0x181146#define REPEAT 0x021147#define RDY 0x011148 1149#define ROMDATA 0x8e1150 1151#define CMCRXMSG0 0x901152 1153#define OVLYRXMSG0 0x901154 1155#define DCHRXMSG0 0x901156 1157#define ROENABLE 0x901158#define MSIROEN 0x201159#define OVLYROEN 0x101160#define CMCROEN 0x081161#define SGROEN 0x041162#define DCH1ROEN 0x021163#define DCH0ROEN 0x011164 1165#define OVLYRXMSG1 0x911166 1167#define CMCRXMSG1 0x911168 1169#define DCHRXMSG1 0x911170 1171#define NSENABLE 0x911172#define MSINSEN 0x201173#define OVLYNSEN 0x101174#define CMCNSEN 0x081175#define SGNSEN 0x041176#define DCH1NSEN 0x021177#define DCH0NSEN 0x011178 1179#define DCHRXMSG2 0x921180 1181#define CMCRXMSG2 0x921182 1183#define OST 0x921184 1185#define OVLYRXMSG2 0x921186 1187#define DCHRXMSG3 0x931188 1189#define OVLYRXMSG3 0x931190 1191#define CMCRXMSG3 0x931192 1193#define PCIXCTL 0x931194#define SERRPULSE 0x801195#define UNEXPSCIEN 0x201196#define SPLTSMADIS 0x101197#define SPLTSTADIS 0x081198#define SRSPDPEEN 0x041199#define TSCSERREN 0x021200#define CMPABCDIS 0x011201 1202#define CMCSEQBCNT 0x941203 1204#define OVLYSEQBCNT 0x941205 1206#define DCHSEQBCNT 0x941207 1208#define DCHSPLTSTAT0 0x961209 1210#define OVLYSPLTSTAT0 0x961211 1212#define CMCSPLTSTAT0 0x961213 1214#define OVLYSPLTSTAT1 0x971215 1216#define DCHSPLTSTAT1 0x971217 1218#define CMCSPLTSTAT1 0x971219 1220#define SGRXMSG0 0x981221#define CDNUM 0xf81222#define CFNUM 0x071223 1224#define SLVSPLTOUTADR0 0x981225#define LOWER_ADDR 0x7f1226 1227#define SGRXMSG1 0x991228#define CBNUM 0xff1229 1230#define SLVSPLTOUTADR1 0x991231#define REQ_DNUM 0xf81232#define REQ_FNUM 0x071233 1234#define SGRXMSG2 0x9a1235#define MINDEX 0xff1236 1237#define SLVSPLTOUTADR2 0x9a1238#define REQ_BNUM 0xff1239 1240#define SGRXMSG3 0x9b1241#define MCLASS 0x0f1242 1243#define SLVSPLTOUTADR3 0x9b1244#define TAG_NUM 0x1f1245#define RLXORD 0x101246 1247#define SLVSPLTOUTATTR0 0x9c1248#define LOWER_BCNT 0xff1249 1250#define SGSEQBCNT 0x9c1251 1252#define SLVSPLTOUTATTR1 0x9d1253#define CMPLT_DNUM 0xf81254#define CMPLT_FNUM 0x071255 1256#define SGSPLTSTAT0 0x9e1257#define STAETERM 0x801258#define SCBCERR 0x401259#define SCADERR 0x201260#define SCDATBUCKET 0x101261#define CNTNOTCMPLT 0x081262#define RXOVRUN 0x041263#define RXSCEMSG 0x021264#define RXSPLTRSP 0x011265 1266#define SLVSPLTOUTATTR2 0x9e1267#define CMPLT_BNUM 0xff1268 1269#define SGSPLTSTAT1 0x9f1270#define RXDATABUCKET 0x011271 1272#define SFUNCT 0x9f1273#define TEST_GROUP 0xf01274#define TEST_NUM 0x0f1275 1276#define DF0PCISTAT 0xa01277 1278#define REG0 0xa01279 1280#define DF1PCISTAT 0xa11281 1282#define SGPCISTAT 0xa21283 1284#define REG1 0xa21285 1286#define CMCPCISTAT 0xa31287 1288#define OVLYPCISTAT 0xa41289#define SCAAPERR 0x081290#define RDPERR 0x041291 1292#define REG_ISR 0xa41293 1294#define SG_STATE 0xa61295#define FETCH_INPROG 0x041296#define LOADING_NEEDED 0x021297#define SEGS_AVAIL 0x011298 1299#define MSIPCISTAT 0xa61300#define RMA 0x201301#define RTA 0x101302#define CLRPENDMSI 0x081303#define DPR 0x011304 1305#define DATA_COUNT_ODD 0xa71306 1307#define TARGPCISTAT 0xa71308#define DPE 0x801309#define SSE 0x401310#define STA 0x081311#define TWATERR 0x021312 1313#define SCBPTR 0xa81314 1315#define CCSCBACNT 0xab1316 1317#define SCBAUTOPTR 0xab1318#define AUSCBPTR_EN 0x801319#define SCBPTR_ADDR 0x381320#define SCBPTR_OFF 0x071321 1322#define CCSGADDR 0xac1323 1324#define CCSCBADDR 0xac1325 1326#define CCSCBADR_BK 0xac1327 1328#define CMC_RAMBIST 0xad1329#define SG_ELEMENT_SIZE 0x801330#define SCBRAMBIST_FAIL 0x401331#define SG_BIST_FAIL 0x201332#define SG_BIST_EN 0x101333#define CMC_BUFFER_BIST_FAIL 0x021334#define CMC_BUFFER_BIST_EN 0x011335 1336#define CCSCBCTL 0xad1337#define CCSCBDONE 0x801338#define ARRDONE 0x401339#define CCARREN 0x101340#define CCSCBEN 0x081341#define CCSCBDIR 0x041342#define CCSCBRESET 0x011343 1344#define CCSGCTL 0xad1345#define CCSGEN 0x0c1346#define CCSGDONE 0x801347#define SG_CACHE_AVAIL 0x101348#define CCSGENACK 0x081349#define SG_FETCH_REQ 0x021350#define CCSGRESET 0x011351 1352#define CCSGRAM 0xb01353 1354#define FLEXADR 0xb01355 1356#define CCSCBRAM 0xb01357 1358#define FLEXCNT 0xb31359 1360#define FLEXDMASTAT 0xb51361#define FLEXDMAERR 0x021362#define FLEXDMADONE 0x011363 1364#define FLEXDATA 0xb61365 1366#define BRDDAT 0xb81367 1368#define BRDCTL 0xb91369#define FLXARBACK 0x801370#define FLXARBREQ 0x401371#define BRDADDR 0x381372#define BRDEN 0x041373#define BRDRW 0x021374#define BRDSTB 0x011375 1376#define SEEADR 0xba1377 1378#define SEEDAT 0xbc1379 1380#define SEECTL 0xbe1381#define SEEOP_EWDS 0x401382#define SEEOP_WALL 0x401383#define SEEOP_EWEN 0x401384#define SEEOPCODE 0x701385#define SEERST 0x021386#define SEESTART 0x011387#define SEEOP_ERASE 0x701388#define SEEOP_READ 0x601389#define SEEOP_WRITE 0x501390#define SEEOP_ERAL 0x401391 1392#define SEESTAT 0xbe1393#define INIT_DONE 0x801394#define LDALTID_L 0x081395#define SEEARBACK 0x041396#define SEEBUSY 0x021397 1398#define SCBCNT 0xbf1399 1400#define DSPFLTRCTL 0xc01401#define FLTRDISABLE 0x201402#define EDGESENSE 0x101403#define DSPFCNTSEL 0x0f1404 1405#define DFWADDR 0xc01406 1407#define DSPDATACTL 0xc11408#define BYPASSENAB 0x801409#define DESQDIS 0x101410#define RCVROFFSTDIS 0x041411#define XMITOFFSTDIS 0x021412 1413#define DSPREQCTL 0xc21414#define MANREQCTL 0xc01415#define MANREQDLY 0x3f1416 1417#define DFRADDR 0xc21418 1419#define DSPACKCTL 0xc31420#define MANACKCTL 0xc01421#define MANACKDLY 0x3f1422 1423#define DFDAT 0xc41424 1425#define DSPSELECT 0xc41426#define AUTOINCEN 0x801427#define DSPSEL 0x1f1428 1429#define WRTBIASCTL 0xc51430#define AUTOXBCDIS 0x801431#define XMITMANVAL 0x3f1432 1433#define RCVRBIOSCTL 0xc61434#define AUTORBCDIS 0x801435#define RCVRMANVAL 0x3f1436 1437#define WRTBIASCALC 0xc71438 1439#define DFPTRS 0xc81440 1441#define RCVRBIASCALC 0xc81442 1443#define DFBKPTR 0xc91444 1445#define SKEWCALC 0xc91446 1447#define DFDBCTL 0xcb1448#define DFF_CIO_WR_RDY 0x201449#define DFF_CIO_RD_RDY 0x101450#define DFF_DIR_ERR 0x081451#define DFF_RAMBIST_FAIL 0x041452#define DFF_RAMBIST_DONE 0x021453#define DFF_RAMBIST_EN 0x011454 1455#define DFSCNT 0xcc1456 1457#define DFBCNT 0xce1458 1459#define OVLYADDR 0xd41460 1461#define SEQCTL0 0xd61462#define PERRORDIS 0x801463#define PAUSEDIS 0x401464#define FAILDIS 0x201465#define FASTMODE 0x101466#define BRKADRINTEN 0x081467#define STEP 0x041468#define SEQRESET 0x021469#define LOADRAM 0x011470 1471#define SEQCTL1 0xd71472#define OVRLAY_DATA_CHK 0x081473#define RAMBIST_DONE 0x041474#define RAMBIST_FAIL 0x021475#define RAMBIST_EN 0x011476 1477#define FLAGS 0xd81478#define ZERO 0x021479#define CARRY 0x011480 1481#define SEQINTCTL 0xd91482#define INTVEC1DSL 0x801483#define INT1_CONTEXT 0x201484#define SCS_SEQ_INT1M1 0x101485#define SCS_SEQ_INT1M0 0x081486#define INTMASK2 0x041487#define INTMASK1 0x021488#define IRET 0x011489 1490#define SEQRAM 0xda1491 1492#define PRGMCNT 0xde1493 1494#define ACCUM 0xe01495 1496#define SINDEX 0xe21497 1498#define DINDEX 0xe41499 1500#define BRKADDR0 0xe61501 1502#define BRKADDR1 0xe61503#define BRKDIS 0x801504 1505#define ALLONES 0xe81506 1507#define ALLZEROS 0xea1508 1509#define NONE 0xea1510 1511#define SINDIR 0xec1512 1513#define DINDIR 0xed1514 1515#define FUNCTION1 0xf01516 1517#define STACK 0xf21518 1519#define INTVEC1_ADDR 0xf41520 1521#define CURADDR 0xf41522 1523#define LASTADDR 0xf61524 1525#define INTVEC2_ADDR 0xf61526 1527#define LONGJMP_ADDR 0xf81528 1529#define ACCUM_SAVE 0xfa1530 1531#define AHD_PCI_CONFIG_BASE 0x1001532 1533#define SRAM_BASE 0x1001534 1535#define WAITING_SCB_TAILS 0x1001536 1537#define WAITING_TID_HEAD 0x1201538 1539#define WAITING_TID_TAIL 0x1221540 1541#define NEXT_QUEUED_SCB_ADDR 0x1241542 1543#define COMPLETE_SCB_HEAD 0x1281544 1545#define COMPLETE_SCB_DMAINPROG_HEAD 0x12a1546 1547#define COMPLETE_DMA_SCB_HEAD 0x12c1548 1549#define COMPLETE_DMA_SCB_TAIL 0x12e1550 1551#define COMPLETE_ON_QFREEZE_HEAD 0x1301552 1553#define QFREEZE_COUNT 0x1321554 1555#define KERNEL_QFREEZE_COUNT 0x1341556 1557#define SAVED_MODE 0x1361558 1559#define MSG_OUT 0x1371560 1561#define DMAPARAMS 0x1381562#define PRELOADEN 0x801563#define WIDEODD 0x401564#define SCSIEN 0x201565#define SDMAENACK 0x101566#define SDMAEN 0x101567#define HDMAEN 0x081568#define HDMAENACK 0x081569#define DIRECTION 0x041570#define FIFOFLUSH 0x021571#define FIFORESET 0x011572 1573#define SEQ_FLAGS 0x1391574#define NOT_IDENTIFIED 0x801575#define NO_CDB_SENT 0x401576#define TARGET_CMD_IS_TAGGED 0x401577#define DPHASE 0x201578#define TARG_CMD_PENDING 0x101579#define CMDPHASE_PENDING 0x081580#define DPHASE_PENDING 0x041581#define SPHASE_PENDING 0x021582#define NO_DISCONNECT 0x011583 1584#define SAVED_SCSIID 0x13a1585 1586#define SAVED_LUN 0x13b1587 1588#define LASTPHASE 0x13c1589#define PHASE_MASK 0xe01590#define CDI 0x801591#define IOI 0x401592#define MSGI 0x201593#define P_BUSFREE 0x011594#define P_MESGIN 0xe01595#define P_STATUS 0xc01596#define P_MESGOUT 0xa01597#define P_COMMAND 0x801598#define P_DATAIN_DT 0x601599#define P_DATAIN 0x401600#define P_DATAOUT_DT 0x201601#define P_DATAOUT 0x001602 1603#define QOUTFIFO_ENTRY_VALID_TAG 0x13d1604 1605#define KERNEL_TQINPOS 0x13e1606 1607#define TQINPOS 0x13f1608 1609#define SHARED_DATA_ADDR 0x1401610 1611#define QOUTFIFO_NEXT_ADDR 0x1441612 1613#define ARG_1 0x1481614#define RETURN_1 0x1481615#define SEND_MSG 0x801616#define SEND_SENSE 0x401617#define SEND_REJ 0x201618#define MSGOUT_PHASEMIS 0x101619#define EXIT_MSG_LOOP 0x081620#define CONT_MSG_LOOP_WRITE 0x041621#define CONT_MSG_LOOP_READ 0x031622#define CONT_MSG_LOOP_TARG 0x021623 1624#define ARG_2 0x1491625#define RETURN_2 0x1491626 1627#define LAST_MSG 0x14a1628 1629#define SCSISEQ_TEMPLATE 0x14b1630#define MANUALCTL 0x401631#define ENSELI 0x201632#define ENRSELI 0x101633#define MANUALP 0x0c1634#define ENAUTOATNP 0x021635#define ALTSTIM 0x011636 1637#define INITIATOR_TAG 0x14c1638 1639#define SEQ_FLAGS2 0x14d1640#define SELECTOUT_QFROZEN 0x041641#define TARGET_MSG_PENDING 0x021642#define PENDING_MK_MESSAGE 0x011643 1644#define ALLOCFIFO_SCBPTR 0x14e1645 1646#define INT_COALESCING_TIMER 0x1501647 1648#define INT_COALESCING_MAXCMDS 0x1521649 1650#define INT_COALESCING_MINCMDS 0x1531651 1652#define CMDS_PENDING 0x1541653 1654#define INT_COALESCING_CMDCOUNT 0x1561655 1656#define LOCAL_HS_MAILBOX 0x1571657 1658#define CMDSIZE_TABLE 0x1581659 1660#define MK_MESSAGE_SCB 0x1601661 1662#define MK_MESSAGE_SCSIID 0x1621663 1664#define SCB_RESIDUAL_DATACNT 0x1801665#define SCB_CDB_STORE 0x1801666#define SCB_HOST_CDB_PTR 0x1801667 1668#define SCB_BASE 0x1801669 1670#define SCB_RESIDUAL_SGPTR 0x1841671#define SG_ADDR_MASK 0xf81672#define SG_OVERRUN_RESID 0x021673 1674#define SCB_SCSI_STATUS 0x1881675#define SCB_HOST_CDB_LEN 0x1881676 1677#define SCB_TARGET_PHASES 0x1891678 1679#define SCB_TARGET_DATA_DIR 0x18a1680 1681#define SCB_TARGET_ITAG 0x18b1682 1683#define SCB_SENSE_BUSADDR 0x18c1684#define SCB_NEXT_COMPLETE 0x18c1685 1686#define SCB_TAG 0x1901687#define SCB_FIFO_USE_COUNT 0x1901688 1689#define SCB_CONTROL 0x1921690#define TARGET_SCB 0x801691#define DISCENB 0x401692#define TAG_ENB 0x201693#define MK_MESSAGE 0x101694#define STATUS_RCVD 0x081695#define DISCONNECTED 0x041696#define SCB_TAG_TYPE 0x031697 1698#define SCB_SCSIID 0x1931699#define TID 0xf01700#define OID 0x0f1701 1702#define SCB_LUN 0x1941703#define LID 0xff1704 1705#define SCB_TASK_ATTRIBUTE 0x1951706#define SCB_XFERLEN_ODD 0x011707 1708#define SCB_CDB_LEN 0x1961709#define SCB_CDB_LEN_PTR 0x801710 1711#define SCB_TASK_MANAGEMENT 0x1971712 1713#define SCB_DATAPTR 0x1981714 1715#define SCB_DATACNT 0x1a01716#define SG_LAST_SEG 0x801717#define SG_HIGH_ADDR_BITS 0x7f1718 1719#define SCB_SGPTR 0x1a41720#define SG_STATUS_VALID 0x041721#define SG_FULL_RESID 0x021722#define SG_LIST_NULL 0x011723 1724#define SCB_BUSADDR 0x1a81725 1726#define SCB_NEXT 0x1ac1727#define SCB_NEXT_SCB_BUSADDR 0x1ac1728 1729#define SCB_NEXT2 0x1ae1730 1731#define SCB_SPARE 0x1b01732#define SCB_PKT_LUN 0x1b01733 1734#define SCB_DISCONNECTED_LISTS 0x1b81735 1736 1737#define STIMESEL_SHIFT 0x031738#define STIMESEL_MIN 0x181739#define INVALID_ADDR 0x801740#define CMD_GROUP_CODE_SHIFT 0x051741#define AHD_PRECOMP_MASK 0x071742#define TARGET_DATA_IN 0x011743#define SEEOP_EWEN_ADDR 0xc01744#define NUMDSPS 0x141745#define DST_MODE_SHIFT 0x041746#define CCSCBADDR_MAX 0x801747#define AHD_ANNEXCOL_PER_DEV0 0x041748#define TARGET_CMD_CMPLT 0xfe1749#define SEEOP_WRAL_ADDR 0x401750#define BUS_8_BIT 0x001751#define AHD_TIMER_MAX_US 0x18ffe71752#define AHD_TIMER_MAX_TICKS 0xffff1753#define AHD_SENSE_BUFSIZE 0x1001754#define AHD_PRECOMP_SHIFT 0x001755#define AHD_PRECOMP_CUTBACK_37 0x071756#define AHD_ANNEXCOL_PRECOMP_SLEW 0x041757#define AHD_AMPLITUDE_DEF 0x071758#define WRTBIASCTL_HP_DEFAULT 0x001759#define TID_SHIFT 0x041760#define STATUS_QUEUE_FULL 0x281761#define STATUS_BUSY 0x081762#define SEEOP_EWDS_ADDR 0x001763#define SCB_TRANSFER_SIZE_FULL_LUN 0x381764#define MK_MESSAGE_BIT_OFFSET 0x041765#define MAX_OFFSET_PACED 0xfe1766#define MAX_OFFSET_NON_PACED 0x7f1767#define LUNLEN_SINGLE_LEVEL_LUN 0x0f1768#define CCSGADDR_MAX 0x801769#define B_CURRFIFO_0 0x021770#define BUS_32_BIT 0x021771#define AHD_TIMER_US_PER_TICK 0x191772#define AHD_SLEWRATE_SHIFT 0x031773#define AHD_SLEWRATE_MASK 0x781774#define AHD_SLEWRATE_DEF_REVA 0x081775#define AHD_PRECOMP_CUTBACK_29 0x061776#define AHD_NUM_PER_DEV_ANNEXCOLS 0x041777#define AHD_ANNEXCOL_AMPLITUDE 0x061778#define AHD_AMPLITUDE_SHIFT 0x001779#define AHD_AMPLITUDE_MASK 0x071780#define STIMESEL_BUG_ADJ 0x081781#define STATUS_PKT_SENSE 0xff1782#define SRC_MODE_SHIFT 0x001783#define SEEOP_ERAL_ADDR 0x801784#define NVRAM_SCB_OFFSET 0x2c1785#define MAX_OFFSET_PACED_BUG 0x7f1786#define CCSGRAM_MAXSEGS 0x101787#define AHD_SLEWRATE_DEF_REVB 0x081788#define AHD_PRECOMP_CUTBACK_17 0x041789#define SCB_TRANSFER_SIZE_1BYTE_LUN 0x301790#define PKT_OVERRUN_BUFSIZE 0x2001791#define MAX_OFFSET 0xfe1792#define HOST_MSG 0xff1793#define BUS_16_BIT 0x011794 1795 1796/* Downloaded Constant Definitions */1797#define SG_SIZEOF 0x041798#define SG_PREFETCH_ALIGN_MASK 0x021799#define SG_PREFETCH_CNT_LIMIT 0x011800#define CACHELINE_MASK 0x071801#define SCB_TRANSFER_SIZE 0x061802#define PKT_OVERRUN_BUFOFFSET 0x051803#define SG_PREFETCH_ADDR_MASK 0x031804#define SG_PREFETCH_CNT 0x001805#define DOWNLOAD_CONST_COUNT 0x081806 1807 1808/* Exported Labels */1809#define LABEL_timer_isr 0x28b1810#define LABEL_seq_isr 0x28f1811