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1/*2 * Aic7xxx register and scratch ram definitions.3 *4 * Copyright (c) 1994-2001 Justin T. Gibbs.5 * Copyright (c) 2000-2001 Adaptec Inc.6 * All rights reserved.7 *8 * Redistribution and use in source and binary forms, with or without9 * modification, are permitted provided that the following conditions10 * are met:11 * 1. Redistributions of source code must retain the above copyright12 * notice, this list of conditions, and the following disclaimer,13 * without modification.14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer15 * substantially similar to the "NO WARRANTY" disclaimer below16 * ("Disclaimer") and any redistribution must be conditioned upon17 * including a substantially similar Disclaimer requirement for further18 * binary redistribution.19 * 3. Neither the names of the above-listed copyright holders nor the names20 * of any contributors may be used to endorse or promote products derived21 * from this software without specific prior written permission.22 *23 * Alternatively, this software may be distributed under the terms of the24 * GNU General Public License ("GPL") version 2 as published by the Free25 * Software Foundation.26 *27 * NO WARRANTY28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE38 * POSSIBILITY OF SUCH DAMAGES.39 *40 * $FreeBSD$41 */42VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $"43 44/*45 * This file is processed by the aic7xxx_asm utility for use in assembling46 * firmware for the aic7xxx family of SCSI host adapters as well as to generate47 * a C header file for use in the kernel portion of the Aic7xxx driver.48 *49 * All page numbers refer to the Adaptec AIC-7770 Data Book available from50 * Adaptec's Technical Documents Department 1-800-934-276651 */52 53/*54 * Registers marked "dont_generate_debug_code" are not (yet) referenced55 * from the driver code, and this keyword inhibit generation56 * of debug code for them.57 *58 * REG_PRETTY_PRINT config will complain if dont_generate_debug_code59 * is added to the register which is referenced in the driver.60 * Unreferenced register with no dont_generate_debug_code will result61 * in dead code. No warning is issued.62 */63 64/*65 * SCSI Sequence Control (p. 3-11).66 * Each bit, when set starts a specific SCSI sequence on the bus67 */68register SCSISEQ {69 address 0x00070 access_mode RW71 field TEMODE 0x8072 field ENSELO 0x4073 field ENSELI 0x2074 field ENRSELI 0x1075 field ENAUTOATNO 0x0876 field ENAUTOATNI 0x0477 field ENAUTOATNP 0x0278 field SCSIRSTO 0x0179}80 81/*82 * SCSI Transfer Control 0 Register (pp. 3-13).83 * Controls the SCSI module data path.84 */85register SXFRCTL0 {86 address 0x00187 access_mode RW88 field DFON 0x8089 field DFPEXP 0x4090 field FAST20 0x2091 field CLRSTCNT 0x1092 field SPIOEN 0x0893 field SCAMEN 0x0494 field CLRCHN 0x0295}96 97/*98 * SCSI Transfer Control 1 Register (pp. 3-14,15).99 * Controls the SCSI module data path.100 */101register SXFRCTL1 {102 address 0x002103 access_mode RW104 field BITBUCKET 0x80105 field SWRAPEN 0x40106 field ENSPCHK 0x20107 mask STIMESEL 0x18108 field ENSTIMER 0x04109 field ACTNEGEN 0x02110 field STPWEN 0x01 /* Powered Termination */111 dont_generate_debug_code112}113 114/*115 * SCSI Control Signal Read Register (p. 3-15).116 * Reads the actual state of the SCSI bus pins117 */118register SCSISIGI {119 address 0x003120 access_mode RO121 field CDI 0x80122 field IOI 0x40123 field MSGI 0x20124 field ATNI 0x10125 field SELI 0x08126 field BSYI 0x04127 field REQI 0x02128 field ACKI 0x01129/*130 * Possible phases in SCSISIGI131 */132 mask PHASE_MASK CDI|IOI|MSGI133 mask P_DATAOUT 0x00134 mask P_DATAIN IOI135 mask P_DATAOUT_DT P_DATAOUT|MSGI136 mask P_DATAIN_DT P_DATAIN|MSGI137 mask P_COMMAND CDI138 mask P_MESGOUT CDI|MSGI139 mask P_STATUS CDI|IOI140 mask P_MESGIN CDI|IOI|MSGI141}142 143/*144 * SCSI Control Signal Write Register (p. 3-16).145 * Writing to this register modifies the control signals on the bus. Only146 * those signals that are allowed in the current mode (Initiator/Target) are147 * asserted.148 */149register SCSISIGO {150 address 0x003151 access_mode WO152 field CDO 0x80153 field IOO 0x40154 field MSGO 0x20155 field ATNO 0x10156 field SELO 0x08157 field BSYO 0x04158 field REQO 0x02159 field ACKO 0x01160/*161 * Possible phases to write into SCSISIG0162 */163 mask PHASE_MASK CDI|IOI|MSGI164 mask P_DATAOUT 0x00165 mask P_DATAIN IOI166 mask P_COMMAND CDI167 mask P_MESGOUT CDI|MSGI168 mask P_STATUS CDI|IOI169 mask P_MESGIN CDI|IOI|MSGI170 dont_generate_debug_code171}172 173/* 174 * SCSI Rate Control (p. 3-17).175 * Contents of this register determine the Synchronous SCSI data transfer176 * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the177 * SOFS (3:0) bits disables synchronous data transfers. Any offset value178 * greater than 0 enables synchronous transfers.179 */180register SCSIRATE {181 address 0x004182 access_mode RW183 field WIDEXFER 0x80 /* Wide transfer control */184 field ENABLE_CRC 0x40 /* CRC for D-Phases */185 field SINGLE_EDGE 0x10 /* Disable DT Transfers */186 mask SXFR 0x70 /* Sync transfer rate */187 mask SXFR_ULTRA2 0x0f /* Sync transfer rate */188 mask SOFS 0x0f /* Sync offset */189}190 191/*192 * SCSI ID (p. 3-18).193 * Contains the ID of the board and the current target on the194 * selected channel.195 */196register SCSIID {197 address 0x005198 access_mode RW199 mask TID 0xf0 /* Target ID mask */200 mask TWIN_TID 0x70201 field TWIN_CHNLB 0x80202 mask OID 0x0f /* Our ID mask */203 /*204 * SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)205 * The aic7890/91 allow an offset of up to 127 transfers in both wide206 * and narrow mode.207 */208 alias SCSIOFFSET209 mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */210 dont_generate_debug_code211}212 213/*214 * SCSI Latched Data (p. 3-19).215 * Read/Write latches used to transfer data on the SCSI bus during216 * Automatic or Manual PIO mode. SCSIDATH can be used for the217 * upper byte of a 16bit wide asynchronouse data phase transfer.218 */219register SCSIDATL {220 address 0x006221 access_mode RW222 dont_generate_debug_code223}224 225register SCSIDATH {226 address 0x007227 access_mode RW228}229 230/*231 * SCSI Transfer Count (pp. 3-19,20)232 * These registers count down the number of bytes transferred233 * across the SCSI bus. The counter is decremented only once234 * the data has been safely transferred. SDONE in SSTAT0 is235 * set when STCNT goes to 0236 */ 237register STCNT {238 address 0x008239 size 3240 access_mode RW241 dont_generate_debug_code242}243 244/* ALT_MODE registers (Ultra2 and Ultra160 chips) */245register SXFRCTL2 {246 address 0x013247 access_mode RW248 field AUTORSTDIS 0x10249 field CMDDMAEN 0x08250 mask ASYNC_SETUP 0x07251}252 253/* ALT_MODE register on Ultra160 chips */254register OPTIONMODE {255 address 0x008256 access_mode RW257 count 2258 field AUTORATEEN 0x80259 field AUTOACKEN 0x40260 field ATNMGMNTEN 0x20261 field BUSFREEREV 0x10262 field EXPPHASEDIS 0x08263 field SCSIDATL_IMGEN 0x04264 field AUTO_MSGOUT_DE 0x02265 field DIS_MSGIN_DUALEDGE 0x01266 mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE267 dont_generate_debug_code268}269 270/* ALT_MODE register on Ultra160 chips */271register TARGCRCCNT {272 address 0x00a273 size 2274 access_mode RW275 count 2276 dont_generate_debug_code277}278 279/*280 * Clear SCSI Interrupt 0 (p. 3-20)281 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.282 */283register CLRSINT0 {284 address 0x00b285 access_mode WO286 field CLRSELDO 0x40287 field CLRSELDI 0x20288 field CLRSELINGO 0x10289 field CLRSWRAP 0x08290 field CLRIOERR 0x08 /* Ultra2 Only */291 field CLRSPIORDY 0x02292 dont_generate_debug_code293}294 295/*296 * SCSI Status 0 (p. 3-21)297 * Contains one set of SCSI Interrupt codes298 * These are most likely of interest to the sequencer299 */300register SSTAT0 {301 address 0x00b302 access_mode RO303 field TARGET 0x80 /* Board acting as target */304 field SELDO 0x40 /* Selection Done */305 field SELDI 0x20 /* Board has been selected */306 field SELINGO 0x10 /* Selection In Progress */307 field SWRAP 0x08 /* 24bit counter wrap */308 field IOERR 0x08 /* LVD Tranceiver mode changed */309 field SDONE 0x04 /* STCNT = 0x000000 */310 field SPIORDY 0x02 /* SCSI PIO Ready */311 field DMADONE 0x01 /* DMA transfer completed */312}313 314/*315 * Clear SCSI Interrupt 1 (p. 3-23)316 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.317 */318register CLRSINT1 {319 address 0x00c320 access_mode WO321 field CLRSELTIMEO 0x80322 field CLRATNO 0x40323 field CLRSCSIRSTI 0x20324 field CLRBUSFREE 0x08325 field CLRSCSIPERR 0x04326 field CLRPHASECHG 0x02327 field CLRREQINIT 0x01328 dont_generate_debug_code329}330 331/*332 * SCSI Status 1 (p. 3-24)333 */334register SSTAT1 {335 address 0x00c336 access_mode RO337 field SELTO 0x80338 field ATNTARG 0x40339 field SCSIRSTI 0x20340 field PHASEMIS 0x10341 field BUSFREE 0x08342 field SCSIPERR 0x04343 field PHASECHG 0x02344 field REQINIT 0x01345}346 347/*348 * SCSI Status 2 (pp. 3-25,26)349 */350register SSTAT2 {351 address 0x00d352 access_mode RO353 field OVERRUN 0x80354 field SHVALID 0x40 /* Shadow Layer non-zero */355 field EXP_ACTIVE 0x10 /* SCSI Expander Active */356 field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */357 field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */358 field CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */359 field DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */360 mask SFCNT 0x1f361}362 363/*364 * SCSI Status 3 (p. 3-26)365 */366register SSTAT3 {367 address 0x00e368 access_mode RO369 count 2370 mask SCSICNT 0xf0371 mask OFFCNT 0x0f372 mask U2OFFCNT 0x7f373}374 375/*376 * SCSI ID for the aic7890/91 chips377 */378register SCSIID_ULTRA2 {379 address 0x00f380 access_mode RW381 mask TID 0xf0 /* Target ID mask */382 mask OID 0x0f /* Our ID mask */383 dont_generate_debug_code384}385 386/*387 * SCSI Interrupt Mode 1 (p. 3-28)388 * Setting any bit will enable the corresponding function389 * in SIMODE0 to interrupt via the IRQ pin.390 */391register SIMODE0 {392 address 0x010393 access_mode RW394 count 2395 field ENSELDO 0x40396 field ENSELDI 0x20397 field ENSELINGO 0x10398 field ENSWRAP 0x08399 field ENIOERR 0x08 /* LVD Tranceiver mode changes */400 field ENSDONE 0x04401 field ENSPIORDY 0x02402 field ENDMADONE 0x01403}404 405/*406 * SCSI Interrupt Mode 1 (pp. 3-28,29)407 * Setting any bit will enable the corresponding function408 * in SIMODE1 to interrupt via the IRQ pin.409 */410register SIMODE1 {411 address 0x011412 access_mode RW413 field ENSELTIMO 0x80414 field ENATNTARG 0x40415 field ENSCSIRST 0x20416 field ENPHASEMIS 0x10417 field ENBUSFREE 0x08418 field ENSCSIPERR 0x04419 field ENPHASECHG 0x02420 field ENREQINIT 0x01421}422 423/*424 * SCSI Data Bus (High) (p. 3-29)425 * This register reads data on the SCSI Data bus directly.426 */427register SCSIBUSL {428 address 0x012429 access_mode RW430}431 432register SCSIBUSH {433 address 0x013434 access_mode RW435}436 437/*438 * SCSI/Host Address (p. 3-30)439 * These registers hold the host address for the byte about to be440 * transferred on the SCSI bus. They are counted up in the same441 * manner as STCNT is counted down. SHADDR should always be used442 * to determine the address of the last byte transferred since HADDR443 * can be skewed by write ahead.444 */445register SHADDR {446 address 0x014447 size 4448 access_mode RO449 dont_generate_debug_code450}451 452/*453 * Selection Timeout Timer (p. 3-30)454 */455register SELTIMER {456 address 0x018457 access_mode RW458 count 1459 field STAGE6 0x20460 field STAGE5 0x10461 field STAGE4 0x08462 field STAGE3 0x04463 field STAGE2 0x02464 field STAGE1 0x01465 alias TARGIDIN466 dont_generate_debug_code467}468 469/*470 * Selection/Reselection ID (p. 3-31)471 * Upper four bits are the device id. The ONEBIT is set when the re/selecting472 * device did not set its own ID.473 */474register SELID {475 address 0x019476 access_mode RW477 mask SELID_MASK 0xf0478 field ONEBIT 0x08479 dont_generate_debug_code480}481 482register SCAMCTL {483 address 0x01a484 access_mode RW485 field ENSCAMSELO 0x80486 field CLRSCAMSELID 0x40487 field ALTSTIM 0x20488 field DFLTTID 0x10489 mask SCAMLVL 0x03490}491 492/*493 * Target Mode Selecting in ID bitmask (aic7890/91/96/97)494 */495register TARGID {496 address 0x01b497 size 2498 access_mode RW499 count 14500 dont_generate_debug_code501}502 503/*504 * Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)505 * Indicates if external logic has been attached to the chip to506 * perform the tasks of accessing a serial eeprom, testing termination507 * strength, and performing cable detection. On the aic7860, most of508 * these features are handled on chip, but on the aic7855 an attached509 * aic3800 does the grunt work.510 */511register SPIOCAP {512 address 0x01b513 access_mode RW514 count 10515 field SOFT1 0x80516 field SOFT0 0x40517 field SOFTCMDEN 0x20 518 field EXT_BRDCTL 0x10 /* External Board control */519 field SEEPROM 0x08 /* External serial eeprom logic */520 field EEPROM 0x04 /* Writable external BIOS ROM */521 field ROM 0x02 /* Logic for accessing external ROM */522 field SSPIOCPS 0x01 /* Termination and cable detection */523 dont_generate_debug_code524}525 526register BRDCTL {527 address 0x01d528 count 11529 field BRDDAT7 0x80530 field BRDDAT6 0x40531 field BRDDAT5 0x20532 field BRDSTB 0x10533 field BRDCS 0x08534 field BRDRW 0x04535 field BRDCTL1 0x02536 field BRDCTL0 0x01537 /* 7890 Definitions */538 field BRDDAT4 0x10539 field BRDDAT3 0x08540 field BRDDAT2 0x04541 field BRDRW_ULTRA2 0x02542 field BRDSTB_ULTRA2 0x01543 dont_generate_debug_code544}545 546/*547 * Serial EEPROM Control (p. 4-92 in 7870 Databook)548 * Controls the reading and writing of an external serial 1-bit549 * EEPROM Device. In order to access the serial EEPROM, you must550 * first set the SEEMS bit that generates a request to the memory551 * port for access to the serial EEPROM device. When the memory552 * port is not busy servicing another request, it reconfigures553 * to allow access to the serial EEPROM. When this happens, SEERDY554 * gets set high to verify that the memory port access has been555 * granted. 556 *557 * After successful arbitration for the memory port, the SEECS bit of 558 * the SEECTL register is connected to the chip select. The SEECK, 559 * SEEDO, and SEEDI are connected to the clock, data out, and data in 560 * lines respectively. The SEERDY bit of SEECTL is useful in that it 561 * gives us an 800 nsec timer. After a write to the SEECTL register, 562 * the SEERDY goes high 800 nsec later. The one exception to this is 563 * when we first request access to the memory port. The SEERDY goes 564 * high to signify that access has been granted and, for this case, has 565 * no implied timing.566 *567 * See 93cx6.c for detailed information on the protocol necessary to 568 * read the serial EEPROM.569 */570register SEECTL {571 address 0x01e572 count 11573 field EXTARBACK 0x80574 field EXTARBREQ 0x40575 field SEEMS 0x20576 field SEERDY 0x10577 field SEECS 0x08578 field SEECK 0x04579 field SEEDO 0x02580 field SEEDI 0x01581 dont_generate_debug_code582}583/*584 * SCSI Block Control (p. 3-32)585 * Controls Bus type and channel selection. In a twin channel configuration586 * addresses 0x00-0x1e are gated to the appropriate channel based on this587 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices588 * on a wide bus.589 */590register SBLKCTL {591 address 0x01f592 access_mode RW593 field DIAGLEDEN 0x80 /* Aic78X0 only */594 field DIAGLEDON 0x40 /* Aic78X0 only */595 field AUTOFLUSHDIS 0x20596 field SELBUSB 0x08597 field ENAB40 0x08 /* LVD transceiver active */598 field ENAB20 0x04 /* SE/HVD transceiver active */599 field SELWIDE 0x02600 field XCVR 0x01 /* External transceiver active */601}602 603/*604 * Sequencer Control (p. 3-33)605 * Error detection mode and speed configuration606 */607register SEQCTL {608 address 0x060609 access_mode RW610 count 15611 field PERRORDIS 0x80612 field PAUSEDIS 0x40613 field FAILDIS 0x20614 field FASTMODE 0x10615 field BRKADRINTEN 0x08616 field STEP 0x04617 field SEQRESET 0x02618 field LOADRAM 0x01619}620 621/*622 * Sequencer RAM Data (p. 3-34)623 * Single byte window into the Scratch Ram area starting at the address624 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write625 * four bytes in succession. The SEQADDRs will increment after the most626 * significant byte is written627 */628register SEQRAM {629 address 0x061630 access_mode RW631 count 2632 dont_generate_debug_code633}634 635/*636 * Sequencer Address Registers (p. 3-35)637 * Only the first bit of SEQADDR1 holds addressing information638 */639register SEQADDR0 {640 address 0x062641 access_mode RW642 dont_generate_debug_code643}644 645register SEQADDR1 {646 address 0x063647 access_mode RW648 count 8649 mask SEQADDR1_MASK 0x01650 dont_generate_debug_code651}652 653/*654 * Accumulator655 * We cheat by passing arguments in the Accumulator up to the kernel driver656 */657register ACCUM {658 address 0x064659 access_mode RW660 accumulator661 dont_generate_debug_code662}663 664register SINDEX {665 address 0x065666 access_mode RW667 sindex668 dont_generate_debug_code669}670 671register DINDEX {672 address 0x066673 access_mode RW674 dont_generate_debug_code675}676 677register ALLONES {678 address 0x069679 access_mode RO680 allones681 dont_generate_debug_code682}683 684register ALLZEROS {685 address 0x06a686 access_mode RO687 allzeros688 dont_generate_debug_code689}690 691register NONE {692 address 0x06a693 access_mode WO694 none695 dont_generate_debug_code696}697 698register FLAGS {699 address 0x06b700 access_mode RO701 count 18702 field ZERO 0x02703 field CARRY 0x01704 dont_generate_debug_code705}706 707register SINDIR {708 address 0x06c709 access_mode RO710 dont_generate_debug_code711}712 713register DINDIR {714 address 0x06d715 access_mode WO716 dont_generate_debug_code717}718 719register FUNCTION1 {720 address 0x06e721 access_mode RW722}723 724register STACK {725 address 0x06f726 access_mode RO727 count 5728 dont_generate_debug_code729}730 731const STACK_SIZE 4732 733/*734 * Board Control (p. 3-43)735 */736register BCTL {737 address 0x084738 access_mode RW739 field ACE 0x08740 field ENABLE 0x01741}742 743/*744 * On the aic78X0 chips, Board Control is replaced by the DSCommand745 * register (p. 4-64)746 */747register DSCOMMAND0 {748 address 0x084749 access_mode RW750 count 7751 field CACHETHEN 0x80 /* Cache Threshold enable */752 field DPARCKEN 0x40 /* Data Parity Check Enable */753 field MPARCKEN 0x20 /* Memory Parity Check Enable */754 field EXTREQLCK 0x10 /* External Request Lock */755 /* aic7890/91/96/97 only */756 field INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */757 field RAMPS 0x04 /* External SCB RAM Present */758 field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */759 field CIOPARCKEN 0x01 /* Internal bus parity error enable */760 dont_generate_debug_code761}762 763register DSCOMMAND1 {764 address 0x085765 access_mode RW766 mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */767 field HADDLDSEL1 0x02 /* Host Address Load Select Bits */768 field HADDLDSEL0 0x01769 dont_generate_debug_code770}771 772/*773 * Bus On/Off Time (p. 3-44) aic7770 only774 */775register BUSTIME {776 address 0x085777 access_mode RW778 count 2779 mask BOFF 0xf0780 mask BON 0x0f781 dont_generate_debug_code782}783 784/*785 * Bus Speed (p. 3-45) aic7770 only786 */787register BUSSPD {788 address 0x086789 access_mode RW790 count 2791 mask DFTHRSH 0xc0792 mask STBOFF 0x38793 mask STBON 0x07794 mask DFTHRSH_100 0xc0795 mask DFTHRSH_75 0x80796 dont_generate_debug_code797}798 799/* aic7850/55/60/70/80/95 only */800register DSPCISTATUS {801 address 0x086802 count 4803 mask DFTHRSH_100 0xc0804 dont_generate_debug_code805}806 807/* aic7890/91/96/97 only */808register HS_MAILBOX {809 address 0x086810 mask HOST_MAILBOX 0xF0811 mask SEQ_MAILBOX 0x0F812 mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */813 dont_generate_debug_code814}815 816const HOST_MAILBOX_SHIFT 4817const SEQ_MAILBOX_SHIFT 0818 819/*820 * Host Control (p. 3-47) R/W821 * Overall host control of the device.822 */823register HCNTRL {824 address 0x087825 access_mode RW826 count 14827 field POWRDN 0x40828 field SWINT 0x10829 field IRQMS 0x08830 field PAUSE 0x04831 field INTEN 0x02832 field CHIPRST 0x01833 field CHIPRSTACK 0x01834 dont_generate_debug_code835}836 837/*838 * Host Address (p. 3-48)839 * This register contains the address of the byte about840 * to be transferred across the host bus.841 */842register HADDR {843 address 0x088844 size 4845 access_mode RW846 dont_generate_debug_code847}848 849register HCNT {850 address 0x08c851 size 3852 access_mode RW853 dont_generate_debug_code854}855 856/*857 * SCB Pointer (p. 3-49)858 * Gate one of the SCBs into the SCBARRAY window.859 */860register SCBPTR {861 address 0x090862 access_mode RW863 dont_generate_debug_code864}865 866/*867 * Interrupt Status (p. 3-50)868 * Status for system interrupts869 */870register INTSTAT {871 address 0x091872 access_mode RW873 field BRKADRINT 0x08874 field SCSIINT 0x04875 field CMDCMPLT 0x02876 field SEQINT 0x01877 mask BAD_PHASE SEQINT /* unknown scsi bus phase */878 mask SEND_REJECT 0x10|SEQINT /* sending a message reject */879 mask PROTO_VIOLATION 0x20|SEQINT /* SCSI protocol violation */ 880 mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */881 mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */882 mask PDATA_REINIT 0x50|SEQINT /*883 * Returned to data phase884 * that requires data885 * transfer pointers to be886 * recalculated from the887 * transfer residual.888 */889 mask HOST_MSG_LOOP 0x60|SEQINT /*890 * The bus is ready for the891 * host to perform another892 * message transaction. This893 * mechanism is used for things894 * like sync/wide negotiation895 * that require a kernel based896 * message state engine.897 */898 mask BAD_STATUS 0x70|SEQINT /* Bad status from target */899 mask PERR_DETECTED 0x80|SEQINT /*900 * Either the phase_lock901 * or inb_next routine has902 * noticed a parity error.903 */904 mask DATA_OVERRUN 0x90|SEQINT /*905 * Target attempted to write906 * beyond the bounds of its907 * command.908 */909 mask MKMSG_FAILED 0xa0|SEQINT /*910 * Target completed command911 * without honoring our ATN912 * request to issue a message. 913 */914 mask MISSED_BUSFREE 0xb0|SEQINT /*915 * The sequencer never saw916 * the bus go free after917 * either a command complete918 * or disconnect message.919 */920 mask SCB_MISMATCH 0xc0|SEQINT /*921 * Downloaded SCB's tag does922 * not match the entry we923 * intended to download.924 */925 mask NO_FREE_SCB 0xd0|SEQINT /*926 * get_free_or_disc_scb failed.927 */928 mask OUT_OF_RANGE 0xe0|SEQINT929 930 mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */931 mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)932 dont_generate_debug_code933}934 935/*936 * Hard Error (p. 3-53)937 * Reporting of catastrophic errors. You usually cannot recover from938 * these without a full board reset.939 */940register ERROR {941 address 0x092942 access_mode RO943 count 26944 field CIOPARERR 0x80 /* Ultra2 only */945 field PCIERRSTAT 0x40 /* PCI only */946 field MPARERR 0x20 /* PCI only */947 field DPARERR 0x10 /* PCI only */948 field SQPARERR 0x08949 field ILLOPCODE 0x04950 field ILLSADDR 0x02951 field ILLHADDR 0x01952}953 954/*955 * Clear Interrupt Status (p. 3-52)956 */957register CLRINT {958 address 0x092959 access_mode WO960 count 24961 field CLRPARERR 0x10 /* PCI only */962 field CLRBRKADRINT 0x08963 field CLRSCSIINT 0x04964 field CLRCMDINT 0x02965 field CLRSEQINT 0x01966 dont_generate_debug_code967}968 969register DFCNTRL {970 address 0x093971 access_mode RW972 field PRELOADEN 0x80 /* aic7890 only */973 field WIDEODD 0x40974 field SCSIEN 0x20975 field SDMAEN 0x10976 field SDMAENACK 0x10977 field HDMAEN 0x08978 field HDMAENACK 0x08979 field DIRECTION 0x04980 field FIFOFLUSH 0x02981 field FIFORESET 0x01982}983 984register DFSTATUS {985 address 0x094986 access_mode RO987 field PRELOAD_AVAIL 0x80988 field DFCACHETH 0x40989 field FIFOQWDEMP 0x20990 field MREQPEND 0x10991 field HDONE 0x08992 field DFTHRESH 0x04993 field FIFOFULL 0x02994 field FIFOEMP 0x01995}996 997register DFWADDR {998 address 0x95999 access_mode RW1000 dont_generate_debug_code1001}1002 1003register DFRADDR {1004 address 0x971005 access_mode RW1006}1007 1008register DFDAT {1009 address 0x0991010 access_mode RW1011 dont_generate_debug_code1012}1013 1014/*1015 * SCB Auto Increment (p. 3-59)1016 * Byte offset into the SCB Array and an optional bit to allow auto1017 * incrementing of the address during download and upload operations1018 */1019register SCBCNT {1020 address 0x09a1021 access_mode RW1022 count 11023 field SCBAUTO 0x801024 mask SCBCNT_MASK 0x1f1025 dont_generate_debug_code1026}1027 1028/*1029 * Queue In FIFO (p. 3-60)1030 * Input queue for queued SCBs (commands that the seqencer has yet to start)1031 */1032register QINFIFO {1033 address 0x09b1034 access_mode RW1035 count 121036 dont_generate_debug_code1037}1038 1039/*1040 * Queue In Count (p. 3-60)1041 * Number of queued SCBs1042 */1043register QINCNT {1044 address 0x09c1045 access_mode RO1046}1047 1048/*1049 * Queue Out FIFO (p. 3-61)1050 * Queue of SCBs that have completed and await the host1051 */1052register QOUTFIFO {1053 address 0x09d1054 access_mode WO1055 count 71056 dont_generate_debug_code1057}1058 1059register CRCCONTROL1 {1060 address 0x09d1061 access_mode RW1062 count 31063 field CRCONSEEN 0x801064 field CRCVALCHKEN 0x401065 field CRCENDCHKEN 0x201066 field CRCREQCHKEN 0x101067 field TARGCRCENDEN 0x081068 field TARGCRCCNTEN 0x041069 dont_generate_debug_code1070}1071 1072 1073/*1074 * Queue Out Count (p. 3-61)1075 * Number of queued SCBs in the Out FIFO1076 */1077register QOUTCNT {1078 address 0x09e1079 access_mode RO1080}1081 1082register SCSIPHASE {1083 address 0x09e1084 access_mode RO1085 field STATUS_PHASE 0x201086 field COMMAND_PHASE 0x101087 field MSG_IN_PHASE 0x081088 field MSG_OUT_PHASE 0x041089 field DATA_IN_PHASE 0x021090 field DATA_OUT_PHASE 0x011091 mask DATA_PHASE_MASK 0x031092}1093 1094/*1095 * Special Function1096 */1097register SFUNCT {1098 address 0x09f1099 access_mode RW1100 count 41101 field ALT_MODE 0x801102 dont_generate_debug_code1103}1104 1105/*1106 * SCB Definition (p. 5-4)1107 */1108scb {1109 address 0x0a01110 size 641111 1112 SCB_CDB_PTR {1113 size 41114 alias SCB_RESIDUAL_DATACNT1115 alias SCB_CDB_STORE1116 dont_generate_debug_code1117 }1118 SCB_RESIDUAL_SGPTR {1119 size 41120 dont_generate_debug_code1121 }1122 SCB_SCSI_STATUS {1123 size 11124 dont_generate_debug_code1125 }1126 SCB_TARGET_PHASES {1127 size 11128 dont_generate_debug_code1129 }1130 SCB_TARGET_DATA_DIR {1131 size 11132 dont_generate_debug_code1133 }1134 SCB_TARGET_ITAG {1135 size 11136 dont_generate_debug_code1137 }1138 SCB_DATAPTR {1139 size 41140 dont_generate_debug_code1141 }1142 SCB_DATACNT {1143 /*1144 * The last byte is really the high address bits for1145 * the data address.1146 */1147 size 41148 field SG_LAST_SEG 0x80 /* In the fourth byte */1149 mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */1150 dont_generate_debug_code1151 }1152 SCB_SGPTR {1153 size 41154 field SG_RESID_VALID 0x04 /* In the first byte */1155 field SG_FULL_RESID 0x02 /* In the first byte */1156 field SG_LIST_NULL 0x01 /* In the first byte */1157 dont_generate_debug_code1158 }1159 SCB_CONTROL {1160 size 11161 field TARGET_SCB 0x801162 field STATUS_RCVD 0x801163 field DISCENB 0x401164 field TAG_ENB 0x201165 field MK_MESSAGE 0x101166 field ULTRAENB 0x081167 field DISCONNECTED 0x041168 mask SCB_TAG_TYPE 0x031169 }1170 SCB_SCSIID {1171 size 11172 field TWIN_CHNLB 0x801173 mask TWIN_TID 0x701174 mask TID 0xf01175 mask OID 0x0f1176 }1177 SCB_LUN {1178 field SCB_XFERLEN_ODD 0x801179 mask LID 0x3f1180 size 11181 }1182 SCB_TAG {1183 size 11184 }1185 SCB_CDB_LEN {1186 size 11187 dont_generate_debug_code1188 }1189 SCB_SCSIRATE {1190 size 11191 dont_generate_debug_code1192 }1193 SCB_SCSIOFFSET {1194 size 11195 count 11196 dont_generate_debug_code1197 }1198 SCB_NEXT {1199 size 11200 dont_generate_debug_code1201 }1202 SCB_64_SPARE {1203 size 161204 }1205 SCB_64_BTT {1206 size 161207 dont_generate_debug_code1208 }1209}1210 1211const SCB_UPLOAD_SIZE 321212const SCB_DOWNLOAD_SIZE 321213const SCB_DOWNLOAD_SIZE_64 481214 1215const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */1216 1217/* --------------------- AHA-2840-only definitions -------------------- */1218 1219register SEECTL_2840 {1220 address 0x0c01221 access_mode RW1222 count 21223 field CS_2840 0x041224 field CK_2840 0x021225 field DO_2840 0x011226 dont_generate_debug_code1227}1228 1229register STATUS_2840 {1230 address 0x0c11231 access_mode RW1232 count 41233 field EEPROM_TF 0x801234 mask BIOS_SEL 0x601235 mask ADSEL 0x1e1236 field DI_2840 0x011237 dont_generate_debug_code1238}1239 1240/* --------------------- AIC-7870-only definitions -------------------- */1241 1242register CCHADDR {1243 address 0x0E01244 size 81245 dont_generate_debug_code1246}1247 1248register CCHCNT {1249 address 0x0E81250 dont_generate_debug_code1251}1252 1253register CCSGRAM {1254 address 0x0E91255 dont_generate_debug_code1256}1257 1258register CCSGADDR {1259 address 0x0EA1260 dont_generate_debug_code1261}1262 1263register CCSGCTL {1264 address 0x0EB1265 field CCSGDONE 0x801266 field CCSGEN 0x081267 field SG_FETCH_NEEDED 0x02 /* Bit used for software state */1268 field CCSGRESET 0x011269 dont_generate_debug_code1270}1271 1272register CCSCBCNT {1273 address 0xEF1274 count 11275 dont_generate_debug_code1276}1277 1278register CCSCBCTL {1279 address 0x0EE1280 field CCSCBDONE 0x801281 field ARRDONE 0x40 /* SCB Array prefetch done */1282 field CCARREN 0x101283 field CCSCBEN 0x081284 field CCSCBDIR 0x041285 field CCSCBRESET 0x011286 dont_generate_debug_code1287}1288 1289register CCSCBADDR {1290 address 0x0ED1291 dont_generate_debug_code1292}1293 1294register CCSCBRAM {1295 address 0xEC1296 dont_generate_debug_code1297}1298 1299/*1300 * SCB bank address (7895/7896/97 only)1301 */1302register SCBBADDR {1303 address 0x0F01304 access_mode RW1305 count 31306 dont_generate_debug_code1307}1308 1309register CCSCBPTR {1310 address 0x0F11311 dont_generate_debug_code1312}1313 1314register HNSCB_QOFF {1315 address 0x0F41316 count 41317 dont_generate_debug_code1318}1319 1320register SNSCB_QOFF {1321 address 0x0F61322 dont_generate_debug_code1323}1324 1325register SDSCB_QOFF {1326 address 0x0F81327 dont_generate_debug_code1328}1329 1330register QOFF_CTLSTA {1331 address 0x0FA1332 field SCB_AVAIL 0x401333 field SNSCB_ROLLOVER 0x201334 field SDSCB_ROLLOVER 0x101335 mask SCB_QSIZE 0x071336 mask SCB_QSIZE_256 0x061337 dont_generate_debug_code1338}1339 1340register DFF_THRSH {1341 address 0x0FB1342 mask WR_DFTHRSH 0x701343 mask RD_DFTHRSH 0x071344 mask RD_DFTHRSH_MIN 0x001345 mask RD_DFTHRSH_25 0x011346 mask RD_DFTHRSH_50 0x021347 mask RD_DFTHRSH_63 0x031348 mask RD_DFTHRSH_75 0x041349 mask RD_DFTHRSH_85 0x051350 mask RD_DFTHRSH_90 0x061351 mask RD_DFTHRSH_MAX 0x071352 mask WR_DFTHRSH_MIN 0x001353 mask WR_DFTHRSH_25 0x101354 mask WR_DFTHRSH_50 0x201355 mask WR_DFTHRSH_63 0x301356 mask WR_DFTHRSH_75 0x401357 mask WR_DFTHRSH_85 0x501358 mask WR_DFTHRSH_90 0x601359 mask WR_DFTHRSH_MAX 0x701360 count 41361 dont_generate_debug_code1362}1363 1364register SG_CACHE_PRE {1365 access_mode WO1366 address 0x0fc1367 mask SG_ADDR_MASK 0xf81368 field LAST_SEG 0x021369 field LAST_SEG_DONE 0x011370 dont_generate_debug_code1371}1372 1373register SG_CACHE_SHADOW {1374 access_mode RO1375 address 0x0fc1376 mask SG_ADDR_MASK 0xf81377 field LAST_SEG 0x021378 field LAST_SEG_DONE 0x011379 dont_generate_debug_code1380}1381/* ---------------------- Scratch RAM Offsets ------------------------- */1382/* These offsets are either to values that are initialized by the board's1383 * BIOS or are specified by the sequencer code.1384 *1385 * The host adapter card (at least the BIOS) uses 20-2f for SCSI1386 * device information, 32-33 and 5a-5f as well. As it turns out, the1387 * BIOS trashes 20-2f, writing the synchronous negotiation results1388 * on top of the BIOS values, so we re-use those for our per-target1389 * scratchspace (actually a value that can be copied directly into1390 * SCSIRATE). The kernel driver will enable synchronous negotiation1391 * for all targets that have a value other than 0 in the lower four1392 * bits of the target scratch space. This should work regardless of1393 * whether the bios has been installed.1394 */1395 1396scratch_ram {1397 address 0x0201398 size 581399 1400 /*1401 * 1 byte per target starting at this address for configuration values1402 */1403 BUSY_TARGETS {1404 alias TARG_SCSIRATE1405 size 161406 dont_generate_debug_code1407 }1408 /*1409 * Bit vector of targets that have ULTRA enabled as set by1410 * the BIOS. The Sequencer relies on a per-SCB field to1411 * control whether to enable Ultra transfers or not. During1412 * initialization, we read this field and reuse it for 21413 * entries in the busy target table.1414 */1415 ULTRA_ENB {1416 alias CMDSIZE_TABLE1417 size 21418 count 21419 dont_generate_debug_code1420 }1421 /*1422 * Bit vector of targets that have disconnection disabled as set by1423 * the BIOS. The Sequencer relies in a per-SCB field to control the1424 * disconnect priveldge. During initialization, we read this field1425 * and reuse it for 2 entries in the busy target table.1426 */1427 DISC_DSB {1428 size 21429 count 61430 dont_generate_debug_code1431 }1432 CMDSIZE_TABLE_TAIL {1433 size 41434 }1435 /*1436 * Partial transfer past cacheline end to be1437 * transferred using an extra S/G.1438 */1439 MWI_RESIDUAL {1440 size 11441 dont_generate_debug_code1442 }1443 /*1444 * SCBID of the next SCB to be started by the controller.1445 */1446 NEXT_QUEUED_SCB {1447 size 11448 dont_generate_debug_code1449 }1450 /*1451 * Single byte buffer used to designate the type or message1452 * to send to a target.1453 */1454 MSG_OUT {1455 size 11456 dont_generate_debug_code1457 }1458 /* Parameters for DMA Logic */1459 DMAPARAMS {1460 size 11461 count 121462 field PRELOADEN 0x801463 field WIDEODD 0x401464 field SCSIEN 0x201465 field SDMAEN 0x101466 field SDMAENACK 0x101467 field HDMAEN 0x081468 field HDMAENACK 0x081469 field DIRECTION 0x04 /* Set indicates PCI->SCSI */1470 field FIFOFLUSH 0x021471 field FIFORESET 0x011472 dont_generate_debug_code1473 }1474 SEQ_FLAGS {1475 size 11476 field NOT_IDENTIFIED 0x801477 field NO_CDB_SENT 0x401478 field TARGET_CMD_IS_TAGGED 0x401479 field DPHASE 0x201480 /* Target flags */1481 field TARG_CMD_PENDING 0x101482 field CMDPHASE_PENDING 0x081483 field DPHASE_PENDING 0x041484 field SPHASE_PENDING 0x021485 field NO_DISCONNECT 0x011486 }1487 /*1488 * Temporary storage for the1489 * target/channel/lun of a1490 * reconnecting target1491 */1492 SAVED_SCSIID {1493 size 11494 dont_generate_debug_code1495 }1496 SAVED_LUN {1497 size 11498 dont_generate_debug_code1499 }1500 /*1501 * The last bus phase as seen by the sequencer. 1502 */1503 LASTPHASE {1504 size 11505 field CDI 0x801506 field IOI 0x401507 field MSGI 0x201508 mask PHASE_MASK CDI|IOI|MSGI1509 mask P_DATAOUT 0x001510 mask P_DATAIN IOI1511 mask P_COMMAND CDI1512 mask P_MESGOUT CDI|MSGI1513 mask P_STATUS CDI|IOI1514 mask P_MESGIN CDI|IOI|MSGI1515 mask P_BUSFREE 0x011516 }1517 /*1518 * head of list of SCBs awaiting1519 * selection1520 */1521 WAITING_SCBH {1522 size 11523 dont_generate_debug_code1524 }1525 /*1526 * head of list of SCBs that are1527 * disconnected. Used for SCB1528 * paging.1529 */1530 DISCONNECTED_SCBH {1531 size 11532 dont_generate_debug_code1533 }1534 /*1535 * head of list of SCBs that are1536 * not in use. Used for SCB paging.1537 */1538 FREE_SCBH {1539 size 11540 dont_generate_debug_code1541 }1542 /*1543 * head of list of SCBs that have1544 * completed but have not been1545 * put into the qoutfifo.1546 */1547 COMPLETE_SCBH {1548 size 11549 }1550 /*1551 * Address of the hardware scb array in the host.1552 */1553 HSCB_ADDR {1554 size 41555 dont_generate_debug_code1556 }1557 /*1558 * Base address of our shared data with the kernel driver in host1559 * memory. This includes the qoutfifo and target mode1560 * incoming command queue.1561 */1562 SHARED_DATA_ADDR {1563 size 41564 dont_generate_debug_code1565 }1566 KERNEL_QINPOS {1567 size 11568 dont_generate_debug_code1569 }1570 QINPOS {1571 size 11572 dont_generate_debug_code1573 }1574 QOUTPOS {1575 size 11576 dont_generate_debug_code1577 }1578 /*1579 * Kernel and sequencer offsets into the queue of1580 * incoming target mode command descriptors. The1581 * queue is full when the KERNEL_TQINPOS == TQINPOS.1582 */1583 KERNEL_TQINPOS {1584 size 11585 dont_generate_debug_code1586 }1587 TQINPOS {1588 size 11589 dont_generate_debug_code1590 }1591 ARG_1 {1592 size 11593 count 11594 mask SEND_MSG 0x801595 mask SEND_SENSE 0x401596 mask SEND_REJ 0x201597 mask MSGOUT_PHASEMIS 0x101598 mask EXIT_MSG_LOOP 0x081599 mask CONT_MSG_LOOP 0x041600 mask CONT_TARG_SESSION 0x021601 alias RETURN_11602 dont_generate_debug_code1603 }1604 ARG_2 {1605 size 11606 alias RETURN_21607 dont_generate_debug_code1608 }1609 1610 /*1611 * Snapshot of MSG_OUT taken after each message is sent.1612 */1613 LAST_MSG {1614 size 11615 alias TARG_IMMEDIATE_SCB1616 dont_generate_debug_code1617 }1618 1619 /*1620 * Sequences the kernel driver has okayed for us. This allows1621 * the driver to do things like prevent initiator or target1622 * operations.1623 */1624 SCSISEQ_TEMPLATE {1625 size 11626 field ENSELO 0x401627 field ENSELI 0x201628 field ENRSELI 0x101629 field ENAUTOATNO 0x081630 field ENAUTOATNI 0x041631 field ENAUTOATNP 0x021632 dont_generate_debug_code1633 }1634}1635 1636scratch_ram {1637 address 0x0561638 size 41639 /*1640 * These scratch ram locations are initialized by the 274X BIOS.1641 * We reuse them after capturing the BIOS settings during1642 * initialization.1643 */1644 1645 /*1646 * The initiator specified tag for this target mode transaction.1647 */1648 HA_274_BIOSGLOBAL {1649 size 11650 field HA_274_EXTENDED_TRANS 0x011651 alias INITIATOR_TAG1652 count 11653 dont_generate_debug_code1654 }1655 1656 SEQ_FLAGS2 {1657 size 11658 field SCB_DMA 0x011659 field TARGET_MSG_PENDING 0x021660 dont_generate_debug_code1661 }1662}1663 1664scratch_ram {1665 address 0x05a1666 size 61667 /*1668 * These are reserved registers in the card's scratch ram on the 2742.1669 * The EISA configuration chip is mapped here. On Rev E. of the1670 * aic7770, the sequencer can use this area for scratch, but the1671 * host cannot directly access these registers. On later chips, this1672 * area can be read and written by both the host and the sequencer.1673 * Even on later chips, many of these locations are initialized by1674 * the BIOS.1675 */1676 SCSICONF {1677 size 11678 count 121679 field TERM_ENB 0x801680 field RESET_SCSI 0x401681 field ENSPCHK 0x201682 mask HSCSIID 0x07 /* our SCSI ID */1683 mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */1684 dont_generate_debug_code1685 }1686 INTDEF {1687 address 0x05c1688 size 11689 count 11690 field EDGE_TRIG 0x801691 mask VECTOR 0x0f1692 dont_generate_debug_code1693 }1694 HOSTCONF {1695 address 0x05d1696 size 11697 count 11698 dont_generate_debug_code1699 }1700 HA_274_BIOSCTRL {1701 address 0x05f1702 size 11703 count 11704 mask BIOSMODE 0x301705 mask BIOSDISABLED 0x30 1706 field CHANNEL_B_PRIMARY 0x081707 dont_generate_debug_code1708 }1709}1710 1711scratch_ram {1712 address 0x0701713 size 161714 1715 /*1716 * Per target SCSI offset values for Ultra2 controllers.1717 */1718 TARG_OFFSET {1719 size 161720 count 11721 dont_generate_debug_code1722 }1723}1724 1725const TID_SHIFT 41726const SCB_LIST_NULL 0xff1727const TARGET_CMD_CMPLT 0xfe1728 1729const CCSGADDR_MAX 0x801730const CCSGRAM_MAXSEGS 161731 1732/* WDTR Message values */1733const BUS_8_BIT 0x001734const BUS_16_BIT 0x011735const BUS_32_BIT 0x021736 1737/* Offset maximums */1738const MAX_OFFSET_8BIT 0x0f1739const MAX_OFFSET_16BIT 0x081740const MAX_OFFSET_ULTRA2 0x7f1741const MAX_OFFSET 0x7f1742const HOST_MSG 0xff1743 1744/* Target mode command processing constants */1745const CMD_GROUP_CODE_SHIFT 0x051746 1747const STATUS_BUSY 0x081748const STATUS_QUEUE_FULL 0x281749const TARGET_DATA_IN 11750 1751/*1752 * Downloaded (kernel inserted) constants1753 */1754/* Offsets into the SCBID array where different data is stored */1755const QOUTFIFO_OFFSET download1756const QINFIFO_OFFSET download1757const CACHESIZE_MASK download1758const INVERTED_CACHESIZE_MASK download1759const SG_PREFETCH_CNT download1760const SG_PREFETCH_ALIGN_MASK download1761const SG_PREFETCH_ADDR_MASK download1762