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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * linux/drivers/acorn/scsi/acornscsi.h4 *5 * Copyright (C) 1997 Russell King6 *7 * Acorn SCSI driver8 */9#ifndef ACORNSCSI_H10#define ACORNSCSI_H11 12/* SBIC registers */13#define SBIC_OWNID 014#define OWNID_FS1 (1<<7)15#define OWNID_FS2 (1<<6)16#define OWNID_EHP (1<<4)17#define OWNID_EAF (1<<3)18 19#define SBIC_CTRL 120#define CTRL_DMAMODE (1<<7)21#define CTRL_DMADBAMODE (1<<6)22#define CTRL_DMABURST (1<<5)23#define CTRL_DMAPOLLED 024#define CTRL_HHP (1<<4)25#define CTRL_EDI (1<<3)26#define CTRL_IDI (1<<2)27#define CTRL_HA (1<<1)28#define CTRL_HSP (1<<0)29 30#define SBIC_TIMEOUT 231#define SBIC_TOTSECTS 332#define SBIC_TOTHEADS 433#define SBIC_TOTCYLH 534#define SBIC_TOTCYLL 635#define SBIC_LOGADDRH 736#define SBIC_LOGADDRM2 837#define SBIC_LOGADDRM1 938#define SBIC_LOGADDRL 1039#define SBIC_SECTORNUM 1140#define SBIC_HEADNUM 1241#define SBIC_CYLH 1342#define SBIC_CYLL 1443#define SBIC_TARGETLUN 1544#define TARGETLUN_TLV (1<<7)45#define TARGETLUN_DOK (1<<6)46 47#define SBIC_CMNDPHASE 1648#define SBIC_SYNCHTRANSFER 1749#define SYNCHTRANSFER_OF0 0x0050#define SYNCHTRANSFER_OF1 0x0151#define SYNCHTRANSFER_OF2 0x0252#define SYNCHTRANSFER_OF3 0x0353#define SYNCHTRANSFER_OF4 0x0454#define SYNCHTRANSFER_OF5 0x0555#define SYNCHTRANSFER_OF6 0x0656#define SYNCHTRANSFER_OF7 0x0757#define SYNCHTRANSFER_OF8 0x0858#define SYNCHTRANSFER_OF9 0x0959#define SYNCHTRANSFER_OF10 0x0A60#define SYNCHTRANSFER_OF11 0x0B61#define SYNCHTRANSFER_OF12 0x0C62#define SYNCHTRANSFER_8DBA 0x0063#define SYNCHTRANSFER_2DBA 0x2064#define SYNCHTRANSFER_3DBA 0x3065#define SYNCHTRANSFER_4DBA 0x4066#define SYNCHTRANSFER_5DBA 0x5067#define SYNCHTRANSFER_6DBA 0x6068#define SYNCHTRANSFER_7DBA 0x7069 70#define SBIC_TRANSCNTH 1871#define SBIC_TRANSCNTM 1972#define SBIC_TRANSCNTL 2073#define SBIC_DESTID 2174#define DESTID_SCC (1<<7)75#define DESTID_DPD (1<<6)76 77#define SBIC_SOURCEID 2278#define SOURCEID_ER (1<<7)79#define SOURCEID_ES (1<<6)80#define SOURCEID_DSP (1<<5)81#define SOURCEID_SIV (1<<4)82 83#define SBIC_SSR 2384#define SBIC_CMND 2485#define CMND_RESET 0x0086#define CMND_ABORT 0x0187#define CMND_ASSERTATN 0x0288#define CMND_NEGATEACK 0x0389#define CMND_DISCONNECT 0x0490#define CMND_RESELECT 0x0591#define CMND_SELWITHATN 0x0692#define CMND_SELECT 0x0793#define CMND_SELECTATNTRANSFER 0x0894#define CMND_SELECTTRANSFER 0x0995#define CMND_RESELECTRXDATA 0x0A96#define CMND_RESELECTTXDATA 0x0B97#define CMND_WAITFORSELRECV 0x0C98#define CMND_SENDSTATCMD 0x0D99#define CMND_SENDDISCONNECT 0x0E100#define CMND_SETIDI 0x0F101#define CMND_RECEIVECMD 0x10102#define CMND_RECEIVEDTA 0x11103#define CMND_RECEIVEMSG 0x12104#define CMND_RECEIVEUSP 0x13105#define CMND_SENDCMD 0x14106#define CMND_SENDDATA 0x15107#define CMND_SENDMSG 0x16108#define CMND_SENDUSP 0x17109#define CMND_TRANSLATEADDR 0x18110#define CMND_XFERINFO 0x20111#define CMND_SBT (1<<7)112 113#define SBIC_DATA 25114#define SBIC_ASR 26115#define ASR_INT (1<<7)116#define ASR_LCI (1<<6)117#define ASR_BSY (1<<5)118#define ASR_CIP (1<<4)119#define ASR_PE (1<<1)120#define ASR_DBR (1<<0)121 122/* DMAC registers */123#define DMAC_INIT 0x00124#define INIT_8BIT (1)125 126#define DMAC_CHANNEL 0x80127#define CHANNEL_0 0x00128#define CHANNEL_1 0x01129#define CHANNEL_2 0x02130#define CHANNEL_3 0x03131 132#define DMAC_TXCNTLO 0x01133#define DMAC_TXCNTHI 0x81134#define DMAC_TXADRLO 0x02135#define DMAC_TXADRMD 0x82136#define DMAC_TXADRHI 0x03137 138#define DMAC_DEVCON0 0x04139#define DEVCON0_AKL (1<<7)140#define DEVCON0_RQL (1<<6)141#define DEVCON0_EXW (1<<5)142#define DEVCON0_ROT (1<<4)143#define DEVCON0_CMP (1<<3)144#define DEVCON0_DDMA (1<<2)145#define DEVCON0_AHLD (1<<1)146#define DEVCON0_MTM (1<<0)147 148#define DMAC_DEVCON1 0x84149#define DEVCON1_WEV (1<<1)150#define DEVCON1_BHLD (1<<0)151 152#define DMAC_MODECON 0x05153#define MODECON_WOED 0x01154#define MODECON_VERIFY 0x00155#define MODECON_READ 0x04156#define MODECON_WRITE 0x08157#define MODECON_AUTOINIT 0x10158#define MODECON_ADDRDIR 0x20159#define MODECON_DEMAND 0x00160#define MODECON_SINGLE 0x40161#define MODECON_BLOCK 0x80162#define MODECON_CASCADE 0xC0163 164#define DMAC_STATUS 0x85165#define STATUS_TC0 (1<<0)166#define STATUS_RQ0 (1<<4)167 168#define DMAC_TEMPLO 0x06169#define DMAC_TEMPHI 0x86170#define DMAC_REQREG 0x07171#define DMAC_MASKREG 0x87172#define MASKREG_M0 0x01173#define MASKREG_M1 0x02174#define MASKREG_M2 0x04175#define MASKREG_M3 0x08176 177/* miscellaneous internal variables */178 179#define MASK_ON (MASKREG_M3|MASKREG_M2|MASKREG_M1|MASKREG_M0)180#define MASK_OFF (MASKREG_M3|MASKREG_M2|MASKREG_M1)181 182/*183 * SCSI driver phases184 */185typedef enum {186 PHASE_IDLE, /* we're not planning on doing anything */187 PHASE_CONNECTING, /* connecting to a target */188 PHASE_CONNECTED, /* connected to a target */189 PHASE_MSGOUT, /* message out to device */190 PHASE_RECONNECTED, /* reconnected */191 PHASE_COMMANDPAUSED, /* command partly sent */192 PHASE_COMMAND, /* command all sent */193 PHASE_DATAOUT, /* data out to device */194 PHASE_DATAIN, /* data in from device */195 PHASE_STATUSIN, /* status in from device */196 PHASE_MSGIN, /* message in from device */197 PHASE_DONE, /* finished */198 PHASE_ABORTED, /* aborted */199 PHASE_DISCONNECT, /* disconnecting */200} phase_t;201 202/*203 * After interrupt, what to do now204 */205typedef enum {206 INTR_IDLE, /* not expecting another IRQ */207 INTR_NEXT_COMMAND, /* start next command */208 INTR_PROCESSING, /* interrupt routine still processing */209} intr_ret_t;210 211/*212 * DMA direction213 */214typedef enum {215 DMA_OUT, /* DMA from memory to chip */216 DMA_IN /* DMA from chip to memory */217} dmadir_t;218 219/*220 * Synchronous transfer state221 */222typedef enum { /* Synchronous transfer state */223 SYNC_ASYNCHRONOUS, /* don't negotiate synchronous transfers*/224 SYNC_NEGOCIATE, /* start negotiation */225 SYNC_SENT_REQUEST, /* sent SDTR message */226 SYNC_COMPLETED, /* received SDTR reply */227} syncxfer_t;228 229/*230 * Command type231 */232typedef enum { /* command type */233 CMD_READ, /* READ_6, READ_10, READ_12 */234 CMD_WRITE, /* WRITE_6, WRITE_10, WRITE_12 */235 CMD_MISC, /* Others */236} cmdtype_t;237 238/*239 * Data phase direction240 */241typedef enum { /* Data direction */242 DATADIR_IN, /* Data in phase expected */243 DATADIR_OUT /* Data out phase expected */244} datadir_t;245 246#include "queue.h"247#include "msgqueue.h"248 249#define STATUS_BUFFER_SIZE 32250/*251 * This is used to dump the previous states of the SBIC252 */253struct status_entry {254 unsigned long when;255 unsigned char ssr;256 unsigned char ph;257 unsigned char irq;258 unsigned char unused;259};260 261#define ADD_STATUS(_q,_ssr,_ph,_irq) \262({ \263 host->status[(_q)][host->status_ptr[(_q)]].when = jiffies; \264 host->status[(_q)][host->status_ptr[(_q)]].ssr = (_ssr); \265 host->status[(_q)][host->status_ptr[(_q)]].ph = (_ph); \266 host->status[(_q)][host->status_ptr[(_q)]].irq = (_irq); \267 host->status_ptr[(_q)] = (host->status_ptr[(_q)] + 1) & (STATUS_BUFFER_SIZE - 1); \268})269 270/*271 * AcornSCSI host specific data272 */273typedef struct acornscsi_hostdata {274 /* miscellaneous */275 struct Scsi_Host *host; /* host */276 struct scsi_cmnd *SCpnt; /* currently processing command */277 struct scsi_cmnd *origSCpnt; /* original connecting command */278 void __iomem *base; /* memc base address */279 void __iomem *fast; /* fast ioc base address */280 281 /* driver information */282 struct {283 unsigned int irq; /* interrupt */284 phase_t phase; /* current phase */285 286 struct {287 unsigned char target; /* reconnected target */288 unsigned char lun; /* reconnected lun */289 unsigned char tag; /* reconnected tag */290 } reconnected;291 292 struct scsi_pointer SCp; /* current commands data pointer */293 294 MsgQueue_t msgs;295 296 unsigned short last_message; /* last message to be sent */297 unsigned char disconnectable:1; /* this command can be disconnected */298 } scsi;299 300 /* statistics information */301 struct {302 unsigned int queues;303 unsigned int removes;304 unsigned int fins;305 unsigned int reads;306 unsigned int writes;307 unsigned int miscs;308 unsigned int disconnects;309 unsigned int aborts;310 unsigned int resets;311 } stats;312 313 /* queue handling */314 struct {315 Queue_t issue; /* issue queue */316 Queue_t disconnected; /* disconnected command queue */317 } queues;318 319 /* per-device info */320 struct {321 unsigned char sync_xfer; /* synchronous transfer (SBIC value) */322 syncxfer_t sync_state; /* sync xfer negotiation state */323 unsigned char disconnect_ok:1; /* device can disconnect */324 } device[8];325 unsigned long busyluns[64 / sizeof(unsigned long)];/* array of bits indicating LUNs busy */326 327 /* DMA info */328 struct {329 unsigned int free_addr; /* next free address */330 unsigned int start_addr; /* start address of current transfer */331 dmadir_t direction; /* dma direction */332 unsigned int transferred; /* number of bytes transferred */333 unsigned int xfer_start; /* scheduled DMA transfer start */334 unsigned int xfer_length; /* scheduled DMA transfer length */335 char *xfer_ptr; /* pointer to area */336 unsigned char xfer_required:1; /* set if we need to transfer something */337 unsigned char xfer_setup:1; /* set if DMA is setup */338 unsigned char xfer_done:1; /* set if DMA reached end of BH list */339 } dma;340 341 /* card info */342 struct {343 unsigned char page_reg; /* current setting of page reg */344 } card;345 346 unsigned char status_ptr[9];347 struct status_entry status[9][STATUS_BUFFER_SIZE];348} AS_Host;349 350#endif /* ACORNSCSI_H */351