brintos / linux-shallow public Read only

1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (C) 2021 Broadcom. All Rights Reserved. The term4 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.5 *6 */7 8/*9 * All common SLI-4 structures and function prototypes.10 */11 12#ifndef _SLI4_H13#define _SLI4_H14 15#include <linux/pci.h>16#include <linux/delay.h>17#include "scsi/fc/fc_els.h"18#include "scsi/fc/fc_fs.h"19#include "../include/efc_common.h"20 21/*************************************************************************22 * Common SLI-4 register offsets and field definitions23 */24 25/* SLI_INTF - SLI Interface Definition Register */26#define SLI4_INTF_REG			0x005827enum sli4_intf {28	SLI4_INTF_REV_SHIFT		= 4,29	SLI4_INTF_REV_MASK		= 0xf0,30 31	SLI4_INTF_REV_S3		= 0x30,32	SLI4_INTF_REV_S4		= 0x40,33 34	SLI4_INTF_FAMILY_SHIFT		= 8,35	SLI4_INTF_FAMILY_MASK		= 0x0f00,36 37	SLI4_FAMILY_CHECK_ASIC_TYPE	= 0x0f00,38 39	SLI4_INTF_IF_TYPE_SHIFT		= 12,40	SLI4_INTF_IF_TYPE_MASK		= 0xf000,41 42	SLI4_INTF_IF_TYPE_2		= 0x2000,43	SLI4_INTF_IF_TYPE_6		= 0x6000,44 45	SLI4_INTF_VALID_SHIFT		= 29,46	SLI4_INTF_VALID_MASK		= 0xe0000000,47 48	SLI4_INTF_VALID_VALUE		= 0xc0000000,49};50 51/* ASIC_ID - SLI ASIC Type and Revision Register */52#define SLI4_ASIC_ID_REG	0x009c53enum sli4_asic {54	SLI4_ASIC_GEN_SHIFT	= 8,55	SLI4_ASIC_GEN_MASK	= 0xff00,56	SLI4_ASIC_GEN_5		= 0x0b00,57	SLI4_ASIC_GEN_6		= 0x0c00,58	SLI4_ASIC_GEN_7		= 0x0d00,59};60 61enum sli4_acic_revisions {62	SLI4_ASIC_REV_A0	= 0x00,63	SLI4_ASIC_REV_A1	= 0x01,64	SLI4_ASIC_REV_A2	= 0x02,65	SLI4_ASIC_REV_A3	= 0x03,66	SLI4_ASIC_REV_B0	= 0x10,67	SLI4_ASIC_REV_B1	= 0x11,68	SLI4_ASIC_REV_B2	= 0x12,69	SLI4_ASIC_REV_C0	= 0x20,70	SLI4_ASIC_REV_C1	= 0x21,71	SLI4_ASIC_REV_C2	= 0x22,72	SLI4_ASIC_REV_D0	= 0x30,73};74 75struct sli4_asic_entry_t {76	u32 rev_id;77	u32 family;78};79 80/* BMBX - Bootstrap Mailbox Register */81#define SLI4_BMBX_REG		0x016082enum sli4_bmbx {83	SLI4_BMBX_MASK_HI	= 0x3,84	SLI4_BMBX_MASK_LO	= 0xf,85	SLI4_BMBX_RDY		= 1 << 0,86	SLI4_BMBX_HI		= 1 << 1,87	SLI4_BMBX_SIZE		= 256,88};89 90static inline u3291sli_bmbx_write_hi(u64 addr) {92	u32 val;93 94	val = upper_32_bits(addr) & ~SLI4_BMBX_MASK_HI;95	val |= SLI4_BMBX_HI;96 97	return val;98}99 100static inline u32101sli_bmbx_write_lo(u64 addr) {102	u32 val;103 104	val = (upper_32_bits(addr) & SLI4_BMBX_MASK_HI) << 30;105	val |= ((addr) & ~SLI4_BMBX_MASK_LO) >> 2;106 107	return val;108}109 110/* SLIPORT_CONTROL - SLI Port Control Register */111#define SLI4_PORT_CTRL_REG	0x0408112enum sli4_port_ctrl {113	SLI4_PORT_CTRL_IP	= 1u << 27,114	SLI4_PORT_CTRL_IDIS	= 1u << 22,115	SLI4_PORT_CTRL_FDD	= 1u << 31,116};117 118/* SLI4_SLIPORT_ERROR - SLI Port Error Register */119#define SLI4_PORT_ERROR1	0x040c120#define SLI4_PORT_ERROR2	0x0410121 122/* EQCQ_DOORBELL - EQ and CQ Doorbell Register */123#define SLI4_EQCQ_DB_REG	0x120124enum sli4_eqcq_e {125	SLI4_EQ_ID_LO_MASK	= 0x01ff,126 127	SLI4_CQ_ID_LO_MASK	= 0x03ff,128 129	SLI4_EQCQ_CI_EQ		= 0x0200,130 131	SLI4_EQCQ_QT_EQ		= 0x00000400,132	SLI4_EQCQ_QT_CQ		= 0x00000000,133 134	SLI4_EQCQ_ID_HI_SHIFT	= 11,135	SLI4_EQCQ_ID_HI_MASK	= 0xf800,136 137	SLI4_EQCQ_NUM_SHIFT	= 16,138	SLI4_EQCQ_NUM_MASK	= 0x1fff0000,139 140	SLI4_EQCQ_ARM		= 0x20000000,141	SLI4_EQCQ_UNARM		= 0x00000000,142};143 144static inline u32145sli_format_eq_db_data(u16 num_popped, u16 id, u32 arm) {146	u32 reg;147 148	reg = (id & SLI4_EQ_ID_LO_MASK) | SLI4_EQCQ_QT_EQ;149	reg |= (((id) >> 9) << SLI4_EQCQ_ID_HI_SHIFT) & SLI4_EQCQ_ID_HI_MASK;150	reg |= ((num_popped) << SLI4_EQCQ_NUM_SHIFT) & SLI4_EQCQ_NUM_MASK;151	reg |= arm | SLI4_EQCQ_CI_EQ;152 153	return reg;154}155 156static inline u32157sli_format_cq_db_data(u16 num_popped, u16 id, u32 arm) {158	u32 reg;159 160	reg = ((id) & SLI4_CQ_ID_LO_MASK) | SLI4_EQCQ_QT_CQ;161	reg |= (((id) >> 10) << SLI4_EQCQ_ID_HI_SHIFT) & SLI4_EQCQ_ID_HI_MASK;162	reg |= ((num_popped) << SLI4_EQCQ_NUM_SHIFT) & SLI4_EQCQ_NUM_MASK;163	reg |= arm;164 165	return reg;166}167 168/* EQ_DOORBELL - EQ Doorbell Register for IF_TYPE = 6*/169#define SLI4_IF6_EQ_DB_REG	0x120170enum sli4_eq_e {171	SLI4_IF6_EQ_ID_MASK	= 0x0fff,172 173	SLI4_IF6_EQ_NUM_SHIFT	= 16,174	SLI4_IF6_EQ_NUM_MASK	= 0x1fff0000,175};176 177static inline u32178sli_format_if6_eq_db_data(u16 num_popped, u16 id, u32 arm) {179	u32 reg;180 181	reg = id & SLI4_IF6_EQ_ID_MASK;182	reg |= (num_popped << SLI4_IF6_EQ_NUM_SHIFT) & SLI4_IF6_EQ_NUM_MASK;183	reg |= arm;184 185	return reg;186}187 188/* CQ_DOORBELL - CQ Doorbell Register for IF_TYPE = 6 */189#define SLI4_IF6_CQ_DB_REG	0xc0190enum sli4_cq_e {191	SLI4_IF6_CQ_ID_MASK	= 0xffff,192 193	SLI4_IF6_CQ_NUM_SHIFT	= 16,194	SLI4_IF6_CQ_NUM_MASK	= 0x1fff0000,195};196 197static inline u32198sli_format_if6_cq_db_data(u16 num_popped, u16 id, u32 arm) {199	u32 reg;200 201	reg = id & SLI4_IF6_CQ_ID_MASK;202	reg |= ((num_popped) << SLI4_IF6_CQ_NUM_SHIFT) & SLI4_IF6_CQ_NUM_MASK;203	reg |= arm;204 205	return reg;206}207 208/* MQ_DOORBELL - MQ Doorbell Register */209#define SLI4_MQ_DB_REG		0x0140210#define SLI4_IF6_MQ_DB_REG	0x0160211enum sli4_mq_e {212	SLI4_MQ_ID_MASK		= 0xffff,213 214	SLI4_MQ_NUM_SHIFT	= 16,215	SLI4_MQ_NUM_MASK	= 0x3fff0000,216};217 218static inline u32219sli_format_mq_db_data(u16 id) {220	u32 reg;221 222	reg = id & SLI4_MQ_ID_MASK;223	reg |= (1 << SLI4_MQ_NUM_SHIFT) & SLI4_MQ_NUM_MASK;224 225	return reg;226}227 228/* RQ_DOORBELL - RQ Doorbell Register */229#define SLI4_RQ_DB_REG		0x0a0230#define SLI4_IF6_RQ_DB_REG	0x0080231enum sli4_rq_e {232	SLI4_RQ_DB_ID_MASK	= 0xffff,233 234	SLI4_RQ_DB_NUM_SHIFT	= 16,235	SLI4_RQ_DB_NUM_MASK	= 0x3fff0000,236};237 238static inline u32239sli_format_rq_db_data(u16 id) {240	u32 reg;241 242	reg = id & SLI4_RQ_DB_ID_MASK;243	reg |= (1 << SLI4_RQ_DB_NUM_SHIFT) & SLI4_RQ_DB_NUM_MASK;244 245	return reg;246}247 248/* WQ_DOORBELL - WQ Doorbell Register */249#define SLI4_IO_WQ_DB_REG	0x040250#define SLI4_IF6_WQ_DB_REG	0x040251enum sli4_wq_e {252	SLI4_WQ_ID_MASK		= 0xffff,253 254	SLI4_WQ_IDX_SHIFT	= 16,255	SLI4_WQ_IDX_MASK	= 0xff0000,256 257	SLI4_WQ_NUM_SHIFT	= 24,258	SLI4_WQ_NUM_MASK	= 0x0ff00000,259};260 261static inline u32262sli_format_wq_db_data(u16 id) {263	u32 reg;264 265	reg = id & SLI4_WQ_ID_MASK;266	reg |= (1 << SLI4_WQ_NUM_SHIFT) & SLI4_WQ_NUM_MASK;267 268	return reg;269}270 271/* SLIPORT_STATUS - SLI Port Status Register */272#define SLI4_PORT_STATUS_REGOFF	0x0404273enum sli4_port_status {274	SLI4_PORT_STATUS_FDP	= 1u << 21,275	SLI4_PORT_STATUS_RDY	= 1u << 23,276	SLI4_PORT_STATUS_RN	= 1u << 24,277	SLI4_PORT_STATUS_DIP	= 1u << 25,278	SLI4_PORT_STATUS_OTI	= 1u << 29,279	SLI4_PORT_STATUS_ERR	= 1u << 31,280};281 282#define SLI4_PHYDEV_CTRL_REG	0x0414283#define SLI4_PHYDEV_CTRL_FRST	(1 << 1)284#define SLI4_PHYDEV_CTRL_DD	(1 << 2)285 286/* Register name enums */287enum sli4_regname_en {288	SLI4_REG_BMBX,289	SLI4_REG_EQ_DOORBELL,290	SLI4_REG_CQ_DOORBELL,291	SLI4_REG_RQ_DOORBELL,292	SLI4_REG_IO_WQ_DOORBELL,293	SLI4_REG_MQ_DOORBELL,294	SLI4_REG_PHYSDEV_CONTROL,295	SLI4_REG_PORT_CONTROL,296	SLI4_REG_PORT_ERROR1,297	SLI4_REG_PORT_ERROR2,298	SLI4_REG_PORT_SEMAPHORE,299	SLI4_REG_PORT_STATUS,300	SLI4_REG_UNKWOWN			/* must be last */301};302 303struct sli4_reg {304	u32	rset;305	u32	off;306};307 308struct sli4_dmaaddr {309	__le32 low;310	__le32 high;311};312 313/*314 * a 3-word Buffer Descriptor Entry with315 * address 1st 2 words, length last word316 */317struct sli4_bufptr {318	struct sli4_dmaaddr addr;319	__le32 length;320};321 322/* Buffer Descriptor Entry (BDE) */323enum sli4_bde_e {324	SLI4_BDE_LEN_MASK	= 0x00ffffff,325	SLI4_BDE_TYPE_MASK	= 0xff000000,326};327 328struct sli4_bde {329	__le32		bde_type_buflen;330	union {331		struct sli4_dmaaddr data;332		struct {333			__le32	offset;334			__le32	rsvd2;335		} imm;336		struct sli4_dmaaddr blp;337	} u;338};339 340/* Buffer Descriptors */341enum sli4_bde_type {342	SLI4_BDE_TYPE_SHIFT	= 24,343	SLI4_BDE_TYPE_64	= 0x00,	/* Generic 64-bit data */344	SLI4_BDE_TYPE_IMM	= 0x01,	/* Immediate data */345	SLI4_BDE_TYPE_BLP	= 0x40,	/* Buffer List Pointer */346};347 348#define SLI4_BDE_TYPE_VAL(type) \349	(SLI4_BDE_TYPE_##type << SLI4_BDE_TYPE_SHIFT)350 351/* Scatter-Gather Entry (SGE) */352#define SLI4_SGE_MAX_RESERVED		3353 354enum sli4_sge_type {355	/* DW2 */356	SLI4_SGE_DATA_OFFSET_MASK	= 0x07ffffff,357	/*DW2W1*/358	SLI4_SGE_TYPE_SHIFT		= 27,359	SLI4_SGE_TYPE_MASK		= 0x78000000,360	/*SGE Types*/361	SLI4_SGE_TYPE_DATA		= 0x00,362	SLI4_SGE_TYPE_DIF		= 0x04,	/* Data Integrity Field */363	SLI4_SGE_TYPE_LSP		= 0x05,	/* List Segment Pointer */364	SLI4_SGE_TYPE_PEDIF		= 0x06,	/* Post Encryption Engine DIF */365	SLI4_SGE_TYPE_PESEED		= 0x07,	/* Post Encryption DIF Seed */366	SLI4_SGE_TYPE_DISEED		= 0x08,	/* DIF Seed */367	SLI4_SGE_TYPE_ENC		= 0x09,	/* Encryption */368	SLI4_SGE_TYPE_ATM		= 0x0a,	/* DIF Application Tag Mask */369	SLI4_SGE_TYPE_SKIP		= 0x0c,	/* SKIP */370 371	SLI4_SGE_LAST			= 1u << 31,372};373 374struct sli4_sge {375	__le32		buffer_address_high;376	__le32		buffer_address_low;377	__le32		dw2_flags;378	__le32		buffer_length;379};380 381/* T10 DIF Scatter-Gather Entry (SGE) */382struct sli4_dif_sge {383	__le32		buffer_address_high;384	__le32		buffer_address_low;385	__le32		dw2_flags;386	__le32		rsvd12;387};388 389/* Data Integrity Seed (DISEED) SGE */390enum sli4_diseed_sge_flags {391	/* DW2W1 */392	SLI4_DISEED_SGE_HS		= 1 << 2,393	SLI4_DISEED_SGE_WS		= 1 << 3,394	SLI4_DISEED_SGE_IC		= 1 << 4,395	SLI4_DISEED_SGE_ICS		= 1 << 5,396	SLI4_DISEED_SGE_ATRT		= 1 << 6,397	SLI4_DISEED_SGE_AT		= 1 << 7,398	SLI4_DISEED_SGE_FAT		= 1 << 8,399	SLI4_DISEED_SGE_NA		= 1 << 9,400	SLI4_DISEED_SGE_HI		= 1 << 10,401 402	/* DW3W1 */403	SLI4_DISEED_SGE_BS_MASK		= 0x0007,404	SLI4_DISEED_SGE_AI		= 1 << 3,405	SLI4_DISEED_SGE_ME		= 1 << 4,406	SLI4_DISEED_SGE_RE		= 1 << 5,407	SLI4_DISEED_SGE_CE		= 1 << 6,408	SLI4_DISEED_SGE_NR		= 1 << 7,409 410	SLI4_DISEED_SGE_OP_RX_SHIFT	= 8,411	SLI4_DISEED_SGE_OP_RX_MASK	= 0x0f00,412	SLI4_DISEED_SGE_OP_TX_SHIFT	= 12,413	SLI4_DISEED_SGE_OP_TX_MASK	= 0xf000,414};415 416/* Opcode values */417enum sli4_diseed_sge_opcodes {418	SLI4_DISEED_SGE_OP_IN_NODIF_OUT_CRC,419	SLI4_DISEED_SGE_OP_IN_CRC_OUT_NODIF,420	SLI4_DISEED_SGE_OP_IN_NODIF_OUT_CSUM,421	SLI4_DISEED_SGE_OP_IN_CSUM_OUT_NODIF,422	SLI4_DISEED_SGE_OP_IN_CRC_OUT_CRC,423	SLI4_DISEED_SGE_OP_IN_CSUM_OUT_CSUM,424	SLI4_DISEED_SGE_OP_IN_CRC_OUT_CSUM,425	SLI4_DISEED_SGE_OP_IN_CSUM_OUT_CRC,426	SLI4_DISEED_SGE_OP_IN_RAW_OUT_RAW,427};428 429#define SLI4_DISEED_SGE_OP_RX_VALUE(stype) \430	(SLI4_DISEED_SGE_OP_##stype << SLI4_DISEED_SGE_OP_RX_SHIFT)431#define SLI4_DISEED_SGE_OP_TX_VALUE(stype) \432	(SLI4_DISEED_SGE_OP_##stype << SLI4_DISEED_SGE_OP_TX_SHIFT)433 434struct sli4_diseed_sge {435	__le32		ref_tag_cmp;436	__le32		ref_tag_repl;437	__le16		app_tag_repl;438	__le16		dw2w1_flags;439	__le16		app_tag_cmp;440	__le16		dw3w1_flags;441};442 443/* List Segment Pointer Scatter-Gather Entry (SGE) */444#define SLI4_LSP_SGE_SEGLEN	0x00ffffff445 446struct sli4_lsp_sge {447	__le32		buffer_address_high;448	__le32		buffer_address_low;449	__le32		dw2_flags;450	__le32		dw3_seglen;451};452 453enum sli4_eqe_e {454	SLI4_EQE_VALID	= 1,455	SLI4_EQE_MJCODE	= 0xe,456	SLI4_EQE_MNCODE	= 0xfff0,457};458 459struct sli4_eqe {460	__le16		dw0w0_flags;461	__le16		resource_id;462};463 464#define SLI4_MAJOR_CODE_STANDARD	0465#define SLI4_MAJOR_CODE_SENTINEL	1466 467/* Sentinel EQE indicating the EQ is full */468#define SLI4_EQE_STATUS_EQ_FULL		2469 470enum sli4_mcqe_e {471	SLI4_MCQE_CONSUMED	= 1u << 27,472	SLI4_MCQE_COMPLETED	= 1u << 28,473	SLI4_MCQE_AE		= 1u << 30,474	SLI4_MCQE_VALID		= 1u << 31,475};476 477/* Entry was consumed but not completed */478#define SLI4_MCQE_STATUS_NOT_COMPLETED	-2479 480struct sli4_mcqe {481	__le16		completion_status;482	__le16		extended_status;483	__le32		mqe_tag_low;484	__le32		mqe_tag_high;485	__le32		dw3_flags;486};487 488enum sli4_acqe_e {489	SLI4_ACQE_AE	= 1 << 6, /* async event - this is an ACQE */490	SLI4_ACQE_VAL	= 1 << 7, /* valid - contents of CQE are valid */491};492 493struct sli4_acqe {494	__le32		event_data[3];495	u8		rsvd12;496	u8		event_code;497	u8		event_type;498	u8		ae_val;499};500 501enum sli4_acqe_event_code {502	SLI4_ACQE_EVENT_CODE_LINK_STATE		= 0x01,503	SLI4_ACQE_EVENT_CODE_FIP		= 0x02,504	SLI4_ACQE_EVENT_CODE_DCBX		= 0x03,505	SLI4_ACQE_EVENT_CODE_ISCSI		= 0x04,506	SLI4_ACQE_EVENT_CODE_GRP_5		= 0x05,507	SLI4_ACQE_EVENT_CODE_FC_LINK_EVENT	= 0x10,508	SLI4_ACQE_EVENT_CODE_SLI_PORT_EVENT	= 0x11,509	SLI4_ACQE_EVENT_CODE_VF_EVENT		= 0x12,510	SLI4_ACQE_EVENT_CODE_MR_EVENT		= 0x13,511};512 513enum sli4_qtype {514	SLI4_QTYPE_EQ,515	SLI4_QTYPE_CQ,516	SLI4_QTYPE_MQ,517	SLI4_QTYPE_WQ,518	SLI4_QTYPE_RQ,519	SLI4_QTYPE_MAX,			/* must be last */520};521 522#define SLI4_USER_MQ_COUNT	1523#define SLI4_MAX_CQ_SET_COUNT	16524#define SLI4_MAX_RQ_SET_COUNT	16525 526enum sli4_qentry {527	SLI4_QENTRY_ASYNC,528	SLI4_QENTRY_MQ,529	SLI4_QENTRY_RQ,530	SLI4_QENTRY_WQ,531	SLI4_QENTRY_WQ_RELEASE,532	SLI4_QENTRY_OPT_WRITE_CMD,533	SLI4_QENTRY_OPT_WRITE_DATA,534	SLI4_QENTRY_XABT,535	SLI4_QENTRY_MAX			/* must be last */536};537 538enum sli4_queue_flags {539	SLI4_QUEUE_FLAG_MQ	= 1 << 0,	/* CQ has MQ/Async completion */540	SLI4_QUEUE_FLAG_HDR	= 1 << 1,	/* RQ for packet headers */541	SLI4_QUEUE_FLAG_RQBATCH	= 1 << 2,	/* RQ index increment by 8 */542};543 544/* Generic Command Request header */545enum sli4_cmd_version {546	CMD_V0,547	CMD_V1,548	CMD_V2,549};550 551struct sli4_rqst_hdr {552	u8		opcode;553	u8		subsystem;554	__le16		rsvd2;555	__le32		timeout;556	__le32		request_length;557	__le32		dw3_version;558};559 560/* Generic Command Response header */561struct sli4_rsp_hdr {562	u8		opcode;563	u8		subsystem;564	__le16		rsvd2;565	u8		status;566	u8		additional_status;567	__le16		rsvd6;568	__le32		response_length;569	__le32		actual_response_length;570};571 572#define SLI4_QUEUE_RQ_BATCH	8573 574#define SZ_DMAADDR		sizeof(struct sli4_dmaaddr)575#define SLI4_RQST_CMDSZ(stype)	sizeof(struct sli4_rqst_##stype)576 577#define SLI4_RQST_PYLD_LEN(stype) \578		cpu_to_le32(sizeof(struct sli4_rqst_##stype) - \579			sizeof(struct sli4_rqst_hdr))580 581#define SLI4_RQST_PYLD_LEN_VAR(stype, varpyld) \582		cpu_to_le32((sizeof(struct sli4_rqst_##stype) + \583			varpyld) - sizeof(struct sli4_rqst_hdr))584 585#define SLI4_CFG_PYLD_LENGTH(stype) \586		max(sizeof(struct sli4_rqst_##stype), \587		sizeof(struct sli4_rsp_##stype))588 589enum sli4_create_cqv2_e {590	/* DW5_flags values*/591	SLI4_CREATE_CQV2_CLSWM_MASK	= 0x00003000,592	SLI4_CREATE_CQV2_NODELAY	= 0x00004000,593	SLI4_CREATE_CQV2_AUTOVALID	= 0x00008000,594	SLI4_CREATE_CQV2_CQECNT_MASK	= 0x18000000,595	SLI4_CREATE_CQV2_VALID		= 0x20000000,596	SLI4_CREATE_CQV2_EVT		= 0x80000000,597	/* DW6W1_flags values*/598	SLI4_CREATE_CQV2_ARM		= 0x8000,599};600 601struct sli4_rqst_cmn_create_cq_v2 {602	struct sli4_rqst_hdr	hdr;603	__le16			num_pages;604	u8			page_size;605	u8			rsvd19;606	__le32			dw5_flags;607	__le16			eq_id;608	__le16			dw6w1_arm;609	__le16			cqe_count;610	__le16			rsvd30;611	__le32			rsvd32;612	struct sli4_dmaaddr	page_phys_addr[];613};614 615enum sli4_create_cqset_e {616	/* DW5_flags values*/617	SLI4_CREATE_CQSETV0_CLSWM_MASK	= 0x00003000,618	SLI4_CREATE_CQSETV0_NODELAY	= 0x00004000,619	SLI4_CREATE_CQSETV0_AUTOVALID	= 0x00008000,620	SLI4_CREATE_CQSETV0_CQECNT_MASK	= 0x18000000,621	SLI4_CREATE_CQSETV0_VALID	= 0x20000000,622	SLI4_CREATE_CQSETV0_EVT		= 0x80000000,623	/* DW5W1_flags values */624	SLI4_CREATE_CQSETV0_CQE_COUNT	= 0x7fff,625	SLI4_CREATE_CQSETV0_ARM		= 0x8000,626};627 628struct sli4_rqst_cmn_create_cq_set_v0 {629	struct sli4_rqst_hdr	hdr;630	__le16			num_pages;631	u8			page_size;632	u8			rsvd19;633	__le32			dw5_flags;634	__le16			num_cq_req;635	__le16			dw6w1_flags;636	__le16			eq_id[16];637	struct sli4_dmaaddr	page_phys_addr[];638};639 640/* CQE count */641enum sli4_cq_cnt {642	SLI4_CQ_CNT_256,643	SLI4_CQ_CNT_512,644	SLI4_CQ_CNT_1024,645	SLI4_CQ_CNT_LARGE,646};647 648#define SLI4_CQ_CNT_SHIFT	27649#define SLI4_CQ_CNT_VAL(type)	(SLI4_CQ_CNT_##type << SLI4_CQ_CNT_SHIFT)650 651#define SLI4_CQE_BYTES		(4 * sizeof(u32))652 653#define SLI4_CREATE_CQV2_MAX_PAGES	8654 655/* Generic Common Create EQ/CQ/MQ/WQ/RQ Queue completion */656struct sli4_rsp_cmn_create_queue {657	struct sli4_rsp_hdr	hdr;658	__le16	q_id;659	u8	rsvd18;660	u8	ulp;661	__le32	db_offset;662	__le16	db_rs;663	__le16	db_fmt;664};665 666struct sli4_rsp_cmn_create_queue_set {667	struct sli4_rsp_hdr	hdr;668	__le16	q_id;669	__le16	num_q_allocated;670};671 672/* Common Destroy Queue */673struct sli4_rqst_cmn_destroy_q {674	struct sli4_rqst_hdr	hdr;675	__le16	q_id;676	__le16	rsvd;677};678 679struct sli4_rsp_cmn_destroy_q {680	struct sli4_rsp_hdr	hdr;681};682 683/* Modify the delay multiplier for EQs */684struct sli4_eqdelay_rec {685	__le32  eq_id;686	__le32  phase;687	__le32  delay_multiplier;688};689 690struct sli4_rqst_cmn_modify_eq_delay {691	struct sli4_rqst_hdr	hdr;692	__le32			num_eq;693	struct sli4_eqdelay_rec eq_delay_record[8];694};695 696struct sli4_rsp_cmn_modify_eq_delay {697	struct sli4_rsp_hdr	hdr;698};699 700enum sli4_create_cq_e {701	/* DW5 */702	SLI4_CREATE_EQ_AUTOVALID		= 1u << 28,703	SLI4_CREATE_EQ_VALID			= 1u << 29,704	SLI4_CREATE_EQ_EQESZ			= 1u << 31,705	/* DW6 */706	SLI4_CREATE_EQ_COUNT			= 7 << 26,707	SLI4_CREATE_EQ_ARM			= 1u << 31,708	/* DW7 */709	SLI4_CREATE_EQ_DELAYMULTI_SHIFT		= 13,710	SLI4_CREATE_EQ_DELAYMULTI_MASK		= 0x007fe000,711	SLI4_CREATE_EQ_DELAYMULTI		= 0x00040000,712};713 714struct sli4_rqst_cmn_create_eq {715	struct sli4_rqst_hdr	hdr;716	__le16			num_pages;717	__le16			rsvd18;718	__le32			dw5_flags;719	__le32			dw6_flags;720	__le32			dw7_delaymulti;721	__le32			rsvd32;722	struct sli4_dmaaddr	page_address[8];723};724 725struct sli4_rsp_cmn_create_eq {726	struct sli4_rsp_cmn_create_queue q_rsp;727};728 729/* EQ count */730enum sli4_eq_cnt {731	SLI4_EQ_CNT_256,732	SLI4_EQ_CNT_512,733	SLI4_EQ_CNT_1024,734	SLI4_EQ_CNT_2048,735	SLI4_EQ_CNT_4096 = 3,736};737 738#define SLI4_EQ_CNT_SHIFT	26739#define SLI4_EQ_CNT_VAL(type)	(SLI4_EQ_CNT_##type << SLI4_EQ_CNT_SHIFT)740 741#define SLI4_EQE_SIZE_4		0742#define SLI4_EQE_SIZE_16	1743 744/* Create a Mailbox Queue; accommodate v0 and v1 forms. */745enum sli4_create_mq_flags {746	/* DW6W1 */747	SLI4_CREATE_MQEXT_RINGSIZE	= 0xf,748	SLI4_CREATE_MQEXT_CQID_SHIFT	= 6,749	SLI4_CREATE_MQEXT_CQIDV0_MASK	= 0xffc0,750	/* DW7 */751	SLI4_CREATE_MQEXT_VAL		= 1u << 31,752	/* DW8 */753	SLI4_CREATE_MQEXT_ACQV		= 1u << 0,754	SLI4_CREATE_MQEXT_ASYNC_CQIDV0	= 0x7fe,755};756 757struct sli4_rqst_cmn_create_mq_ext {758	struct sli4_rqst_hdr	hdr;759	__le16			num_pages;760	__le16			cq_id_v1;761	__le32			async_event_bitmap;762	__le16			async_cq_id_v1;763	__le16			dw6w1_flags;764	__le32			dw7_val;765	__le32			dw8_flags;766	__le32			rsvd36;767	struct sli4_dmaaddr	page_phys_addr[];768};769 770struct sli4_rsp_cmn_create_mq_ext {771	struct sli4_rsp_cmn_create_queue q_rsp;772};773 774enum sli4_mqe_size {775	SLI4_MQE_SIZE_16 = 0x05,776	SLI4_MQE_SIZE_32,777	SLI4_MQE_SIZE_64,778	SLI4_MQE_SIZE_128,779};780 781enum sli4_async_evt {782	SLI4_ASYNC_EVT_LINK_STATE	= 1 << 1,783	SLI4_ASYNC_EVT_FIP		= 1 << 2,784	SLI4_ASYNC_EVT_GRP5		= 1 << 5,785	SLI4_ASYNC_EVT_FC		= 1 << 16,786	SLI4_ASYNC_EVT_SLI_PORT		= 1 << 17,787};788 789#define	SLI4_ASYNC_EVT_FC_ALL \790		(SLI4_ASYNC_EVT_LINK_STATE	| \791		 SLI4_ASYNC_EVT_FIP		| \792		 SLI4_ASYNC_EVT_GRP5		| \793		 SLI4_ASYNC_EVT_FC		| \794		 SLI4_ASYNC_EVT_SLI_PORT)795 796/* Create a Completion Queue. */797struct sli4_rqst_cmn_create_cq_v0 {798	struct sli4_rqst_hdr	hdr;799	__le16			num_pages;800	__le16			rsvd18;801	__le32			dw5_flags;802	__le32			dw6_flags;803	__le32			rsvd28;804	__le32			rsvd32;805	struct sli4_dmaaddr	page_phys_addr[];806};807 808enum sli4_create_rq_e {809	SLI4_RQ_CREATE_DUA		= 0x1,810	SLI4_RQ_CREATE_BQU		= 0x2,811 812	SLI4_RQE_SIZE			= 8,813	SLI4_RQE_SIZE_8			= 0x2,814	SLI4_RQE_SIZE_16		= 0x3,815	SLI4_RQE_SIZE_32		= 0x4,816	SLI4_RQE_SIZE_64		= 0x5,817	SLI4_RQE_SIZE_128		= 0x6,818 819	SLI4_RQ_PAGE_SIZE_4096		= 0x1,820	SLI4_RQ_PAGE_SIZE_8192		= 0x2,821	SLI4_RQ_PAGE_SIZE_16384		= 0x4,822	SLI4_RQ_PAGE_SIZE_32768		= 0x8,823	SLI4_RQ_PAGE_SIZE_64536		= 0x10,824 825	SLI4_RQ_CREATE_V0_MAX_PAGES	= 8,826	SLI4_RQ_CREATE_V0_MIN_BUF_SIZE	= 128,827	SLI4_RQ_CREATE_V0_MAX_BUF_SIZE	= 2048,828};829 830struct sli4_rqst_rq_create {831	struct sli4_rqst_hdr	hdr;832	__le16			num_pages;833	u8			dua_bqu_byte;834	u8			ulp;835	__le16			rsvd16;836	u8			rqe_count_byte;837	u8			rsvd19;838	__le32			rsvd20;839	__le16			buffer_size;840	__le16			cq_id;841	__le32			rsvd28;842	struct sli4_dmaaddr	page_phys_addr[SLI4_RQ_CREATE_V0_MAX_PAGES];843};844 845struct sli4_rsp_rq_create {846	struct sli4_rsp_cmn_create_queue rsp;847};848 849enum sli4_create_rqv1_e {850	SLI4_RQ_CREATE_V1_DNB		= 0x80,851	SLI4_RQ_CREATE_V1_MAX_PAGES	= 8,852	SLI4_RQ_CREATE_V1_MIN_BUF_SIZE	= 64,853	SLI4_RQ_CREATE_V1_MAX_BUF_SIZE	= 2048,854};855 856struct sli4_rqst_rq_create_v1 {857	struct sli4_rqst_hdr	hdr;858	__le16			num_pages;859	u8			rsvd14;860	u8			dim_dfd_dnb;861	u8			page_size;862	u8			rqe_size_byte;863	__le16			rqe_count;864	__le32			rsvd20;865	__le16			rsvd24;866	__le16			cq_id;867	__le32			buffer_size;868	struct sli4_dmaaddr	page_phys_addr[SLI4_RQ_CREATE_V1_MAX_PAGES];869};870 871struct sli4_rsp_rq_create_v1 {872	struct sli4_rsp_cmn_create_queue rsp;873};874 875#define	SLI4_RQCREATEV2_DNB	0x80876 877struct sli4_rqst_rq_create_v2 {878	struct sli4_rqst_hdr	hdr;879	__le16			num_pages;880	u8			rq_count;881	u8			dim_dfd_dnb;882	u8			page_size;883	u8			rqe_size_byte;884	__le16			rqe_count;885	__le16			hdr_buffer_size;886	__le16			payload_buffer_size;887	__le16			base_cq_id;888	__le16			rsvd26;889	__le32			rsvd42;890	struct sli4_dmaaddr	page_phys_addr[];891};892 893struct sli4_rsp_rq_create_v2 {894	struct sli4_rsp_cmn_create_queue rsp;895};896 897#define SLI4_CQE_CODE_OFFSET	14898 899enum sli4_cqe_code {900	SLI4_CQE_CODE_WORK_REQUEST_COMPLETION = 0x01,901	SLI4_CQE_CODE_RELEASE_WQE,902	SLI4_CQE_CODE_RSVD,903	SLI4_CQE_CODE_RQ_ASYNC,904	SLI4_CQE_CODE_XRI_ABORTED,905	SLI4_CQE_CODE_RQ_COALESCING,906	SLI4_CQE_CODE_RQ_CONSUMPTION,907	SLI4_CQE_CODE_MEASUREMENT_REPORTING,908	SLI4_CQE_CODE_RQ_ASYNC_V1,909	SLI4_CQE_CODE_RQ_COALESCING_V1,910	SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD,911	SLI4_CQE_CODE_OPTIMIZED_WRITE_DATA,912};913 914#define SLI4_WQ_CREATE_MAX_PAGES		8915 916struct sli4_rqst_wq_create {917	struct sli4_rqst_hdr	hdr;918	__le16			num_pages;919	__le16			cq_id;920	u8			page_size;921	u8			wqe_size_byte;922	__le16			wqe_count;923	__le32			rsvd;924	struct	sli4_dmaaddr	page_phys_addr[SLI4_WQ_CREATE_MAX_PAGES];925};926 927struct sli4_rsp_wq_create {928	struct sli4_rsp_cmn_create_queue rsp;929};930 931enum sli4_link_attention_flags {932	SLI4_LNK_ATTN_TYPE_LINK_UP		= 0x01,933	SLI4_LNK_ATTN_TYPE_LINK_DOWN		= 0x02,934	SLI4_LNK_ATTN_TYPE_NO_HARD_ALPA		= 0x03,935 936	SLI4_LNK_ATTN_P2P			= 0x01,937	SLI4_LNK_ATTN_FC_AL			= 0x02,938	SLI4_LNK_ATTN_INTERNAL_LOOPBACK		= 0x03,939	SLI4_LNK_ATTN_SERDES_LOOPBACK		= 0x04,940};941 942struct sli4_link_attention {943	u8		link_number;944	u8		attn_type;945	u8		topology;946	u8		port_speed;947	u8		port_fault;948	u8		shared_link_status;949	__le16		logical_link_speed;950	__le32		event_tag;951	u8		rsvd12;952	u8		event_code;953	u8		event_type;954	u8		flags;955};956 957enum sli4_link_event_type {958	SLI4_EVENT_LINK_ATTENTION		= 0x01,959	SLI4_EVENT_SHARED_LINK_ATTENTION	= 0x02,960};961 962enum sli4_wcqe_flags {963	SLI4_WCQE_XB = 0x10,964	SLI4_WCQE_QX = 0x80,965};966 967struct sli4_fc_wcqe {968	u8		hw_status;969	u8		status;970	__le16		request_tag;971	__le32		wqe_specific_1;972	__le32		wqe_specific_2;973	u8		rsvd12;974	u8		qx_byte;975	u8		code;976	u8		flags;977};978 979/* FC WQ consumed CQ queue entry */980struct sli4_fc_wqec {981	__le32		rsvd0;982	__le32		rsvd1;983	__le16		wqe_index;984	__le16		wq_id;985	__le16		rsvd12;986	u8		code;987	u8		vld_byte;988};989 990/* FC Completion Status Codes. */991enum sli4_wcqe_status {992	SLI4_FC_WCQE_STATUS_SUCCESS,993	SLI4_FC_WCQE_STATUS_FCP_RSP_FAILURE,994	SLI4_FC_WCQE_STATUS_REMOTE_STOP,995	SLI4_FC_WCQE_STATUS_LOCAL_REJECT,996	SLI4_FC_WCQE_STATUS_NPORT_RJT,997	SLI4_FC_WCQE_STATUS_FABRIC_RJT,998	SLI4_FC_WCQE_STATUS_NPORT_BSY,999	SLI4_FC_WCQE_STATUS_FABRIC_BSY,1000	SLI4_FC_WCQE_STATUS_RSVD,1001	SLI4_FC_WCQE_STATUS_LS_RJT,1002	SLI4_FC_WCQE_STATUS_RX_BUF_OVERRUN,1003	SLI4_FC_WCQE_STATUS_CMD_REJECT,1004	SLI4_FC_WCQE_STATUS_FCP_TGT_LENCHECK,1005	SLI4_FC_WCQE_STATUS_RSVD1,1006	SLI4_FC_WCQE_STATUS_ELS_CMPLT_NO_AUTOREG,1007	SLI4_FC_WCQE_STATUS_RSVD2,1008	SLI4_FC_WCQE_STATUS_RQ_SUCCESS,1009	SLI4_FC_WCQE_STATUS_RQ_BUF_LEN_EXCEEDED,1010	SLI4_FC_WCQE_STATUS_RQ_INSUFF_BUF_NEEDED,1011	SLI4_FC_WCQE_STATUS_RQ_INSUFF_FRM_DISC,1012	SLI4_FC_WCQE_STATUS_RQ_DMA_FAILURE,1013	SLI4_FC_WCQE_STATUS_FCP_RSP_TRUNCATE,1014	SLI4_FC_WCQE_STATUS_DI_ERROR,1015	SLI4_FC_WCQE_STATUS_BA_RJT,1016	SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_NEEDED,1017	SLI4_FC_WCQE_STATUS_RQ_INSUFF_XRI_DISC,1018	SLI4_FC_WCQE_STATUS_RX_ERROR_DETECT,1019	SLI4_FC_WCQE_STATUS_RX_ABORT_REQUEST,1020 1021	/* driver generated status codes */1022	SLI4_FC_WCQE_STATUS_DISPATCH_ERROR	= 0xfd,1023	SLI4_FC_WCQE_STATUS_SHUTDOWN		= 0xfe,1024	SLI4_FC_WCQE_STATUS_TARGET_WQE_TIMEOUT	= 0xff,1025};1026 1027/* DI_ERROR Extended Status */1028enum sli4_fc_di_error_status {1029	SLI4_FC_DI_ERROR_GE			= 1 << 0,1030	SLI4_FC_DI_ERROR_AE			= 1 << 1,1031	SLI4_FC_DI_ERROR_RE			= 1 << 2,1032	SLI4_FC_DI_ERROR_TDPV			= 1 << 3,1033	SLI4_FC_DI_ERROR_UDB			= 1 << 4,1034	SLI4_FC_DI_ERROR_EDIR			= 1 << 5,1035};1036 1037/* WQE DIF field contents */1038enum sli4_dif_fields {1039	SLI4_DIF_DISABLED,1040	SLI4_DIF_PASS_THROUGH,1041	SLI4_DIF_STRIP,1042	SLI4_DIF_INSERT,1043};1044 1045/* Work Queue Entry (WQE) types */1046enum sli4_wqe_types {1047	SLI4_WQE_ABORT				= 0x0f,1048	SLI4_WQE_ELS_REQUEST64			= 0x8a,1049	SLI4_WQE_FCP_IBIDIR64			= 0xac,1050	SLI4_WQE_FCP_IREAD64			= 0x9a,1051	SLI4_WQE_FCP_IWRITE64			= 0x98,1052	SLI4_WQE_FCP_ICMND64			= 0x9c,1053	SLI4_WQE_FCP_TRECEIVE64			= 0xa1,1054	SLI4_WQE_FCP_CONT_TRECEIVE64		= 0xe5,1055	SLI4_WQE_FCP_TRSP64			= 0xa3,1056	SLI4_WQE_FCP_TSEND64			= 0x9f,1057	SLI4_WQE_GEN_REQUEST64			= 0xc2,1058	SLI4_WQE_SEND_FRAME			= 0xe1,1059	SLI4_WQE_XMIT_BCAST64			= 0x84,1060	SLI4_WQE_XMIT_BLS_RSP			= 0x97,1061	SLI4_WQE_ELS_RSP64			= 0x95,1062	SLI4_WQE_XMIT_SEQUENCE64		= 0x82,1063	SLI4_WQE_REQUEUE_XRI			= 0x93,1064};1065 1066/* WQE command types */1067enum sli4_wqe_cmds {1068	SLI4_CMD_FCP_IREAD64_WQE		= 0x00,1069	SLI4_CMD_FCP_ICMND64_WQE		= 0x00,1070	SLI4_CMD_FCP_IWRITE64_WQE		= 0x01,1071	SLI4_CMD_FCP_TRECEIVE64_WQE		= 0x02,1072	SLI4_CMD_FCP_TRSP64_WQE			= 0x03,1073	SLI4_CMD_FCP_TSEND64_WQE		= 0x07,1074	SLI4_CMD_GEN_REQUEST64_WQE		= 0x08,1075	SLI4_CMD_XMIT_BCAST64_WQE		= 0x08,1076	SLI4_CMD_XMIT_BLS_RSP64_WQE		= 0x08,1077	SLI4_CMD_ABORT_WQE			= 0x08,1078	SLI4_CMD_XMIT_SEQUENCE64_WQE		= 0x08,1079	SLI4_CMD_REQUEUE_XRI_WQE		= 0x0a,1080	SLI4_CMD_SEND_FRAME_WQE			= 0x0a,1081};1082 1083#define SLI4_WQE_SIZE		0x051084#define SLI4_WQE_EXT_SIZE	0x061085 1086#define SLI4_WQE_BYTES		(16 * sizeof(u32))1087#define SLI4_WQE_EXT_BYTES	(32 * sizeof(u32))1088 1089/* Mask for ccp (CS_CTL) */1090#define SLI4_MASK_CCP		0xfe1091 1092/* Generic WQE */1093enum sli4_gen_wqe_flags {1094	SLI4_GEN_WQE_EBDECNT	= 0xf,1095	SLI4_GEN_WQE_LEN_LOC	= 0x3 << 7,1096	SLI4_GEN_WQE_QOSD	= 1 << 9,1097	SLI4_GEN_WQE_XBL	= 1 << 11,1098	SLI4_GEN_WQE_HLM	= 1 << 12,1099	SLI4_GEN_WQE_IOD	= 1 << 13,1100	SLI4_GEN_WQE_DBDE	= 1 << 14,1101	SLI4_GEN_WQE_WQES	= 1 << 15,1102 1103	SLI4_GEN_WQE_PRI	= 0x7,1104	SLI4_GEN_WQE_PV		= 1 << 3,1105	SLI4_GEN_WQE_EAT	= 1 << 4,1106	SLI4_GEN_WQE_XC		= 1 << 5,1107	SLI4_GEN_WQE_CCPE	= 1 << 7,1108 1109	SLI4_GEN_WQE_CMDTYPE	= 0xf,1110	SLI4_GEN_WQE_WQEC	= 1 << 7,1111};1112 1113struct sli4_generic_wqe {1114	__le32		cmd_spec0_5[6];1115	__le16		xri_tag;1116	__le16		context_tag;1117	u8		ct_byte;1118	u8		command;1119	u8		class_byte;1120	u8		timer;1121	__le32		abort_tag;1122	__le16		request_tag;1123	__le16		rsvd34;1124	__le16		dw10w0_flags;1125	u8		eat_xc_ccpe;1126	u8		ccp;1127	u8		cmdtype_wqec_byte;1128	u8		rsvd41;1129	__le16		cq_id;1130};1131 1132/* WQE used to abort exchanges. */1133enum sli4_abort_wqe_flags {1134	SLI4_ABRT_WQE_IR	= 0x02,1135 1136	SLI4_ABRT_WQE_EBDECNT	= 0xf,1137	SLI4_ABRT_WQE_LEN_LOC	= 0x3 << 7,1138	SLI4_ABRT_WQE_QOSD	= 1 << 9,1139	SLI4_ABRT_WQE_XBL	= 1 << 11,1140	SLI4_ABRT_WQE_IOD	= 1 << 13,1141	SLI4_ABRT_WQE_DBDE	= 1 << 14,1142	SLI4_ABRT_WQE_WQES	= 1 << 15,1143 1144	SLI4_ABRT_WQE_PRI	= 0x7,1145	SLI4_ABRT_WQE_PV	= 1 << 3,1146	SLI4_ABRT_WQE_EAT	= 1 << 4,1147	SLI4_ABRT_WQE_XC	= 1 << 5,1148	SLI4_ABRT_WQE_CCPE	= 1 << 7,1149 1150	SLI4_ABRT_WQE_CMDTYPE	= 0xf,1151	SLI4_ABRT_WQE_WQEC	= 1 << 7,1152};1153 1154struct sli4_abort_wqe {1155	__le32		rsvd0;1156	__le32		rsvd4;1157	__le32		ext_t_tag;1158	u8		ia_ir_byte;1159	u8		criteria;1160	__le16		rsvd10;1161	__le32		ext_t_mask;1162	__le32		t_mask;1163	__le16		xri_tag;1164	__le16		context_tag;1165	u8		ct_byte;1166	u8		command;1167	u8		class_byte;1168	u8		timer;1169	__le32		t_tag;1170	__le16		request_tag;1171	__le16		rsvd34;1172	__le16		dw10w0_flags;1173	u8		eat_xc_ccpe;1174	u8		ccp;1175	u8		cmdtype_wqec_byte;1176	u8		rsvd41;1177	__le16		cq_id;1178};1179 1180enum sli4_abort_criteria {1181	SLI4_ABORT_CRITERIA_XRI_TAG = 0x01,1182	SLI4_ABORT_CRITERIA_ABORT_TAG,1183	SLI4_ABORT_CRITERIA_REQUEST_TAG,1184	SLI4_ABORT_CRITERIA_EXT_ABORT_TAG,1185};1186 1187enum sli4_abort_type {1188	SLI4_ABORT_XRI,1189	SLI4_ABORT_ABORT_ID,1190	SLI4_ABORT_REQUEST_ID,1191	SLI4_ABORT_MAX,		/* must be last */1192};1193 1194/* WQE used to create an ELS request. */1195enum sli4_els_req_wqe_flags {1196	SLI4_REQ_WQE_QOSD		= 0x2,1197	SLI4_REQ_WQE_DBDE		= 0x40,1198	SLI4_REQ_WQE_XBL		= 0x8,1199	SLI4_REQ_WQE_XC			= 0x20,1200	SLI4_REQ_WQE_IOD		= 0x20,1201	SLI4_REQ_WQE_HLM		= 0x10,1202	SLI4_REQ_WQE_CCPE		= 0x80,1203	SLI4_REQ_WQE_EAT		= 0x10,1204	SLI4_REQ_WQE_WQES		= 0x80,1205	SLI4_REQ_WQE_PU_SHFT		= 4,1206	SLI4_REQ_WQE_CT_SHFT		= 2,1207	SLI4_REQ_WQE_CT			= 0xc,1208	SLI4_REQ_WQE_ELSID_SHFT		= 4,1209	SLI4_REQ_WQE_SP_SHFT		= 24,1210	SLI4_REQ_WQE_LEN_LOC_BIT1	= 0x80,1211	SLI4_REQ_WQE_LEN_LOC_BIT2	= 0x1,1212};1213 1214struct sli4_els_request64_wqe {1215	struct sli4_bde	els_request_payload;1216	__le32		els_request_payload_length;1217	__le32		sid_sp_dword;1218	__le32		remote_id_dword;1219	__le16		xri_tag;1220	__le16		context_tag;1221	u8		ct_byte;1222	u8		command;1223	u8		class_byte;1224	u8		timer;1225	__le32		abort_tag;1226	__le16		request_tag;1227	__le16		temporary_rpi;1228	u8		len_loc1_byte;1229	u8		qosd_xbl_hlm_iod_dbde_wqes;1230	u8		eat_xc_ccpe;1231	u8		ccp;1232	u8		cmdtype_elsid_byte;1233	u8		rsvd41;1234	__le16		cq_id;1235	struct sli4_bde	els_response_payload_bde;1236	__le32		max_response_payload_length;1237};1238 1239/* WQE used to create an FCP initiator no data command. */1240enum sli4_icmd_wqe_flags {1241	SLI4_ICMD_WQE_DBDE		= 0x40,1242	SLI4_ICMD_WQE_XBL		= 0x8,1243	SLI4_ICMD_WQE_XC		= 0x20,1244	SLI4_ICMD_WQE_IOD		= 0x20,1245	SLI4_ICMD_WQE_HLM		= 0x10,1246	SLI4_ICMD_WQE_CCPE		= 0x80,1247	SLI4_ICMD_WQE_EAT		= 0x10,1248	SLI4_ICMD_WQE_APPID		= 0x10,1249	SLI4_ICMD_WQE_WQES		= 0x80,1250	SLI4_ICMD_WQE_PU_SHFT		= 4,1251	SLI4_ICMD_WQE_CT_SHFT		= 2,1252	SLI4_ICMD_WQE_BS_SHFT		= 4,1253	SLI4_ICMD_WQE_LEN_LOC_BIT1	= 0x80,1254	SLI4_ICMD_WQE_LEN_LOC_BIT2	= 0x1,1255};1256 1257struct sli4_fcp_icmnd64_wqe {1258	struct sli4_bde	bde;1259	__le16		payload_offset_length;1260	__le16		fcp_cmd_buffer_length;1261	__le32		rsvd12;1262	__le32		remote_n_port_id_dword;1263	__le16		xri_tag;1264	__le16		context_tag;1265	u8		dif_ct_bs_byte;1266	u8		command;1267	u8		class_pu_byte;1268	u8		timer;1269	__le32		abort_tag;1270	__le16		request_tag;1271	__le16		rsvd34;1272	u8		len_loc1_byte;1273	u8		qosd_xbl_hlm_iod_dbde_wqes;1274	u8		eat_xc_ccpe;1275	u8		ccp;1276	u8		cmd_type_byte;1277	u8		rsvd41;1278	__le16		cq_id;1279	__le32		rsvd44;1280	__le32		rsvd48;1281	__le32		rsvd52;1282	__le32		rsvd56;1283};1284 1285/* WQE used to create an FCP initiator read. */1286enum sli4_ir_wqe_flags {1287	SLI4_IR_WQE_DBDE		= 0x40,1288	SLI4_IR_WQE_XBL			= 0x8,1289	SLI4_IR_WQE_XC			= 0x20,1290	SLI4_IR_WQE_IOD			= 0x20,1291	SLI4_IR_WQE_HLM			= 0x10,1292	SLI4_IR_WQE_CCPE		= 0x80,1293	SLI4_IR_WQE_EAT			= 0x10,1294	SLI4_IR_WQE_APPID		= 0x10,1295	SLI4_IR_WQE_WQES		= 0x80,1296	SLI4_IR_WQE_PU_SHFT		= 4,1297	SLI4_IR_WQE_CT_SHFT		= 2,1298	SLI4_IR_WQE_BS_SHFT		= 4,1299	SLI4_IR_WQE_LEN_LOC_BIT1	= 0x80,1300	SLI4_IR_WQE_LEN_LOC_BIT2	= 0x1,1301};1302 1303struct sli4_fcp_iread64_wqe {1304	struct sli4_bde	bde;1305	__le16		payload_offset_length;1306	__le16		fcp_cmd_buffer_length;1307 1308	__le32		total_transfer_length;1309 1310	__le32		remote_n_port_id_dword;1311 1312	__le16		xri_tag;1313	__le16		context_tag;1314 1315	u8		dif_ct_bs_byte;1316	u8		command;1317	u8		class_pu_byte;1318	u8		timer;1319 1320	__le32		abort_tag;1321 1322	__le16		request_tag;1323	__le16		rsvd34;1324 1325	u8		len_loc1_byte;1326	u8		qosd_xbl_hlm_iod_dbde_wqes;1327	u8		eat_xc_ccpe;1328	u8		ccp;1329 1330	u8		cmd_type_byte;1331	u8		rsvd41;1332	__le16		cq_id;1333 1334	__le32		rsvd44;1335	struct sli4_bde	first_data_bde;1336};1337 1338/* WQE used to create an FCP initiator write. */1339enum sli4_iwr_wqe_flags {1340	SLI4_IWR_WQE_DBDE		= 0x40,1341	SLI4_IWR_WQE_XBL		= 0x8,1342	SLI4_IWR_WQE_XC			= 0x20,1343	SLI4_IWR_WQE_IOD		= 0x20,1344	SLI4_IWR_WQE_HLM		= 0x10,1345	SLI4_IWR_WQE_DNRX		= 0x10,1346	SLI4_IWR_WQE_CCPE		= 0x80,1347	SLI4_IWR_WQE_EAT		= 0x10,1348	SLI4_IWR_WQE_APPID		= 0x10,1349	SLI4_IWR_WQE_WQES		= 0x80,1350	SLI4_IWR_WQE_PU_SHFT		= 4,1351	SLI4_IWR_WQE_CT_SHFT		= 2,1352	SLI4_IWR_WQE_BS_SHFT		= 4,1353	SLI4_IWR_WQE_LEN_LOC_BIT1	= 0x80,1354	SLI4_IWR_WQE_LEN_LOC_BIT2	= 0x1,1355};1356 1357struct sli4_fcp_iwrite64_wqe {1358	struct sli4_bde	bde;1359	__le16		payload_offset_length;1360	__le16		fcp_cmd_buffer_length;1361	__le16		total_transfer_length;1362	__le16		initial_transfer_length;1363	__le16		xri_tag;1364	__le16		context_tag;1365	u8		dif_ct_bs_byte;1366	u8		command;1367	u8		class_pu_byte;1368	u8		timer;1369	__le32		abort_tag;1370	__le16		request_tag;1371	__le16		rsvd34;1372	u8		len_loc1_byte;1373	u8		qosd_xbl_hlm_iod_dbde_wqes;1374	u8		eat_xc_ccpe;1375	u8		ccp;1376	u8		cmd_type_byte;1377	u8		rsvd41;1378	__le16		cq_id;1379	__le32		remote_n_port_id_dword;1380	struct sli4_bde	first_data_bde;1381};1382 1383struct sli4_fcp_128byte_wqe {1384	u32 dw[32];1385};1386 1387/* WQE used to create an FCP target receive */1388enum sli4_trcv_wqe_flags {1389	SLI4_TRCV_WQE_DBDE		= 0x40,1390	SLI4_TRCV_WQE_XBL		= 0x8,1391	SLI4_TRCV_WQE_AR		= 0x8,1392	SLI4_TRCV_WQE_XC		= 0x20,1393	SLI4_TRCV_WQE_IOD		= 0x20,1394	SLI4_TRCV_WQE_HLM		= 0x10,1395	SLI4_TRCV_WQE_DNRX		= 0x10,1396	SLI4_TRCV_WQE_CCPE		= 0x80,1397	SLI4_TRCV_WQE_EAT		= 0x10,1398	SLI4_TRCV_WQE_APPID		= 0x10,1399	SLI4_TRCV_WQE_WQES		= 0x80,1400	SLI4_TRCV_WQE_PU_SHFT		= 4,1401	SLI4_TRCV_WQE_CT_SHFT		= 2,1402	SLI4_TRCV_WQE_BS_SHFT		= 4,1403	SLI4_TRCV_WQE_LEN_LOC_BIT2	= 0x1,1404};1405 1406struct sli4_fcp_treceive64_wqe {1407	struct sli4_bde	bde;1408	__le32		payload_offset_length;1409	__le32		relative_offset;1410	union {1411		__le16	sec_xri_tag;1412		__le16	rsvd;1413		__le32	dword;1414	} dword5;1415	__le16		xri_tag;1416	__le16		context_tag;1417	u8		dif_ct_bs_byte;1418	u8		command;1419	u8		class_ar_pu_byte;1420	u8		timer;1421	__le32		abort_tag;1422	__le16		request_tag;1423	__le16		remote_xid;1424	u8		lloc1_appid;1425	u8		qosd_xbl_hlm_iod_dbde_wqes;1426	u8		eat_xc_ccpe;1427	u8		ccp;1428	u8		cmd_type_byte;1429	u8		rsvd41;1430	__le16		cq_id;1431	__le32		fcp_data_receive_length;1432	struct sli4_bde	first_data_bde;1433};1434 1435/* WQE used to create an FCP target response */1436enum sli4_trsp_wqe_flags {1437	SLI4_TRSP_WQE_AG	= 0x8,1438	SLI4_TRSP_WQE_DBDE	= 0x40,1439	SLI4_TRSP_WQE_XBL	= 0x8,1440	SLI4_TRSP_WQE_XC	= 0x20,1441	SLI4_TRSP_WQE_HLM	= 0x10,1442	SLI4_TRSP_WQE_DNRX	= 0x10,1443	SLI4_TRSP_WQE_CCPE	= 0x80,1444	SLI4_TRSP_WQE_EAT	= 0x10,1445	SLI4_TRSP_WQE_APPID	= 0x10,1446	SLI4_TRSP_WQE_WQES	= 0x80,1447};1448 1449struct sli4_fcp_trsp64_wqe {1450	struct sli4_bde	bde;1451	__le32		fcp_response_length;1452	__le32		rsvd12;1453	__le32		dword5;1454	__le16		xri_tag;1455	__le16		rpi;1456	u8		ct_dnrx_byte;1457	u8		command;1458	u8		class_ag_byte;1459	u8		timer;1460	__le32		abort_tag;1461	__le16		request_tag;1462	__le16		remote_xid;1463	u8		lloc1_appid;1464	u8		qosd_xbl_hlm_dbde_wqes;1465	u8		eat_xc_ccpe;1466	u8		ccp;1467	u8		cmd_type_byte;1468	u8		rsvd41;1469	__le16		cq_id;1470	__le32		rsvd44;1471	__le32		rsvd48;1472	__le32		rsvd52;1473	__le32		rsvd56;1474};1475 1476/* WQE used to create an FCP target send (DATA IN). */1477enum sli4_tsend_wqe_flags {1478	SLI4_TSEND_WQE_XBL	= 0x8,1479	SLI4_TSEND_WQE_DBDE	= 0x40,1480	SLI4_TSEND_WQE_IOD	= 0x20,1481	SLI4_TSEND_WQE_QOSD	= 0x2,1482	SLI4_TSEND_WQE_HLM	= 0x10,1483	SLI4_TSEND_WQE_PU_SHFT	= 4,1484	SLI4_TSEND_WQE_AR	= 0x8,1485	SLI4_TSEND_CT_SHFT	= 2,1486	SLI4_TSEND_BS_SHFT	= 4,1487	SLI4_TSEND_LEN_LOC_BIT2 = 0x1,1488	SLI4_TSEND_CCPE		= 0x80,1489	SLI4_TSEND_APPID_VALID	= 0x20,1490	SLI4_TSEND_WQES		= 0x80,1491	SLI4_TSEND_XC		= 0x20,1492	SLI4_TSEND_EAT		= 0x10,1493};1494 1495struct sli4_fcp_tsend64_wqe {1496	struct sli4_bde	bde;1497	__le32		payload_offset_length;1498	__le32		relative_offset;1499	__le32		dword5;1500	__le16		xri_tag;1501	__le16		rpi;1502	u8		ct_byte;1503	u8		command;1504	u8		class_pu_ar_byte;1505	u8		timer;1506	__le32		abort_tag;1507	__le16		request_tag;1508	__le16		remote_xid;1509	u8		dw10byte0;1510	u8		ll_qd_xbl_hlm_iod_dbde;1511	u8		dw10byte2;1512	u8		ccp;1513	u8		cmd_type_byte;1514	u8		rsvd45;1515	__le16		cq_id;1516	__le32		fcp_data_transmit_length;1517	struct sli4_bde	first_data_bde;1518};1519 1520/* WQE used to create a general request. */1521enum sli4_gen_req_wqe_flags {1522	SLI4_GEN_REQ64_WQE_XBL	= 0x8,1523	SLI4_GEN_REQ64_WQE_DBDE	= 0x40,1524	SLI4_GEN_REQ64_WQE_IOD	= 0x20,1525	SLI4_GEN_REQ64_WQE_QOSD	= 0x2,1526	SLI4_GEN_REQ64_WQE_HLM	= 0x10,1527	SLI4_GEN_REQ64_CT_SHFT	= 2,1528};1529 1530struct sli4_gen_request64_wqe {1531	struct sli4_bde	bde;1532	__le32		request_payload_length;1533	__le32		relative_offset;1534	u8		rsvd17;1535	u8		df_ctl;1536	u8		type;1537	u8		r_ctl;1538	__le16		xri_tag;1539	__le16		context_tag;1540	u8		ct_byte;1541	u8		command;1542	u8		class_byte;1543	u8		timer;1544	__le32		abort_tag;1545	__le16		request_tag;1546	__le16		rsvd34;1547	u8		dw10flags0;1548	u8		dw10flags1;1549	u8		dw10flags2;1550	u8		ccp;1551	u8		cmd_type_byte;1552	u8		rsvd41;1553	__le16		cq_id;1554	__le32		remote_n_port_id_dword;1555	__le32		rsvd48;1556	__le32		rsvd52;1557	__le32		max_response_payload_length;1558};1559 1560/* WQE used to create a send frame request */1561enum sli4_sf_wqe_flags {1562	SLI4_SF_WQE_DBDE	= 0x40,1563	SLI4_SF_PU		= 0x30,1564	SLI4_SF_CT		= 0xc,1565	SLI4_SF_QOSD		= 0x2,1566	SLI4_SF_LEN_LOC_BIT1	= 0x80,1567	SLI4_SF_LEN_LOC_BIT2	= 0x1,1568	SLI4_SF_XC		= 0x20,1569	SLI4_SF_XBL		= 0x8,1570};1571 1572struct sli4_send_frame_wqe {1573	struct sli4_bde	bde;1574	__le32		frame_length;1575	__le32		fc_header_0_1[2];1576	__le16		xri_tag;1577	__le16		context_tag;1578	u8		ct_byte;1579	u8		command;1580	u8		dw7flags0;1581	u8		timer;1582	__le32		abort_tag;1583	__le16		request_tag;1584	u8		eof;1585	u8		sof;1586	u8		dw10flags0;1587	u8		dw10flags1;1588	u8		dw10flags2;1589	u8		ccp;1590	u8		cmd_type_byte;1591	u8		rsvd41;1592	__le16		cq_id;1593	__le32		fc_header_2_5[4];1594};1595 1596/* WQE used to create a transmit sequence */1597enum sli4_seq_wqe_flags {1598	SLI4_SEQ_WQE_DBDE		= 0x4000,1599	SLI4_SEQ_WQE_XBL		= 0x800,1600	SLI4_SEQ_WQE_SI			= 0x4,1601	SLI4_SEQ_WQE_FT			= 0x8,1602	SLI4_SEQ_WQE_XO			= 0x40,1603	SLI4_SEQ_WQE_LS			= 0x80,1604	SLI4_SEQ_WQE_DIF		= 0x3,1605	SLI4_SEQ_WQE_BS			= 0x70,1606	SLI4_SEQ_WQE_PU			= 0x30,1607	SLI4_SEQ_WQE_HLM		= 0x1000,1608	SLI4_SEQ_WQE_IOD_SHIFT		= 13,1609	SLI4_SEQ_WQE_CT_SHIFT		= 2,1610	SLI4_SEQ_WQE_LEN_LOC_SHIFT	= 7,1611};1612 1613struct sli4_xmit_sequence64_wqe {1614	struct sli4_bde	bde;1615	__le32		remote_n_port_id_dword;1616	__le32		relative_offset;1617	u8		dw5flags0;1618	u8		df_ctl;1619	u8		type;1620	u8		r_ctl;1621	__le16		xri_tag;1622	__le16		context_tag;1623	u8		dw7flags0;1624	u8		command;1625	u8		dw7flags1;1626	u8		timer;1627	__le32		abort_tag;1628	__le16		request_tag;1629	__le16		remote_xid;1630	__le16		dw10w0;1631	u8		dw10flags0;1632	u8		ccp;1633	u8		cmd_type_wqec_byte;1634	u8		rsvd45;1635	__le16		cq_id;1636	__le32		sequence_payload_len;1637	__le32		rsvd48;1638	__le32		rsvd52;1639	__le32		rsvd56;1640};1641 1642/*1643 * WQE used unblock the specified XRI and to release1644 * it to the SLI Port's free pool.1645 */1646enum sli4_requeue_wqe_flags {1647	SLI4_REQU_XRI_WQE_XC	= 0x20,1648	SLI4_REQU_XRI_WQE_QOSD	= 0x2,1649};1650 1651struct sli4_requeue_xri_wqe {1652	__le32		rsvd0;1653	__le32		rsvd4;1654	__le32		rsvd8;1655	__le32		rsvd12;1656	__le32		rsvd16;1657	__le32		rsvd20;1658	__le16		xri_tag;1659	__le16		context_tag;1660	u8		ct_byte;1661	u8		command;1662	u8		class_byte;1663	u8		timer;1664	__le32		rsvd32;1665	__le16		request_tag;1666	__le16		rsvd34;1667	__le16		flags0;1668	__le16		flags1;1669	__le16		flags2;1670	u8		ccp;1671	u8		cmd_type_wqec_byte;1672	u8		rsvd42;1673	__le16		cq_id;1674	__le32		rsvd44;1675	__le32		rsvd48;1676	__le32		rsvd52;1677	__le32		rsvd56;1678};1679 1680/* WQE used to create a BLS response */1681enum sli4_bls_rsp_wqe_flags {1682	SLI4_BLS_RSP_RID		= 0xffffff,1683	SLI4_BLS_RSP_WQE_AR		= 0x40000000,1684	SLI4_BLS_RSP_WQE_CT_SHFT	= 2,1685	SLI4_BLS_RSP_WQE_QOSD		= 0x2,1686	SLI4_BLS_RSP_WQE_HLM		= 0x10,1687};1688 1689struct sli4_xmit_bls_rsp_wqe {1690	__le32		payload_word0;1691	__le16		rx_id;1692	__le16		ox_id;1693	__le16		high_seq_cnt;1694	__le16		low_seq_cnt;1695	__le32		rsvd12;1696	__le32		local_n_port_id_dword;1697	__le32		remote_id_dword;1698	__le16		xri_tag;1699	__le16		context_tag;1700	u8		dw8flags0;1701	u8		command;1702	u8		dw8flags1;1703	u8		timer;1704	__le32		abort_tag;1705	__le16		request_tag;1706	__le16		rsvd38;1707	u8		dw11flags0;1708	u8		dw11flags1;1709	u8		dw11flags2;1710	u8		ccp;1711	u8		dw12flags0;1712	u8		rsvd45;1713	__le16		cq_id;1714	__le16		temporary_rpi;1715	u8		rsvd50;1716	u8		rsvd51;1717	__le32		rsvd52;1718	__le32		rsvd56;1719	__le32		rsvd60;1720};1721 1722enum sli_bls_type {1723	SLI4_SLI_BLS_ACC,1724	SLI4_SLI_BLS_RJT,1725	SLI4_SLI_BLS_MAX1726};1727 1728struct sli_bls_payload {1729	enum sli_bls_type	type;1730	__le16			ox_id;1731	__le16			rx_id;1732	union {1733		struct {1734			u8	seq_id_validity;1735			u8	seq_id_last;1736			u8	rsvd2;1737			u8	rsvd3;1738			u16	ox_id;1739			u16	rx_id;1740			__le16	low_seq_cnt;1741			__le16	high_seq_cnt;1742		} acc;1743		struct {1744			u8	vendor_unique;1745			u8	reason_explanation;1746			u8	reason_code;1747			u8	rsvd3;1748		} rjt;1749	} u;1750};1751 1752/* WQE used to create an ELS response */1753 1754enum sli4_els_rsp_flags {1755	SLI4_ELS_SID		= 0xffffff,1756	SLI4_ELS_RID		= 0xffffff,1757	SLI4_ELS_DBDE		= 0x40,1758	SLI4_ELS_XBL		= 0x8,1759	SLI4_ELS_IOD		= 0x20,1760	SLI4_ELS_QOSD		= 0x2,1761	SLI4_ELS_XC		= 0x20,1762	SLI4_ELS_CT_OFFSET	= 0X2,1763	SLI4_ELS_SP		= 0X1000000,1764	SLI4_ELS_HLM		= 0X10,1765};1766 1767struct sli4_xmit_els_rsp64_wqe {1768	struct sli4_bde	els_response_payload;1769	__le32		els_response_payload_length;1770	__le32		sid_dw;1771	__le32		rid_dw;1772	__le16		xri_tag;1773	__le16		context_tag;1774	u8		ct_byte;1775	u8		command;1776	u8		class_byte;1777	u8		timer;1778	__le32		abort_tag;1779	__le16		request_tag;1780	__le16		ox_id;1781	u8		flags1;1782	u8		flags2;1783	u8		flags3;1784	u8		flags4;1785	u8		cmd_type_wqec;1786	u8		rsvd34;1787	__le16		cq_id;1788	__le16		temporary_rpi;1789	__le16		rsvd38;1790	u32		rsvd40;1791	u32		rsvd44;1792	u32		rsvd48;1793};1794 1795/* Local Reject Reason Codes */1796enum sli4_fc_local_rej_codes {1797	SLI4_FC_LOCAL_REJECT_UNKNOWN,1798	SLI4_FC_LOCAL_REJECT_MISSING_CONTINUE,1799	SLI4_FC_LOCAL_REJECT_SEQUENCE_TIMEOUT,1800	SLI4_FC_LOCAL_REJECT_INTERNAL_ERROR,1801	SLI4_FC_LOCAL_REJECT_INVALID_RPI,1802	SLI4_FC_LOCAL_REJECT_NO_XRI,1803	SLI4_FC_LOCAL_REJECT_ILLEGAL_COMMAND,1804	SLI4_FC_LOCAL_REJECT_XCHG_DROPPED,1805	SLI4_FC_LOCAL_REJECT_ILLEGAL_FIELD,1806	SLI4_FC_LOCAL_REJECT_RPI_SUSPENDED,1807	SLI4_FC_LOCAL_REJECT_RSVD,1808	SLI4_FC_LOCAL_REJECT_RSVD1,1809	SLI4_FC_LOCAL_REJECT_NO_ABORT_MATCH,1810	SLI4_FC_LOCAL_REJECT_TX_DMA_FAILED,1811	SLI4_FC_LOCAL_REJECT_RX_DMA_FAILED,1812	SLI4_FC_LOCAL_REJECT_ILLEGAL_FRAME,1813	SLI4_FC_LOCAL_REJECT_RSVD2,1814	SLI4_FC_LOCAL_REJECT_NO_RESOURCES, //0x111815	SLI4_FC_LOCAL_REJECT_FCP_CONF_FAILURE,1816	SLI4_FC_LOCAL_REJECT_ILLEGAL_LENGTH,1817	SLI4_FC_LOCAL_REJECT_UNSUPPORTED_FEATURE,1818	SLI4_FC_LOCAL_REJECT_ABORT_IN_PROGRESS,1819	SLI4_FC_LOCAL_REJECT_ABORT_REQUESTED,1820	SLI4_FC_LOCAL_REJECT_RCV_BUFFER_TIMEOUT,1821	SLI4_FC_LOCAL_REJECT_LOOP_OPEN_FAILURE,1822	SLI4_FC_LOCAL_REJECT_RSVD3,1823	SLI4_FC_LOCAL_REJECT_LINK_DOWN,1824	SLI4_FC_LOCAL_REJECT_CORRUPTED_DATA,1825	SLI4_FC_LOCAL_REJECT_CORRUPTED_RPI,1826	SLI4_FC_LOCAL_REJECT_OUTOFORDER_DATA,1827	SLI4_FC_LOCAL_REJECT_OUTOFORDER_ACK,1828	SLI4_FC_LOCAL_REJECT_DUP_FRAME,1829	SLI4_FC_LOCAL_REJECT_LINK_CONTROL_FRAME, //0x201830	SLI4_FC_LOCAL_REJECT_BAD_HOST_ADDRESS,1831	SLI4_FC_LOCAL_REJECT_RSVD4,1832	SLI4_FC_LOCAL_REJECT_MISSING_HDR_BUFFER,1833	SLI4_FC_LOCAL_REJECT_MSEQ_CHAIN_CORRUPTED,1834	SLI4_FC_LOCAL_REJECT_ABORTMULT_REQUESTED,1835	SLI4_FC_LOCAL_REJECT_BUFFER_SHORTAGE	= 0x28,1836	SLI4_FC_LOCAL_REJECT_RCV_XRIBUF_WAITING,1837	SLI4_FC_LOCAL_REJECT_INVALID_VPI	= 0x2e,1838	SLI4_FC_LOCAL_REJECT_NO_FPORT_DETECTED,1839	SLI4_FC_LOCAL_REJECT_MISSING_XRIBUF,1840	SLI4_FC_LOCAL_REJECT_RSVD5,1841	SLI4_FC_LOCAL_REJECT_INVALID_XRI,1842	SLI4_FC_LOCAL_REJECT_INVALID_RELOFFSET	= 0x40,1843	SLI4_FC_LOCAL_REJECT_MISSING_RELOFFSET,1844	SLI4_FC_LOCAL_REJECT_INSUFF_BUFFERSPACE,1845	SLI4_FC_LOCAL_REJECT_MISSING_SI,1846	SLI4_FC_LOCAL_REJECT_MISSING_ES,1847	SLI4_FC_LOCAL_REJECT_INCOMPLETE_XFER,1848	SLI4_FC_LOCAL_REJECT_SLER_FAILURE,1849	SLI4_FC_LOCAL_REJECT_SLER_CMD_RCV_FAILURE,1850	SLI4_FC_LOCAL_REJECT_SLER_REC_RJT_ERR,1851	SLI4_FC_LOCAL_REJECT_SLER_REC_SRR_RETRY_ERR,1852	SLI4_FC_LOCAL_REJECT_SLER_SRR_RJT_ERR,1853	SLI4_FC_LOCAL_REJECT_RSVD6,1854	SLI4_FC_LOCAL_REJECT_SLER_RRQ_RJT_ERR,1855	SLI4_FC_LOCAL_REJECT_SLER_RRQ_RETRY_ERR,1856	SLI4_FC_LOCAL_REJECT_SLER_ABTS_ERR,1857};1858 1859enum sli4_async_rcqe_flags {1860	SLI4_RACQE_RQ_EL_INDX	= 0xfff,1861	SLI4_RACQE_FCFI		= 0x3f,1862	SLI4_RACQE_HDPL		= 0x3f,1863	SLI4_RACQE_RQ_ID	= 0xffc0,1864};1865 1866struct sli4_fc_async_rcqe {1867	u8		rsvd0;1868	u8		status;1869	__le16		rq_elmt_indx_word;1870	__le32		rsvd4;1871	__le16		fcfi_rq_id_word;1872	__le16		data_placement_length;1873	u8		sof_byte;1874	u8		eof_byte;1875	u8		code;1876	u8		hdpl_byte;1877};1878 1879struct sli4_fc_async_rcqe_v1 {1880	u8		rsvd0;1881	u8		status;1882	__le16		rq_elmt_indx_word;1883	u8		fcfi_byte;1884	u8		rsvd5;1885	__le16		rsvd6;1886	__le16		rq_id;1887	__le16		data_placement_length;1888	u8		sof_byte;1889	u8		eof_byte;1890	u8		code;1891	u8		hdpl_byte;1892};1893 1894enum sli4_fc_async_rq_status {1895	SLI4_FC_ASYNC_RQ_SUCCESS = 0x10,1896	SLI4_FC_ASYNC_RQ_BUF_LEN_EXCEEDED,1897	SLI4_FC_ASYNC_RQ_INSUFF_BUF_NEEDED,1898	SLI4_FC_ASYNC_RQ_INSUFF_BUF_FRM_DISC,1899	SLI4_FC_ASYNC_RQ_DMA_FAILURE,1900};1901 1902#define SLI4_RCQE_RQ_EL_INDX	0xfff1903 1904struct sli4_fc_coalescing_rcqe {1905	u8		rsvd0;1906	u8		status;1907	__le16		rq_elmt_indx_word;1908	__le32		rsvd4;1909	__le16		rq_id;1910	__le16		seq_placement_length;1911	__le16		rsvd14;1912	u8		code;1913	u8		vld_byte;1914};1915 1916#define SLI4_FC_COALESCE_RQ_SUCCESS		0x101917#define SLI4_FC_COALESCE_RQ_INSUFF_XRI_NEEDED	0x181918 1919enum sli4_optimized_write_cmd_cqe_flags {1920	SLI4_OCQE_RQ_EL_INDX	= 0x7f,		/* DW0 bits 16:30 */1921	SLI4_OCQE_FCFI		= 0x3f,		/* DW1 bits 0:6 */1922	SLI4_OCQE_OOX		= 1 << 6,	/* DW1 bit 15 */1923	SLI4_OCQE_AGXR		= 1 << 7,	/* DW1 bit 16 */1924	SLI4_OCQE_HDPL		= 0x3f,		/* DW3 bits 24:29*/1925};1926 1927struct sli4_fc_optimized_write_cmd_cqe {1928	u8		rsvd0;1929	u8		status;1930	__le16		w1;1931	u8		flags0;1932	u8		flags1;1933	__le16		xri;1934	__le16		rq_id;1935	__le16		data_placement_length;1936	__le16		rpi;1937	u8		code;1938	u8		hdpl_vld;1939};1940 1941#define	SLI4_OCQE_XB		0x101942 1943struct sli4_fc_optimized_write_data_cqe {1944	u8		hw_status;1945	u8		status;1946	__le16		xri;1947	__le32		total_data_placed;1948	__le32		extended_status;1949	__le16		rsvd12;1950	u8		code;1951	u8		flags;1952};1953 1954struct sli4_fc_xri_aborted_cqe {1955	u8		rsvd0;1956	u8		status;1957	__le16		rsvd2;1958	__le32		extended_status;1959	__le16		xri;1960	__le16		remote_xid;1961	__le16		rsvd12;1962	u8		code;1963	u8		flags;1964};1965 1966enum sli4_generic_ctx {1967	SLI4_GENERIC_CONTEXT_RPI,1968	SLI4_GENERIC_CONTEXT_VPI,1969	SLI4_GENERIC_CONTEXT_VFI,1970	SLI4_GENERIC_CONTEXT_FCFI,1971};1972 1973#define SLI4_GENERIC_CLASS_CLASS_2		0x11974#define SLI4_GENERIC_CLASS_CLASS_3		0x21975 1976#define SLI4_ELS_REQUEST64_DIR_WRITE		0x01977#define SLI4_ELS_REQUEST64_DIR_READ		0x11978 1979enum sli4_els_request {1980	SLI4_ELS_REQUEST64_OTHER,1981	SLI4_ELS_REQUEST64_LOGO,1982	SLI4_ELS_REQUEST64_FDISC,1983	SLI4_ELS_REQUEST64_FLOGIN,1984	SLI4_ELS_REQUEST64_PLOGI,1985};1986 1987enum sli4_els_cmd_type {1988	SLI4_ELS_REQUEST64_CMD_GEN		= 0x08,1989	SLI4_ELS_REQUEST64_CMD_NON_FABRIC	= 0x0c,1990	SLI4_ELS_REQUEST64_CMD_FABRIC		= 0x0d,1991};1992 1993#define SLI_PAGE_SIZE				SZ_4K1994 1995#define SLI4_BMBX_TIMEOUT_MSEC			300001996#define SLI4_FW_READY_TIMEOUT_MSEC		300001997 1998#define SLI4_BMBX_DELAY_US			1000	/* 1 ms */1999#define SLI4_INIT_PORT_DELAY_US			10000	/* 10 ms */2000 2001static inline u322002sli_page_count(size_t bytes, u32 page_size)2003{2004	if (!page_size)2005		return 0;2006 2007	return (bytes + (page_size - 1)) >> __ffs(page_size);2008}2009 2010/*************************************************************************2011 * SLI-4 mailbox command formats and definitions2012 */2013 2014struct sli4_mbox_command_header {2015	u8	resvd0;2016	u8	command;2017	__le16	status;	/* Port writes to indicate success/fail */2018};2019 2020enum sli4_mbx_cmd_value {2021	SLI4_MBX_CMD_CONFIG_LINK	= 0x07,2022	SLI4_MBX_CMD_DUMP		= 0x17,2023	SLI4_MBX_CMD_DOWN_LINK		= 0x06,2024	SLI4_MBX_CMD_INIT_LINK		= 0x05,2025	SLI4_MBX_CMD_INIT_VFI		= 0xa3,2026	SLI4_MBX_CMD_INIT_VPI		= 0xa4,2027	SLI4_MBX_CMD_POST_XRI		= 0xa7,2028	SLI4_MBX_CMD_RELEASE_XRI	= 0xac,2029	SLI4_MBX_CMD_READ_CONFIG	= 0x0b,2030	SLI4_MBX_CMD_READ_STATUS	= 0x0e,2031	SLI4_MBX_CMD_READ_NVPARMS	= 0x02,2032	SLI4_MBX_CMD_READ_REV		= 0x11,2033	SLI4_MBX_CMD_READ_LNK_STAT	= 0x12,2034	SLI4_MBX_CMD_READ_SPARM64	= 0x8d,2035	SLI4_MBX_CMD_READ_TOPOLOGY	= 0x95,2036	SLI4_MBX_CMD_REG_FCFI		= 0xa0,2037	SLI4_MBX_CMD_REG_FCFI_MRQ	= 0xaf,2038	SLI4_MBX_CMD_REG_RPI		= 0x93,2039	SLI4_MBX_CMD_REG_RX_RQ		= 0xa6,2040	SLI4_MBX_CMD_REG_VFI		= 0x9f,2041	SLI4_MBX_CMD_REG_VPI		= 0x96,2042	SLI4_MBX_CMD_RQST_FEATURES	= 0x9d,2043	SLI4_MBX_CMD_SLI_CONFIG		= 0x9b,2044	SLI4_MBX_CMD_UNREG_FCFI		= 0xa2,2045	SLI4_MBX_CMD_UNREG_RPI		= 0x14,2046	SLI4_MBX_CMD_UNREG_VFI		= 0xa1,2047	SLI4_MBX_CMD_UNREG_VPI		= 0x97,2048	SLI4_MBX_CMD_WRITE_NVPARMS	= 0x03,2049	SLI4_MBX_CMD_CFG_AUTO_XFER_RDY	= 0xad,2050};2051 2052enum sli4_mbx_status {2053	SLI4_MBX_STATUS_SUCCESS		= 0x0000,2054	SLI4_MBX_STATUS_FAILURE		= 0x0001,2055	SLI4_MBX_STATUS_RPI_NOT_REG	= 0x1400,2056};2057 2058/* CONFIG_LINK - configure link-oriented parameters,2059 * such as default N_Port_ID address and various timers2060 */2061enum sli4_cmd_config_link_flags {2062	SLI4_CFG_LINK_BBSCN = 0xf00,2063	SLI4_CFG_LINK_CSCN  = 0x1000,2064};2065 2066struct sli4_cmd_config_link {2067	struct sli4_mbox_command_header	hdr;2068	u8		maxbbc;2069	u8		rsvd5;2070	u8		rsvd6;2071	u8		rsvd7;2072	u8		alpa;2073	__le16		n_port_id;2074	u8		rsvd11;2075	__le32		rsvd12;2076	__le32		e_d_tov;2077	__le32		lp_tov;2078	__le32		r_a_tov;2079	__le32		r_t_tov;2080	__le32		al_tov;2081	__le32		rsvd36;2082	__le32		bbscn_dword;2083};2084 2085#define SLI4_DUMP4_TYPE		0xf2086 2087#define SLI4_WKI_TAG_SAT_TEM	0x10402088 2089struct sli4_cmd_dump4 {2090	struct sli4_mbox_command_header	hdr;2091	__le32		type_dword;2092	__le16		wki_selection;2093	__le16		rsvd10;2094	__le32		rsvd12;2095	__le32		returned_byte_cnt;2096	__le32		resp_data[59];2097};2098 2099/* INIT_LINK - initialize the link for a FC port */2100enum sli4_init_link_flags {2101	SLI4_INIT_LINK_F_LOOPBACK	= 1 << 0,2102 2103	SLI4_INIT_LINK_F_P2P_ONLY	= 1 << 1,2104	SLI4_INIT_LINK_F_FCAL_ONLY	= 2 << 1,2105	SLI4_INIT_LINK_F_FCAL_FAIL_OVER	= 0 << 1,2106	SLI4_INIT_LINK_F_P2P_FAIL_OVER	= 1 << 1,2107 2108	SLI4_INIT_LINK_F_UNFAIR		= 1 << 6,2109	SLI4_INIT_LINK_F_NO_LIRP	= 1 << 7,2110	SLI4_INIT_LINK_F_LOOP_VALID_CHK	= 1 << 8,2111	SLI4_INIT_LINK_F_NO_LISA	= 1 << 9,2112	SLI4_INIT_LINK_F_FAIL_OVER	= 1 << 10,2113	SLI4_INIT_LINK_F_FIXED_SPEED	= 1 << 11,2114	SLI4_INIT_LINK_F_PICK_HI_ALPA	= 1 << 15,2115 2116};2117 2118enum sli4_fc_link_speed {2119	SLI4_LINK_SPEED_1G = 1,2120	SLI4_LINK_SPEED_2G,2121	SLI4_LINK_SPEED_AUTO_1_2,2122	SLI4_LINK_SPEED_4G,2123	SLI4_LINK_SPEED_AUTO_4_1,2124	SLI4_LINK_SPEED_AUTO_4_2,2125	SLI4_LINK_SPEED_AUTO_4_2_1,2126	SLI4_LINK_SPEED_8G,2127	SLI4_LINK_SPEED_AUTO_8_1,2128	SLI4_LINK_SPEED_AUTO_8_2,2129	SLI4_LINK_SPEED_AUTO_8_2_1,2130	SLI4_LINK_SPEED_AUTO_8_4,2131	SLI4_LINK_SPEED_AUTO_8_4_1,2132	SLI4_LINK_SPEED_AUTO_8_4_2,2133	SLI4_LINK_SPEED_10G,2134	SLI4_LINK_SPEED_16G,2135	SLI4_LINK_SPEED_AUTO_16_8_4,2136	SLI4_LINK_SPEED_AUTO_16_8,2137	SLI4_LINK_SPEED_32G,2138	SLI4_LINK_SPEED_AUTO_32_16_8,2139	SLI4_LINK_SPEED_AUTO_32_16,2140	SLI4_LINK_SPEED_64G,2141	SLI4_LINK_SPEED_AUTO_64_32_16,2142	SLI4_LINK_SPEED_AUTO_64_32,2143	SLI4_LINK_SPEED_128G,2144	SLI4_LINK_SPEED_AUTO_128_64_32,2145	SLI4_LINK_SPEED_AUTO_128_64,2146};2147 2148struct sli4_cmd_init_link {2149	struct sli4_mbox_command_header       hdr;2150	__le32	sel_reset_al_pa_dword;2151	__le32	flags0;2152	__le32	link_speed_sel_code;2153};2154 2155/* INIT_VFI - initialize the VFI resource */2156enum sli4_init_vfi_flags {2157	SLI4_INIT_VFI_FLAG_VP	= 0x1000,2158	SLI4_INIT_VFI_FLAG_VF	= 0x2000,2159	SLI4_INIT_VFI_FLAG_VT	= 0x4000,2160	SLI4_INIT_VFI_FLAG_VR	= 0x8000,2161 2162	SLI4_INIT_VFI_VFID	= 0x1fff,2163	SLI4_INIT_VFI_PRI	= 0xe000,2164 2165	SLI4_INIT_VFI_HOP_COUNT = 0xff000000,2166};2167 2168struct sli4_cmd_init_vfi {2169	struct sli4_mbox_command_header	hdr;2170	__le16		vfi;2171	__le16		flags0_word;2172	__le16		fcfi;2173	__le16		vpi;2174	__le32		vf_id_pri_dword;2175	__le32		hop_cnt_dword;2176};2177 2178/* INIT_VPI - initialize the VPI resource */2179struct sli4_cmd_init_vpi {2180	struct sli4_mbox_command_header	hdr;2181	__le16		vpi;2182	__le16		vfi;2183};2184 2185/* POST_XRI - post XRI resources to the SLI Port */2186enum sli4_post_xri_flags {2187	SLI4_POST_XRI_COUNT	= 0xfff,2188	SLI4_POST_XRI_FLAG_ENX	= 0x1000,2189	SLI4_POST_XRI_FLAG_DL	= 0x2000,2190	SLI4_POST_XRI_FLAG_DI	= 0x4000,2191	SLI4_POST_XRI_FLAG_VAL	= 0x8000,2192};2193 2194struct sli4_cmd_post_xri {2195	struct sli4_mbox_command_header	hdr;2196	__le16		xri_base;2197	__le16		xri_count_flags;2198};2199 2200/* RELEASE_XRI - Release XRI resources from the SLI Port */2201enum sli4_release_xri_flags {2202	SLI4_RELEASE_XRI_REL_XRI_CNT	= 0x1f,2203	SLI4_RELEASE_XRI_COUNT		= 0x1f,2204};2205 2206struct sli4_cmd_release_xri {2207	struct sli4_mbox_command_header	hdr;2208	__le16		rel_xri_count_word;2209	__le16		xri_count_word;2210 2211	struct {2212		__le16	xri_tag0;2213		__le16	xri_tag1;2214	} xri_tbl[62];2215};2216 2217/* READ_CONFIG - read SLI port configuration parameters */2218struct sli4_cmd_read_config {2219	struct sli4_mbox_command_header	hdr;2220};2221 2222enum sli4_read_cfg_resp_flags {2223	SLI4_READ_CFG_RESP_RESOURCE_EXT = 0x80000000,	/* DW1 */2224	SLI4_READ_CFG_RESP_TOPOLOGY	= 0xff000000,	/* DW2 */2225};2226 2227enum sli4_read_cfg_topo {2228	SLI4_READ_CFG_TOPO_FC		= 0x1,	/* FC topology unknown */2229	SLI4_READ_CFG_TOPO_NON_FC_AL	= 0x2,	/* FC point-to-point or fabric */2230	SLI4_READ_CFG_TOPO_FC_AL	= 0x3,	/* FC-AL topology */2231};2232 2233/* Link Module Type */2234enum sli4_read_cfg_lmt {2235	SLI4_LINK_MODULE_TYPE_1GB	= 0x0004,2236	SLI4_LINK_MODULE_TYPE_2GB	= 0x0008,2237	SLI4_LINK_MODULE_TYPE_4GB	= 0x0040,2238	SLI4_LINK_MODULE_TYPE_8GB	= 0x0080,2239	SLI4_LINK_MODULE_TYPE_16GB	= 0x0200,2240	SLI4_LINK_MODULE_TYPE_32GB	= 0x0400,2241	SLI4_LINK_MODULE_TYPE_64GB	= 0x0800,2242	SLI4_LINK_MODULE_TYPE_128GB	= 0x1000,2243};2244 2245struct sli4_rsp_read_config {2246	struct sli4_mbox_command_header	hdr;2247	__le32		ext_dword;2248	__le32		topology_dword;2249	__le32		resvd8;2250	__le16		e_d_tov;2251	__le16		resvd14;2252	__le32		resvd16;2253	__le16		r_a_tov;2254	__le16		resvd22;2255	__le32		resvd24;2256	__le32		resvd28;2257	__le16		lmt;2258	__le16		resvd34;2259	__le32		resvd36;2260	__le32		resvd40;2261	__le16		xri_base;2262	__le16		xri_count;2263	__le16		rpi_base;2264	__le16		rpi_count;2265	__le16		vpi_base;2266	__le16		vpi_count;2267	__le16		vfi_base;2268	__le16		vfi_count;2269	__le16		resvd60;2270	__le16		fcfi_count;2271	__le16		rq_count;2272	__le16		eq_count;2273	__le16		wq_count;2274	__le16		cq_count;2275	__le32		pad[45];2276};2277 2278/* READ_NVPARMS - read SLI port configuration parameters */2279enum sli4_read_nvparms_flags {2280	SLI4_READ_NVPARAMS_HARD_ALPA	  = 0xff,2281	SLI4_READ_NVPARAMS_PREFERRED_D_ID = 0xffffff00,2282};2283 2284struct sli4_cmd_read_nvparms {2285	struct sli4_mbox_command_header	hdr;2286	__le32		resvd0;2287	__le32		resvd4;2288	__le32		resvd8;2289	__le32		resvd12;2290	u8		wwpn[8];2291	u8		wwnn[8];2292	__le32		hard_alpa_d_id;2293};2294 2295/* WRITE_NVPARMS - write SLI port configuration parameters */2296struct sli4_cmd_write_nvparms {2297	struct sli4_mbox_command_header	hdr;2298	__le32		resvd0;2299	__le32		resvd4;2300	__le32		resvd8;2301	__le32		resvd12;2302	u8		wwpn[8];2303	u8		wwnn[8];2304	__le32		hard_alpa_d_id;2305};2306 2307/* READ_REV - read the Port revision levels */2308enum {2309	SLI4_READ_REV_FLAG_SLI_LEVEL	= 0xf,2310	SLI4_READ_REV_FLAG_FCOEM	= 0x10,2311	SLI4_READ_REV_FLAG_CEEV		= 0x60,2312	SLI4_READ_REV_FLAG_VPD		= 0x2000,2313 2314	SLI4_READ_REV_AVAILABLE_LENGTH	= 0xffffff,2315};2316 2317struct sli4_cmd_read_rev {2318	struct sli4_mbox_command_header	hdr;2319	__le16			resvd0;2320	__le16			flags0_word;2321	__le32			first_hw_rev;2322	__le32			second_hw_rev;2323	__le32			resvd12;2324	__le32			third_hw_rev;2325	u8			fc_ph_low;2326	u8			fc_ph_high;2327	u8			feature_level_low;2328	u8			feature_level_high;2329	__le32			resvd24;2330	__le32			first_fw_id;2331	u8			first_fw_name[16];2332	__le32			second_fw_id;2333	u8			second_fw_name[16];2334	__le32			rsvd18[30];2335	__le32			available_length_dword;2336	struct sli4_dmaaddr	hostbuf;2337	__le32			returned_vpd_length;2338	__le32			actual_vpd_length;2339};2340 2341/* READ_SPARM64 - read the Port service parameters */2342#define SLI4_READ_SPARM64_WWPN_OFFSET	(4 * sizeof(u32))2343#define SLI4_READ_SPARM64_WWNN_OFFSET	(6 * sizeof(u32))2344 2345struct sli4_cmd_read_sparm64 {2346	struct sli4_mbox_command_header hdr;2347	__le32			resvd0;2348	__le32			resvd4;2349	struct sli4_bde		bde_64;2350	__le16			vpi;2351	__le16			resvd22;2352	__le16			port_name_start;2353	__le16			port_name_len;2354	__le16			node_name_start;2355	__le16			node_name_len;2356};2357 2358/* READ_TOPOLOGY - read the link event information */2359enum sli4_read_topo_e {2360	SLI4_READTOPO_ATTEN_TYPE	= 0xff,2361	SLI4_READTOPO_FLAG_IL		= 0x100,2362	SLI4_READTOPO_FLAG_PB_RECVD	= 0x200,2363 2364	SLI4_READTOPO_LINKSTATE_RECV	= 0x3,2365	SLI4_READTOPO_LINKSTATE_TRANS	= 0xc,2366	SLI4_READTOPO_LINKSTATE_MACHINE	= 0xf0,2367	SLI4_READTOPO_LINKSTATE_SPEED	= 0xff00,2368	SLI4_READTOPO_LINKSTATE_TF	= 0x40000000,2369	SLI4_READTOPO_LINKSTATE_LU	= 0x80000000,2370 2371	SLI4_READTOPO_SCN_BBSCN		= 0xf,2372	SLI4_READTOPO_SCN_CBBSCN	= 0xf0,2373 2374	SLI4_READTOPO_R_T_TOV		= 0x1ff,2375	SLI4_READTOPO_AL_TOV		= 0xf000,2376 2377	SLI4_READTOPO_PB_FLAG		= 0x80,2378 2379	SLI4_READTOPO_INIT_N_PORTID	= 0xffffff,2380};2381 2382#define SLI4_MIN_LOOP_MAP_BYTES	1282383 2384struct sli4_cmd_read_topology {2385	struct sli4_mbox_command_header	hdr;2386	__le32			event_tag;2387	__le32			dw2_attentype;2388	u8			topology;2389	u8			lip_type;2390	u8			lip_al_ps;2391	u8			al_pa_granted;2392	struct sli4_bde		bde_loop_map;2393	__le32			linkdown_state;2394	__le32			currlink_state;2395	u8			max_bbc;2396	u8			init_bbc;2397	u8			scn_flags;2398	u8			rsvd39;2399	__le16			dw10w0_al_rt_tov;2400	__le16			lp_tov;2401	u8			acquired_al_pa;2402	u8			pb_flags;2403	__le16			specified_al_pa;2404	__le32			dw12_init_n_port_id;2405};2406 2407enum sli4_read_topo_link {2408	SLI4_READ_TOPOLOGY_LINK_UP	= 0x1,2409	SLI4_READ_TOPOLOGY_LINK_DOWN,2410	SLI4_READ_TOPOLOGY_LINK_NO_ALPA,2411};2412 2413enum sli4_read_topo {2414	SLI4_READ_TOPO_UNKNOWN		= 0x0,2415	SLI4_READ_TOPO_NON_FC_AL,2416	SLI4_READ_TOPO_FC_AL,2417};2418 2419enum sli4_read_topo_speed {2420	SLI4_READ_TOPOLOGY_SPEED_NONE	= 0x00,2421	SLI4_READ_TOPOLOGY_SPEED_1G	= 0x04,2422	SLI4_READ_TOPOLOGY_SPEED_2G	= 0x08,2423	SLI4_READ_TOPOLOGY_SPEED_4G	= 0x10,2424	SLI4_READ_TOPOLOGY_SPEED_8G	= 0x20,2425	SLI4_READ_TOPOLOGY_SPEED_10G	= 0x40,2426	SLI4_READ_TOPOLOGY_SPEED_16G	= 0x80,2427	SLI4_READ_TOPOLOGY_SPEED_32G	= 0x90,2428	SLI4_READ_TOPOLOGY_SPEED_64G	= 0xa0,2429	SLI4_READ_TOPOLOGY_SPEED_128G	= 0xb0,2430};2431 2432/* REG_FCFI - activate a FC Forwarder */2433struct sli4_cmd_reg_fcfi_rq_cfg {2434	u8	r_ctl_mask;2435	u8	r_ctl_match;2436	u8	type_mask;2437	u8	type_match;2438};2439 2440enum sli4_regfcfi_tag {2441	SLI4_REGFCFI_VLAN_TAG		= 0xfff,2442	SLI4_REGFCFI_VLANTAG_VALID	= 0x1000,2443};2444 2445#define SLI4_CMD_REG_FCFI_NUM_RQ_CFG	42446struct sli4_cmd_reg_fcfi {2447	struct sli4_mbox_command_header	hdr;2448	__le16		fcf_index;2449	__le16		fcfi;2450	__le16		rqid1;2451	__le16		rqid0;2452	__le16		rqid3;2453	__le16		rqid2;2454	struct sli4_cmd_reg_fcfi_rq_cfg2455			rq_cfg[SLI4_CMD_REG_FCFI_NUM_RQ_CFG];2456	__le32		dw8_vlan;2457};2458 2459#define SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG	42460#define SLI4_CMD_REG_FCFI_MRQ_MAX_NUM_RQ	322461#define SLI4_CMD_REG_FCFI_SET_FCFI_MODE		02462#define SLI4_CMD_REG_FCFI_SET_MRQ_MODE		12463 2464enum sli4_reg_fcfi_mrq {2465	SLI4_REGFCFI_MRQ_VLAN_TAG	= 0xfff,2466	SLI4_REGFCFI_MRQ_VLANTAG_VALID	= 0x1000,2467	SLI4_REGFCFI_MRQ_MODE		= 0x2000,2468 2469	SLI4_REGFCFI_MRQ_MASK_NUM_PAIRS	= 0xff,2470	SLI4_REGFCFI_MRQ_FILTER_BITMASK = 0xf00,2471	SLI4_REGFCFI_MRQ_RQ_SEL_POLICY	= 0xf000,2472};2473 2474struct sli4_cmd_reg_fcfi_mrq {2475	struct sli4_mbox_command_header	hdr;2476	__le16		fcf_index;2477	__le16		fcfi;2478	__le16		rqid1;2479	__le16		rqid0;2480	__le16		rqid3;2481	__le16		rqid2;2482	struct sli4_cmd_reg_fcfi_rq_cfg2483			rq_cfg[SLI4_CMD_REG_FCFI_MRQ_NUM_RQ_CFG];2484	__le32		dw8_vlan;2485	__le32		dw9_mrqflags;2486};2487 2488struct sli4_cmd_rq_cfg {2489	__le16	rq_id;2490	u8	r_ctl_mask;2491	u8	r_ctl_match;2492	u8	type_mask;2493	u8	type_match;2494};2495 2496/* REG_RPI - register a Remote Port Indicator */2497enum sli4_reg_rpi {2498	SLI4_REGRPI_REMOTE_N_PORTID	= 0xffffff,	/* DW2 */2499	SLI4_REGRPI_UPD			= 0x1000000,2500	SLI4_REGRPI_ETOW		= 0x8000000,2501	SLI4_REGRPI_TERP		= 0x20000000,2502	SLI4_REGRPI_CI			= 0x80000000,2503};2504 2505struct sli4_cmd_reg_rpi {2506	struct sli4_mbox_command_header	hdr;2507	__le16			rpi;2508	__le16			rsvd2;2509	__le32			dw2_rportid_flags;2510	struct sli4_bde		bde_64;2511	__le16			vpi;2512	__le16			rsvd26;2513};2514 2515#define SLI4_REG_RPI_BUF_LEN		0x702516 2517/* REG_VFI - register a Virtual Fabric Indicator */2518enum sli_reg_vfi {2519	SLI4_REGVFI_VP			= 0x1000,	/* DW1 */2520	SLI4_REGVFI_UPD			= 0x2000,2521 2522	SLI4_REGVFI_LOCAL_N_PORTID	= 0xffffff,	/* DW10 */2523};2524 2525struct sli4_cmd_reg_vfi {2526	struct sli4_mbox_command_header	hdr;2527	__le16			vfi;2528	__le16			dw0w1_flags;2529	__le16			fcfi;2530	__le16			vpi;2531	u8			wwpn[8];2532	struct sli4_bde		sparm;2533	__le32			e_d_tov;2534	__le32			r_a_tov;2535	__le32			dw10_lportid_flags;2536};2537 2538/* REG_VPI - register a Virtual Port Indicator */2539enum sli4_reg_vpi {2540	SLI4_REGVPI_LOCAL_N_PORTID	= 0xffffff,2541	SLI4_REGVPI_UPD			= 0x1000000,2542};2543 2544struct sli4_cmd_reg_vpi {2545	struct sli4_mbox_command_header	hdr;2546	__le32		rsvd0;2547	__le32		dw2_lportid_flags;2548	u8		wwpn[8];2549	__le32		rsvd12;2550	__le16		vpi;2551	__le16		vfi;2552};2553 2554/* REQUEST_FEATURES - request / query SLI features */2555enum sli4_req_features_flags {2556	SLI4_REQFEAT_QRY	= 0x1,		/* Dw1 */2557 2558	SLI4_REQFEAT_IAAB	= 1 << 0,	/* DW2 & DW3 */2559	SLI4_REQFEAT_NPIV	= 1 << 1,2560	SLI4_REQFEAT_DIF	= 1 << 2,2561	SLI4_REQFEAT_VF		= 1 << 3,2562	SLI4_REQFEAT_FCPI	= 1 << 4,2563	SLI4_REQFEAT_FCPT	= 1 << 5,2564	SLI4_REQFEAT_FCPC	= 1 << 6,2565	SLI4_REQFEAT_RSVD	= 1 << 7,2566	SLI4_REQFEAT_RQD	= 1 << 8,2567	SLI4_REQFEAT_IAAR	= 1 << 9,2568	SLI4_REQFEAT_HLM	= 1 << 10,2569	SLI4_REQFEAT_PERFH	= 1 << 11,2570	SLI4_REQFEAT_RXSEQ	= 1 << 12,2571	SLI4_REQFEAT_RXRI	= 1 << 13,2572	SLI4_REQFEAT_DCL2	= 1 << 14,2573	SLI4_REQFEAT_RSCO	= 1 << 15,2574	SLI4_REQFEAT_MRQP	= 1 << 16,2575};2576 2577struct sli4_cmd_request_features {2578	struct sli4_mbox_command_header	hdr;2579	__le32		dw1_qry;2580	__le32		cmd;2581	__le32		resp;2582};2583 2584/*2585 * SLI_CONFIG - submit a configuration command to Port2586 *2587 * Command is either embedded as part of the payload (embed) or located2588 * in a separate memory buffer (mem)2589 */2590enum sli4_sli_config {2591	SLI4_SLICONF_EMB		= 0x1,		/* DW1 */2592	SLI4_SLICONF_PMDCMD_SHIFT	= 3,2593	SLI4_SLICONF_PMDCMD_MASK	= 0xf8,2594	SLI4_SLICONF_PMDCMD_VAL_1	= 8,2595	SLI4_SLICONF_PMDCNT		= 0xf8,2596 2597	SLI4_SLICONF_PMD_LEN		= 0x00ffffff,2598};2599 2600struct sli4_cmd_sli_config {2601	struct sli4_mbox_command_header	hdr;2602	__le32		dw1_flags;2603	__le32		payload_len;2604	__le32		rsvd12[3];2605	union {2606		u8 embed[58 * sizeof(u32)];2607		struct sli4_bufptr mem;2608	} payload;2609};2610 2611/* READ_STATUS - read tx/rx status of a particular port */2612#define SLI4_READSTATUS_CLEAR_COUNTERS	0x12613 2614struct sli4_cmd_read_status {2615	struct sli4_mbox_command_header	hdr;2616	__le32		dw1_flags;2617	__le32		rsvd4;2618	__le32		trans_kbyte_cnt;2619	__le32		recv_kbyte_cnt;2620	__le32		trans_frame_cnt;2621	__le32		recv_frame_cnt;2622	__le32		trans_seq_cnt;2623	__le32		recv_seq_cnt;2624	__le32		tot_exchanges_orig;2625	__le32		tot_exchanges_resp;2626	__le32		recv_p_bsy_cnt;2627	__le32		recv_f_bsy_cnt;2628	__le32		no_rq_buf_dropped_frames_cnt;2629	__le32		empty_rq_timeout_cnt;2630	__le32		no_xri_dropped_frames_cnt;2631	__le32		empty_xri_pool_cnt;2632};2633 2634/* READ_LNK_STAT - read link status of a particular port */2635enum sli4_read_link_stats_flags {2636	SLI4_READ_LNKSTAT_REC	= 1u << 0,2637	SLI4_READ_LNKSTAT_GEC	= 1u << 1,2638	SLI4_READ_LNKSTAT_W02OF	= 1u << 2,2639	SLI4_READ_LNKSTAT_W03OF	= 1u << 3,2640	SLI4_READ_LNKSTAT_W04OF	= 1u << 4,2641	SLI4_READ_LNKSTAT_W05OF	= 1u << 5,2642	SLI4_READ_LNKSTAT_W06OF	= 1u << 6,2643	SLI4_READ_LNKSTAT_W07OF	= 1u << 7,2644	SLI4_READ_LNKSTAT_W08OF	= 1u << 8,2645	SLI4_READ_LNKSTAT_W09OF	= 1u << 9,2646	SLI4_READ_LNKSTAT_W10OF = 1u << 10,2647	SLI4_READ_LNKSTAT_W11OF = 1u << 11,2648	SLI4_READ_LNKSTAT_W12OF	= 1u << 12,2649	SLI4_READ_LNKSTAT_W13OF	= 1u << 13,2650	SLI4_READ_LNKSTAT_W14OF	= 1u << 14,2651	SLI4_READ_LNKSTAT_W15OF	= 1u << 15,2652	SLI4_READ_LNKSTAT_W16OF	= 1u << 16,2653	SLI4_READ_LNKSTAT_W17OF	= 1u << 17,2654	SLI4_READ_LNKSTAT_W18OF	= 1u << 18,2655	SLI4_READ_LNKSTAT_W19OF	= 1u << 19,2656	SLI4_READ_LNKSTAT_W20OF	= 1u << 20,2657	SLI4_READ_LNKSTAT_W21OF	= 1u << 21,2658	SLI4_READ_LNKSTAT_CLRC	= 1u << 30,2659	SLI4_READ_LNKSTAT_CLOF	= 1u << 31,2660};2661 2662struct sli4_cmd_read_link_stats {2663	struct sli4_mbox_command_header	hdr;2664	__le32	dw1_flags;2665	__le32	linkfail_errcnt;2666	__le32	losssync_errcnt;2667	__le32	losssignal_errcnt;2668	__le32	primseq_errcnt;2669	__le32	inval_txword_errcnt;2670	__le32	crc_errcnt;2671	__le32	primseq_eventtimeout_cnt;2672	__le32	elastic_bufoverrun_errcnt;2673	__le32	arbit_fc_al_timeout_cnt;2674	__le32	adv_rx_buftor_to_buf_credit;2675	__le32	curr_rx_buf_to_buf_credit;2676	__le32	adv_tx_buf_to_buf_credit;2677	__le32	curr_tx_buf_to_buf_credit;2678	__le32	rx_eofa_cnt;2679	__le32	rx_eofdti_cnt;2680	__le32	rx_eofni_cnt;2681	__le32	rx_soff_cnt;2682	__le32	rx_dropped_no_aer_cnt;2683	__le32	rx_dropped_no_avail_rpi_rescnt;2684	__le32	rx_dropped_no_avail_xri_rescnt;2685};2686 2687/* Format a WQE with WQ_ID Association performance hint */2688static inline void2689sli_set_wq_id_association(void *entry, u16 q_id)2690{2691	u32 *wqe = entry;2692 2693	/*2694	 * Set Word 10, bit 0 to zero2695	 * Set Word 10, bits 15:1 to the WQ ID2696	 */2697	wqe[10] &= ~0xffff;2698	wqe[10] |= q_id << 1;2699}2700 2701/* UNREG_FCFI - unregister a FCFI */2702struct sli4_cmd_unreg_fcfi {2703	struct sli4_mbox_command_header	hdr;2704	__le32		rsvd0;2705	__le16		fcfi;2706	__le16		rsvd6;2707};2708 2709/* UNREG_RPI - unregister one or more RPI */2710enum sli4_unreg_rpi {2711	SLI4_UNREG_RPI_DP	= 0x2000,2712	SLI4_UNREG_RPI_II_SHIFT	= 14,2713	SLI4_UNREG_RPI_II_MASK	= 0xc000,2714	SLI4_UNREG_RPI_II_RPI	= 0x0000,2715	SLI4_UNREG_RPI_II_VPI	= 0x4000,2716	SLI4_UNREG_RPI_II_VFI	= 0x8000,2717	SLI4_UNREG_RPI_II_FCFI	= 0xc000,2718 2719	SLI4_UNREG_RPI_DEST_N_PORTID_MASK = 0x00ffffff,2720};2721 2722struct sli4_cmd_unreg_rpi {2723	struct sli4_mbox_command_header	hdr;2724	__le16		index;2725	__le16		dw1w1_flags;2726	__le32		dw2_dest_n_portid;2727};2728 2729/* UNREG_VFI - unregister one or more VFI */2730enum sli4_unreg_vfi {2731	SLI4_UNREG_VFI_II_SHIFT	= 14,2732	SLI4_UNREG_VFI_II_MASK	= 0xc000,2733	SLI4_UNREG_VFI_II_VFI	= 0x0000,2734	SLI4_UNREG_VFI_II_FCFI	= 0xc000,2735};2736 2737struct sli4_cmd_unreg_vfi {2738	struct sli4_mbox_command_header	hdr;2739	__le32		rsvd0;2740	__le16		index;2741	__le16		dw2_flags;2742};2743 2744enum sli4_unreg_type {2745	SLI4_UNREG_TYPE_PORT,2746	SLI4_UNREG_TYPE_DOMAIN,2747	SLI4_UNREG_TYPE_FCF,2748	SLI4_UNREG_TYPE_ALL2749};2750 2751/* UNREG_VPI - unregister one or more VPI */2752enum sli4_unreg_vpi {2753	SLI4_UNREG_VPI_II_SHIFT	= 14,2754	SLI4_UNREG_VPI_II_MASK	= 0xc000,2755	SLI4_UNREG_VPI_II_VPI	= 0x0000,2756	SLI4_UNREG_VPI_II_VFI	= 0x8000,2757	SLI4_UNREG_VPI_II_FCFI	= 0xc000,2758};2759 2760struct sli4_cmd_unreg_vpi {2761	struct sli4_mbox_command_header	hdr;2762	__le32		rsvd0;2763	__le16		index;2764	__le16		dw2w0_flags;2765};2766 2767/* AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature */2768struct sli4_cmd_config_auto_xfer_rdy {2769	struct sli4_mbox_command_header	hdr;2770	__le32		rsvd0;2771	__le32		max_burst_len;2772};2773 2774#define SLI4_CONFIG_AUTO_XFERRDY_BLKSIZE	0xffff2775 2776struct sli4_cmd_config_auto_xfer_rdy_hp {2777	struct sli4_mbox_command_header	hdr;2778	__le32		rsvd0;2779	__le32		max_burst_len;2780	__le32		dw3_esoc_flags;2781	__le16		block_size;2782	__le16		rsvd14;2783};2784 2785/*************************************************************************2786 * SLI-4 common configuration command formats and definitions2787 */2788 2789/*2790 * Subsystem values.2791 */2792enum sli4_subsystem {2793	SLI4_SUBSYSTEM_COMMON	= 0x01,2794	SLI4_SUBSYSTEM_LOWLEVEL	= 0x0b,2795	SLI4_SUBSYSTEM_FC	= 0x0c,2796	SLI4_SUBSYSTEM_DMTF	= 0x11,2797};2798 2799#define	SLI4_OPC_LOWLEVEL_SET_WATCHDOG		0X362800 2801/*2802 * Common opcode (OPC) values.2803 */2804enum sli4_cmn_opcode {2805	SLI4_CMN_FUNCTION_RESET		= 0x3d,2806	SLI4_CMN_CREATE_CQ		= 0x0c,2807	SLI4_CMN_CREATE_CQ_SET		= 0x1d,2808	SLI4_CMN_DESTROY_CQ		= 0x36,2809	SLI4_CMN_MODIFY_EQ_DELAY	= 0x29,2810	SLI4_CMN_CREATE_EQ		= 0x0d,2811	SLI4_CMN_DESTROY_EQ		= 0x37,2812	SLI4_CMN_CREATE_MQ_EXT		= 0x5a,2813	SLI4_CMN_DESTROY_MQ		= 0x35,2814	SLI4_CMN_GET_CNTL_ATTRIBUTES	= 0x20,2815	SLI4_CMN_NOP			= 0x21,2816	SLI4_CMN_GET_RSC_EXTENT_INFO	= 0x9a,2817	SLI4_CMN_GET_SLI4_PARAMS	= 0xb5,2818	SLI4_CMN_QUERY_FW_CONFIG	= 0x3a,2819	SLI4_CMN_GET_PORT_NAME		= 0x4d,2820 2821	SLI4_CMN_WRITE_FLASHROM		= 0x07,2822	/* TRANSCEIVER Data */2823	SLI4_CMN_READ_TRANS_DATA	= 0x49,2824	SLI4_CMN_GET_CNTL_ADDL_ATTRS	= 0x79,2825	SLI4_CMN_GET_FUNCTION_CFG	= 0xa0,2826	SLI4_CMN_GET_PROFILE_CFG	= 0xa4,2827	SLI4_CMN_SET_PROFILE_CFG	= 0xa5,2828	SLI4_CMN_GET_PROFILE_LIST	= 0xa6,2829	SLI4_CMN_GET_ACTIVE_PROFILE	= 0xa7,2830	SLI4_CMN_SET_ACTIVE_PROFILE	= 0xa8,2831	SLI4_CMN_READ_OBJECT		= 0xab,2832	SLI4_CMN_WRITE_OBJECT		= 0xac,2833	SLI4_CMN_DELETE_OBJECT		= 0xae,2834	SLI4_CMN_READ_OBJECT_LIST	= 0xad,2835	SLI4_CMN_SET_DUMP_LOCATION	= 0xb8,2836	SLI4_CMN_SET_FEATURES		= 0xbf,2837	SLI4_CMN_GET_RECFG_LINK_INFO	= 0xc9,2838	SLI4_CMN_SET_RECNG_LINK_ID	= 0xca,2839};2840 2841/* DMTF opcode (OPC) values */2842#define DMTF_EXEC_CLP_CMD 0x012843 2844/*2845 * COMMON_FUNCTION_RESET2846 *2847 * Resets the Port, returning it to a power-on state. This configuration2848 * command does not have a payload and should set/expect the lengths to2849 * be zero.2850 */2851struct sli4_rqst_cmn_function_reset {2852	struct sli4_rqst_hdr	hdr;2853};2854 2855struct sli4_rsp_cmn_function_reset {2856	struct sli4_rsp_hdr	hdr;2857};2858 2859/*2860 * COMMON_GET_CNTL_ATTRIBUTES2861 *2862 * Query for information about the SLI Port2863 */2864enum sli4_cntrl_attr_flags {2865	SLI4_CNTL_ATTR_PORTNUM	= 0x3f,2866	SLI4_CNTL_ATTR_PORTTYPE	= 0xc0,2867};2868 2869struct sli4_rsp_cmn_get_cntl_attributes {2870	struct sli4_rsp_hdr	hdr;2871	u8		version_str[32];2872	u8		manufacturer_name[32];2873	__le32		supported_modes;2874	u8		eprom_version_lo;2875	u8		eprom_version_hi;2876	__le16		rsvd17;2877	__le32		mbx_ds_version;2878	__le32		ep_fw_ds_version;2879	u8		ncsi_version_str[12];2880	__le32		def_extended_timeout;2881	u8		model_number[32];2882	u8		description[64];2883	u8		serial_number[32];2884	u8		ip_version_str[32];2885	u8		fw_version_str[32];2886	u8		bios_version_str[32];2887	u8		redboot_version_str[32];2888	u8		driver_version_str[32];2889	u8		fw_on_flash_version_str[32];2890	__le32		functionalities_supported;2891	__le16		max_cdb_length;2892	u8		asic_revision;2893	u8		generational_guid0;2894	__le32		generational_guid1_12[3];2895	__le16		generational_guid13_14;2896	u8		generational_guid15;2897	u8		hba_port_count;2898	__le16		default_link_down_timeout;2899	u8		iscsi_version_min_max;2900	u8		multifunctional_device;2901	u8		cache_valid;2902	u8		hba_status;2903	u8		max_domains_supported;2904	u8		port_num_type_flags;2905	__le32		firmware_post_status;2906	__le32		hba_mtu;2907	u8		iscsi_features;2908	u8		rsvd121[3];2909	__le16		pci_vendor_id;2910	__le16		pci_device_id;2911	__le16		pci_sub_vendor_id;2912	__le16		pci_sub_system_id;2913	u8		pci_bus_number;2914	u8		pci_device_number;2915	u8		pci_function_number;2916	u8		interface_type;2917	__le64		unique_identifier;2918	u8		number_of_netfilters;2919	u8		rsvd122[3];2920};2921 2922/*2923 * COMMON_GET_CNTL_ATTRIBUTES2924 *2925 * This command queries the controller information from the Flash ROM.2926 */2927struct sli4_rqst_cmn_get_cntl_addl_attributes {2928	struct sli4_rqst_hdr	hdr;2929};2930 2931struct sli4_rsp_cmn_get_cntl_addl_attributes {2932	struct sli4_rsp_hdr	hdr;2933	__le16		ipl_file_number;2934	u8		ipl_file_version;2935	u8		rsvd4;2936	u8		on_die_temperature;2937	u8		rsvd5[3];2938	__le32		driver_advanced_features_supported;2939	__le32		rsvd7[4];2940	char		universal_bios_version[32];2941	char		x86_bios_version[32];2942	char		efi_bios_version[32];2943	char		fcode_version[32];2944	char		uefi_bios_version[32];2945	char		uefi_nic_version[32];2946	char		uefi_fcode_version[32];2947	char		uefi_iscsi_version[32];2948	char		iscsi_x86_bios_version[32];2949	char		pxe_x86_bios_version[32];2950	u8		default_wwpn[8];2951	u8		ext_phy_version[32];2952	u8		fc_universal_bios_version[32];2953	u8		fc_x86_bios_version[32];2954	u8		fc_efi_bios_version[32];2955	u8		fc_fcode_version[32];2956	u8		ext_phy_crc_label[8];2957	u8		ipl_file_name[16];2958	u8		rsvd139[72];2959};2960 2961/*2962 * COMMON_NOP2963 *2964 * This command does not do anything; it only returns2965 * the payload in the completion.2966 */2967struct sli4_rqst_cmn_nop {2968	struct sli4_rqst_hdr	hdr;2969	__le32			context[2];2970};2971 2972struct sli4_rsp_cmn_nop {2973	struct sli4_rsp_hdr	hdr;2974	__le32			context[2];2975};2976 2977struct sli4_rqst_cmn_get_resource_extent_info {2978	struct sli4_rqst_hdr	hdr;2979	__le16	resource_type;2980	__le16	rsvd16;2981};2982 2983enum sli4_rsc_type {2984	SLI4_RSC_TYPE_VFI	= 0x20,2985	SLI4_RSC_TYPE_VPI	= 0x21,2986	SLI4_RSC_TYPE_RPI	= 0x22,2987	SLI4_RSC_TYPE_XRI	= 0x23,2988};2989 2990struct sli4_rsp_cmn_get_resource_extent_info {2991	struct sli4_rsp_hdr	hdr;2992	__le16		resource_extent_count;2993	__le16		resource_extent_size;2994};2995 2996#define SLI4_128BYTE_WQE_SUPPORT	0x022997 2998#define GET_Q_CNT_METHOD(m) \2999	(((m) & SLI4_PARAM_Q_CNT_MTHD_MASK) >> SLI4_PARAM_Q_CNT_MTHD_SHFT)3000#define GET_Q_CREATE_VERSION(v) \3001	(((v) & SLI4_PARAM_QV_MASK) >> SLI4_PARAM_QV_SHIFT)3002 3003enum sli4_rsp_get_params_e {3004	/*GENERIC*/3005	SLI4_PARAM_Q_CNT_MTHD_SHFT	= 24,3006	SLI4_PARAM_Q_CNT_MTHD_MASK	= 0xf << 24,3007	SLI4_PARAM_QV_SHIFT		= 14,3008	SLI4_PARAM_QV_MASK		= 3 << 14,3009 3010	/* DW4 */3011	SLI4_PARAM_PROTO_TYPE_MASK	= 0xff,3012	/* DW5 */3013	SLI4_PARAM_FT			= 1 << 0,3014	SLI4_PARAM_SLI_REV_MASK		= 0xf << 4,3015	SLI4_PARAM_SLI_FAM_MASK		= 0xf << 8,3016	SLI4_PARAM_IF_TYPE_MASK		= 0xf << 12,3017	SLI4_PARAM_SLI_HINT1_MASK	= 0xff << 16,3018	SLI4_PARAM_SLI_HINT2_MASK	= 0x1f << 24,3019	/* DW6 */3020	SLI4_PARAM_EQ_PAGE_CNT_MASK	= 0xf << 0,3021	SLI4_PARAM_EQE_SZS_MASK		= 0xf << 8,3022	SLI4_PARAM_EQ_PAGE_SZS_MASK	= 0xff << 16,3023	/* DW8 */3024	SLI4_PARAM_CQ_PAGE_CNT_MASK	= 0xf << 0,3025	SLI4_PARAM_CQE_SZS_MASK		= 0xf << 8,3026	SLI4_PARAM_CQ_PAGE_SZS_MASK	= 0xff << 16,3027	/* DW10 */3028	SLI4_PARAM_MQ_PAGE_CNT_MASK	= 0xf << 0,3029	SLI4_PARAM_MQ_PAGE_SZS_MASK	= 0xff << 16,3030	/* DW12 */3031	SLI4_PARAM_WQ_PAGE_CNT_MASK	= 0xf << 0,3032	SLI4_PARAM_WQE_SZS_MASK		= 0xf << 8,3033	SLI4_PARAM_WQ_PAGE_SZS_MASK	= 0xff << 16,3034	/* DW14 */3035	SLI4_PARAM_RQ_PAGE_CNT_MASK	= 0xf << 0,3036	SLI4_PARAM_RQE_SZS_MASK		= 0xf << 8,3037	SLI4_PARAM_RQ_PAGE_SZS_MASK	= 0xff << 16,3038	/* DW15W1*/3039	SLI4_PARAM_RQ_DB_WINDOW_MASK	= 0xf000,3040	/* DW16 */3041	SLI4_PARAM_FC			= 1 << 0,3042	SLI4_PARAM_EXT			= 1 << 1,3043	SLI4_PARAM_HDRR			= 1 << 2,3044	SLI4_PARAM_SGLR			= 1 << 3,3045	SLI4_PARAM_FBRR			= 1 << 4,3046	SLI4_PARAM_AREG			= 1 << 5,3047	SLI4_PARAM_TGT			= 1 << 6,3048	SLI4_PARAM_TERP			= 1 << 7,3049	SLI4_PARAM_ASSI			= 1 << 8,3050	SLI4_PARAM_WCHN			= 1 << 9,3051	SLI4_PARAM_TCCA			= 1 << 10,3052	SLI4_PARAM_TRTY			= 1 << 11,3053	SLI4_PARAM_TRIR			= 1 << 12,3054	SLI4_PARAM_PHOFF		= 1 << 13,3055	SLI4_PARAM_PHON			= 1 << 14,3056	SLI4_PARAM_PHWQ			= 1 << 15,3057	SLI4_PARAM_BOUND_4GA		= 1 << 16,3058	SLI4_PARAM_RXC			= 1 << 17,3059	SLI4_PARAM_HLM			= 1 << 18,3060	SLI4_PARAM_IPR			= 1 << 19,3061	SLI4_PARAM_RXRI			= 1 << 20,3062	SLI4_PARAM_SGLC			= 1 << 21,3063	SLI4_PARAM_TIMM			= 1 << 22,3064	SLI4_PARAM_TSMM			= 1 << 23,3065	SLI4_PARAM_OAS			= 1 << 25,3066	SLI4_PARAM_LC			= 1 << 26,3067	SLI4_PARAM_AGXF			= 1 << 27,3068	SLI4_PARAM_LOOPBACK_MASK	= 0xf << 28,3069	/* DW18 */3070	SLI4_PARAM_SGL_PAGE_CNT_MASK	= 0xf << 0,3071	SLI4_PARAM_SGL_PAGE_SZS_MASK	= 0xff << 8,3072	SLI4_PARAM_SGL_PP_ALIGN_MASK	= 0xff << 16,3073};3074 3075struct sli4_rqst_cmn_get_sli4_params {3076	struct sli4_rqst_hdr	hdr;3077};3078 3079struct sli4_rsp_cmn_get_sli4_params {3080	struct sli4_rsp_hdr	hdr;3081	__le32		dw4_protocol_type;3082	__le32		dw5_sli;3083	__le32		dw6_eq_page_cnt;3084	__le16		eqe_count_mask;3085	__le16		rsvd26;3086	__le32		dw8_cq_page_cnt;3087	__le16		cqe_count_mask;3088	__le16		rsvd34;3089	__le32		dw10_mq_page_cnt;3090	__le16		mqe_count_mask;3091	__le16		rsvd42;3092	__le32		dw12_wq_page_cnt;3093	__le16		wqe_count_mask;3094	__le16		rsvd50;3095	__le32		dw14_rq_page_cnt;3096	__le16		rqe_count_mask;3097	__le16		dw15w1_rq_db_window;3098	__le32		dw16_loopback_scope;3099	__le32		sge_supported_length;3100	__le32		dw18_sgl_page_cnt;3101	__le16		min_rq_buffer_size;3102	__le16		rsvd75;3103	__le32		max_rq_buffer_size;3104	__le16		physical_xri_max;3105	__le16		physical_rpi_max;3106	__le16		physical_vpi_max;3107	__le16		physical_vfi_max;3108	__le32		rsvd88;3109	__le16		frag_num_field_offset;3110	__le16		frag_num_field_size;3111	__le16		sgl_index_field_offset;3112	__le16		sgl_index_field_size;3113	__le32		chain_sge_initial_value_lo;3114	__le32		chain_sge_initial_value_hi;3115};3116 3117/*Port Types*/3118enum sli4_port_types {3119	SLI4_PORT_TYPE_ETH	= 0,3120	SLI4_PORT_TYPE_FC	= 1,3121};3122 3123struct sli4_rqst_cmn_get_port_name {3124	struct sli4_rqst_hdr	hdr;3125	u8	port_type;3126	u8	rsvd4[3];3127};3128 3129struct sli4_rsp_cmn_get_port_name {3130	struct sli4_rsp_hdr	hdr;3131	char	port_name[4];3132};3133 3134struct sli4_rqst_cmn_write_flashrom {3135	struct sli4_rqst_hdr	hdr;3136	__le32		flash_rom_access_opcode;3137	__le32		flash_rom_access_operation_type;3138	__le32		data_buffer_size;3139	__le32		offset;3140	u8		data_buffer[4];3141};3142 3143/*3144 * COMMON_READ_TRANSCEIVER_DATA3145 *3146 * This command reads SFF transceiver data(Format is defined3147 * by the SFF-8472 specification).3148 */3149struct sli4_rqst_cmn_read_transceiver_data {3150	struct sli4_rqst_hdr	hdr;3151	__le32			page_number;3152	__le32			port;3153};3154 3155struct sli4_rsp_cmn_read_transceiver_data {3156	struct sli4_rsp_hdr	hdr;3157	__le32			page_number;3158	__le32			port;3159	u8			page_data[128];3160	u8			page_data_2[128];3161};3162 3163#define SLI4_REQ_DESIRE_READLEN		0xffffff3164 3165struct sli4_rqst_cmn_read_object {3166	struct sli4_rqst_hdr	hdr;3167	__le32			desired_read_length_dword;3168	__le32			read_offset;3169	u8			object_name[104];3170	__le32			host_buffer_descriptor_count;3171	struct sli4_bde		host_buffer_descriptor[];3172};3173 3174#define RSP_COM_READ_OBJ_EOF		0x800000003175 3176struct sli4_rsp_cmn_read_object {3177	struct sli4_rsp_hdr	hdr;3178	__le32			actual_read_length;3179	__le32			eof_dword;3180};3181 3182enum sli4_rqst_write_object_flags {3183	SLI4_RQ_DES_WRITE_LEN		= 0xffffff,3184	SLI4_RQ_DES_WRITE_LEN_NOC	= 0x40000000,3185	SLI4_RQ_DES_WRITE_LEN_EOF	= 0x80000000,3186};3187 3188struct sli4_rqst_cmn_write_object {3189	struct sli4_rqst_hdr	hdr;3190	__le32			desired_write_len_dword;3191	__le32			write_offset;3192	u8			object_name[104];3193	__le32			host_buffer_descriptor_count;3194	struct sli4_bde		host_buffer_descriptor[];3195};3196 3197#define	RSP_CHANGE_STATUS		0xff3198 3199struct sli4_rsp_cmn_write_object {3200	struct sli4_rsp_hdr	hdr;3201	__le32			actual_write_length;3202	__le32			change_status_dword;3203};3204 3205struct sli4_rqst_cmn_delete_object {3206	struct sli4_rqst_hdr	hdr;3207	__le32			rsvd4;3208	__le32			rsvd5;3209	u8			object_name[104];3210};3211 3212#define SLI4_RQ_OBJ_LIST_READ_LEN	0xffffff3213 3214struct sli4_rqst_cmn_read_object_list {3215	struct sli4_rqst_hdr	hdr;3216	__le32			desired_read_length_dword;3217	__le32			read_offset;3218	u8			object_name[104];3219	__le32			host_buffer_descriptor_count;3220	struct sli4_bde		host_buffer_descriptor[];3221};3222 3223enum sli4_rqst_set_dump_flags {3224	SLI4_CMN_SET_DUMP_BUFFER_LEN	= 0xffffff,3225	SLI4_CMN_SET_DUMP_FDB		= 0x20000000,3226	SLI4_CMN_SET_DUMP_BLP		= 0x40000000,3227	SLI4_CMN_SET_DUMP_QRY		= 0x80000000,3228};3229 3230struct sli4_rqst_cmn_set_dump_location {3231	struct sli4_rqst_hdr	hdr;3232	__le32			buffer_length_dword;3233	__le32			buf_addr_low;3234	__le32			buf_addr_high;3235};3236 3237struct sli4_rsp_cmn_set_dump_location {3238	struct sli4_rsp_hdr	hdr;3239	__le32			buffer_length_dword;3240};3241 3242enum sli4_dump_level {3243	SLI4_DUMP_LEVEL_NONE,3244	SLI4_CHIP_LEVEL_DUMP,3245	SLI4_FUNC_DESC_DUMP,3246};3247 3248enum sli4_dump_state {3249	SLI4_DUMP_STATE_NONE,3250	SLI4_CHIP_DUMP_STATE_VALID,3251	SLI4_FUNC_DUMP_STATE_VALID,3252};3253 3254enum sli4_dump_status {3255	SLI4_DUMP_READY_STATUS_NOT_READY,3256	SLI4_DUMP_READY_STATUS_DD_PRESENT,3257	SLI4_DUMP_READY_STATUS_FDB_PRESENT,3258	SLI4_DUMP_READY_STATUS_SKIP_DUMP,3259	SLI4_DUMP_READY_STATUS_FAILED = -1,3260};3261 3262enum sli4_set_features {3263	SLI4_SET_FEATURES_DIF_SEED			= 0x01,3264	SLI4_SET_FEATURES_XRI_TIMER			= 0x03,3265	SLI4_SET_FEATURES_MAX_PCIE_SPEED		= 0x04,3266	SLI4_SET_FEATURES_FCTL_CHECK			= 0x05,3267	SLI4_SET_FEATURES_FEC				= 0x06,3268	SLI4_SET_FEATURES_PCIE_RECV_DETECT		= 0x07,3269	SLI4_SET_FEATURES_DIF_MEMORY_MODE		= 0x08,3270	SLI4_SET_FEATURES_DISABLE_SLI_PORT_PAUSE_STATE	= 0x09,3271	SLI4_SET_FEATURES_ENABLE_PCIE_OPTIONS		= 0x0a,3272	SLI4_SET_FEAT_CFG_AUTO_XFER_RDY_T10PI		= 0x0c,3273	SLI4_SET_FEATURES_ENABLE_MULTI_RECEIVE_QUEUE	= 0x0d,3274	SLI4_SET_FEATURES_SET_FTD_XFER_HINT		= 0x0f,3275	SLI4_SET_FEATURES_SLI_PORT_HEALTH_CHECK		= 0x11,3276};3277 3278struct sli4_rqst_cmn_set_features {3279	struct sli4_rqst_hdr	hdr;3280	__le32			feature;3281	__le32			param_len;3282	__le32			params[8];3283};3284 3285struct sli4_rqst_cmn_set_features_dif_seed {3286	__le16		seed;3287	__le16		rsvd16;3288};3289 3290enum sli4_rqst_set_mrq_features {3291	SLI4_RQ_MULTIRQ_ISR		 = 0x1,3292	SLI4_RQ_MULTIRQ_AUTOGEN_XFER_RDY = 0x2,3293 3294	SLI4_RQ_MULTIRQ_NUM_RQS		 = 0xff,3295	SLI4_RQ_MULTIRQ_RQ_SELECT	 = 0xf00,3296};3297 3298struct sli4_rqst_cmn_set_features_multirq {3299	__le32		auto_gen_xfer_dword;3300	__le32		num_rqs_dword;3301};3302 3303enum sli4_rqst_health_check_flags {3304	SLI4_RQ_HEALTH_CHECK_ENABLE	= 0x1,3305	SLI4_RQ_HEALTH_CHECK_QUERY	= 0x2,3306};3307 3308struct sli4_rqst_cmn_set_features_health_check {3309	__le32		health_check_dword;3310};3311 3312struct sli4_rqst_cmn_set_features_set_fdt_xfer_hint {3313	__le32		fdt_xfer_hint;3314};3315 3316struct sli4_rqst_dmtf_exec_clp_cmd {3317	struct sli4_rqst_hdr	hdr;3318	__le32			cmd_buf_length;3319	__le32			resp_buf_length;3320	__le32			cmd_buf_addr_low;3321	__le32			cmd_buf_addr_high;3322	__le32			resp_buf_addr_low;3323	__le32			resp_buf_addr_high;3324};3325 3326struct sli4_rsp_dmtf_exec_clp_cmd {3327	struct sli4_rsp_hdr	hdr;3328	__le32			rsvd4;3329	__le32			resp_length;3330	__le32			rsvd6;3331	__le32			rsvd7;3332	__le32			rsvd8;3333	__le32			rsvd9;3334	__le32			clp_status;3335	__le32			clp_detailed_status;3336};3337 3338#define SLI4_PROTOCOL_FC		0x103339#define SLI4_PROTOCOL_DEFAULT		0xff3340 3341struct sli4_rspource_descriptor_v1 {3342	u8		descriptor_type;3343	u8		descriptor_length;3344	__le16		rsvd16;3345	__le32		type_specific[];3346};3347 3348enum sli4_pcie_desc_flags {3349	SLI4_PCIE_DESC_IMM		= 0x4000,3350	SLI4_PCIE_DESC_NOSV		= 0x8000,3351 3352	SLI4_PCIE_DESC_PF_NO		= 0x3ff0000,3353 3354	SLI4_PCIE_DESC_MISSN_ROLE	= 0xff,3355	SLI4_PCIE_DESC_PCHG		= 0x8000000,3356	SLI4_PCIE_DESC_SCHG		= 0x10000000,3357	SLI4_PCIE_DESC_XCHG		= 0x20000000,3358	SLI4_PCIE_DESC_XROM		= 0xc00000003359};3360 3361struct sli4_pcie_resource_descriptor_v1 {3362	u8		descriptor_type;3363	u8		descriptor_length;3364	__le16		imm_nosv_dword;3365	__le32		pf_number_dword;3366	__le32		rsvd3;3367	u8		sriov_state;3368	u8		pf_state;3369	u8		pf_type;3370	u8		rsvd4;3371	__le16		number_of_vfs;3372	__le16		rsvd5;3373	__le32		mission_roles_dword;3374	__le32		rsvd7[16];3375};3376 3377struct sli4_rqst_cmn_get_function_config {3378	struct sli4_rqst_hdr  hdr;3379};3380 3381struct sli4_rsp_cmn_get_function_config {3382	struct sli4_rsp_hdr	hdr;3383	__le32			desc_count;3384	__le32			desc[54];3385};3386 3387/* Link Config Descriptor for link config functions */3388struct sli4_link_config_descriptor {3389	u8		link_config_id;3390	u8		rsvd1[3];3391	__le32		config_description[8];3392};3393 3394#define MAX_LINK_DES	103395 3396struct sli4_rqst_cmn_get_reconfig_link_info {3397	struct sli4_rqst_hdr  hdr;3398};3399 3400struct sli4_rsp_cmn_get_reconfig_link_info {3401	struct sli4_rsp_hdr	hdr;3402	u8			active_link_config_id;3403	u8			rsvd17;3404	u8			next_link_config_id;3405	u8			rsvd19;3406	__le32			link_configuration_descriptor_count;3407	struct sli4_link_config_descriptor3408				desc[MAX_LINK_DES];3409};3410 3411enum sli4_set_reconfig_link_flags {3412	SLI4_SET_RECONFIG_LINKID_NEXT	= 0xff,3413	SLI4_SET_RECONFIG_LINKID_FD	= 1u << 31,3414};3415 3416struct sli4_rqst_cmn_set_reconfig_link_id {3417	struct sli4_rqst_hdr  hdr;3418	__le32			dw4_flags;3419};3420 3421struct sli4_rsp_cmn_set_reconfig_link_id {3422	struct sli4_rsp_hdr	hdr;3423};3424 3425struct sli4_rqst_lowlevel_set_watchdog {3426	struct sli4_rqst_hdr	hdr;3427	__le16			watchdog_timeout;3428	__le16			rsvd18;3429};3430 3431struct sli4_rsp_lowlevel_set_watchdog {3432	struct sli4_rsp_hdr	hdr;3433	__le32			rsvd;3434};3435 3436/* FC opcode (OPC) values */3437enum sli4_fc_opcodes {3438	SLI4_OPC_WQ_CREATE		= 0x1,3439	SLI4_OPC_WQ_DESTROY		= 0x2,3440	SLI4_OPC_POST_SGL_PAGES		= 0x3,3441	SLI4_OPC_RQ_CREATE		= 0x5,3442	SLI4_OPC_RQ_DESTROY		= 0x6,3443	SLI4_OPC_READ_FCF_TABLE		= 0x8,3444	SLI4_OPC_POST_HDR_TEMPLATES	= 0xb,3445	SLI4_OPC_REDISCOVER_FCF		= 0x10,3446};3447 3448/* Use the default CQ associated with the WQ */3449#define SLI4_CQ_DEFAULT 0xffff3450 3451/*3452 * POST_SGL_PAGES3453 *3454 * Register the scatter gather list (SGL) memory and3455 * associate it with an XRI.3456 */3457struct sli4_rqst_post_sgl_pages {3458	struct sli4_rqst_hdr	hdr;3459	__le16			xri_start;3460	__le16			xri_count;3461	struct {3462		__le32		page0_low;3463		__le32		page0_high;3464		__le32		page1_low;3465		__le32		page1_high;3466	} page_set[10];3467};3468 3469struct sli4_rsp_post_sgl_pages {3470	struct sli4_rsp_hdr	hdr;3471};3472 3473struct sli4_rqst_post_hdr_templates {3474	struct sli4_rqst_hdr	hdr;3475	__le16			rpi_offset;3476	__le16			page_count;3477	struct sli4_dmaaddr	page_descriptor[];3478};3479 3480#define SLI4_HDR_TEMPLATE_SIZE		643481 3482enum sli4_io_flags {3483/* The XRI associated with this IO is already active */3484	SLI4_IO_CONTINUATION		= 1 << 0,3485/* Automatically generate a good RSP frame */3486	SLI4_IO_AUTO_GOOD_RESPONSE	= 1 << 1,3487	SLI4_IO_NO_ABORT		= 1 << 2,3488/* Set the DNRX bit because no auto xref rdy buffer is posted */3489	SLI4_IO_DNRX			= 1 << 3,3490};3491 3492enum sli4_callback {3493	SLI4_CB_LINK,3494	SLI4_CB_MAX,3495};3496 3497enum sli4_link_status {3498	SLI4_LINK_STATUS_UP,3499	SLI4_LINK_STATUS_DOWN,3500	SLI4_LINK_STATUS_NO_ALPA,3501	SLI4_LINK_STATUS_MAX,3502};3503 3504enum sli4_link_topology {3505	SLI4_LINK_TOPO_NON_FC_AL = 1,3506	SLI4_LINK_TOPO_FC_AL,3507	SLI4_LINK_TOPO_LOOPBACK_INTERNAL,3508	SLI4_LINK_TOPO_LOOPBACK_EXTERNAL,3509	SLI4_LINK_TOPO_NONE,3510	SLI4_LINK_TOPO_MAX,3511};3512 3513enum sli4_link_medium {3514	SLI4_LINK_MEDIUM_ETHERNET,3515	SLI4_LINK_MEDIUM_FC,3516	SLI4_LINK_MEDIUM_MAX,3517};3518/******Driver specific structures******/3519 3520struct sli4_queue {3521	/* Common to all queue types */3522	struct efc_dma	dma;3523	spinlock_t	lock;		/* Lock to protect the doorbell register3524					 * writes and queue reads3525					 */3526	u32		index;		/* current host entry index */3527	u16		size;		/* entry size */3528	u16		length;		/* number of entries */3529	u16		n_posted;	/* number entries posted for CQ, EQ */3530	u16		id;		/* Port assigned xQ_ID */3531	u8		type;		/* queue type ie EQ, CQ, ... */3532	void __iomem    *db_regaddr;	/* register address for the doorbell */3533	u16		phase;		/* For if_type = 6, this value toggle3534					 * for each iteration of the queue,3535					 * a queue entry is valid when a cqe3536					 * valid bit matches this value3537					 */3538	u32		proc_limit;	/* limit CQE processed per iteration */3539	u32		posted_limit;	/* CQE/EQE process before ring db */3540	u32		max_num_processed;3541	u64		max_process_time;3542	union {3543		u32	r_idx;		/* "read" index (MQ only) */3544		u32	flag;3545	} u;3546};3547 3548/* Parameters used to populate WQE*/3549struct sli_bls_params {3550	u32		s_id;3551	u32		d_id;3552	u16		ox_id;3553	u16		rx_id;3554	u32		rpi;3555	u32		vpi;3556	bool		rpi_registered;3557	u8		payload[12];3558	u16		xri;3559	u16		tag;3560};3561 3562struct sli_els_params {3563	u32		s_id;3564	u32		d_id;3565	u16		ox_id;3566	u32		rpi;3567	u32		vpi;3568	bool		rpi_registered;3569	u32		xmit_len;3570	u32		rsp_len;3571	u8		timeout;3572	u8		cmd;3573	u16		xri;3574	u16		tag;3575};3576 3577struct sli_ct_params {3578	u8		r_ctl;3579	u8		type;3580	u8		df_ctl;3581	u8		timeout;3582	u16		ox_id;3583	u32		d_id;3584	u32		rpi;3585	u32		vpi;3586	bool		rpi_registered;3587	u32		xmit_len;3588	u32		rsp_len;3589	u16		xri;3590	u16		tag;3591};3592 3593struct sli_fcp_tgt_params {3594	u32		s_id;3595	u32		d_id;3596	u32		rpi;3597	u32		vpi;3598	u32		offset;3599	u16		ox_id;3600	u16		flags;3601	u8		cs_ctl;3602	u8		timeout;3603	u32		app_id;3604	u32		xmit_len;3605	u16		xri;3606	u16		tag;3607};3608 3609struct sli4_link_event {3610	enum sli4_link_status	status;3611	enum sli4_link_topology	topology;3612	enum sli4_link_medium	medium;3613	u32			speed;3614	u8			*loop_map;3615	u32			fc_id;3616};3617 3618enum sli4_resource {3619	SLI4_RSRC_VFI,3620	SLI4_RSRC_VPI,3621	SLI4_RSRC_RPI,3622	SLI4_RSRC_XRI,3623	SLI4_RSRC_FCFI,3624	SLI4_RSRC_MAX,3625};3626 3627struct sli4_extent {3628	u32		number;3629	u32		size;3630	u32		n_alloc;3631	u32		*base;3632	unsigned long	*use_map;3633	u32		map_size;3634};3635 3636struct sli4_queue_info {3637	u16	max_qcount[SLI4_QTYPE_MAX];3638	u32	max_qentries[SLI4_QTYPE_MAX];3639	u16	count_mask[SLI4_QTYPE_MAX];3640	u16	count_method[SLI4_QTYPE_MAX];3641	u32	qpage_count[SLI4_QTYPE_MAX];3642};3643 3644struct sli4_params {3645	u8	has_extents;3646	u8	auto_reg;3647	u8	auto_xfer_rdy;3648	u8	hdr_template_req;3649	u8	perf_hint;3650	u8	perf_wq_id_association;3651	u8	cq_create_version;3652	u8	mq_create_version;3653	u8	high_login_mode;3654	u8	sgl_pre_registered;3655	u8	sgl_pre_reg_required;3656	u8	t10_dif_inline_capable;3657	u8	t10_dif_separate_capable;3658};3659 3660struct sli4 {3661	void			*os;3662	struct pci_dev		*pci;3663	void __iomem		*reg[PCI_STD_NUM_BARS];3664 3665	u32			sli_rev;3666	u32			sli_family;3667	u32			if_type;3668 3669	u16			asic_type;3670	u16			asic_rev;3671 3672	u16			e_d_tov;3673	u16			r_a_tov;3674	struct sli4_queue_info	qinfo;3675	u16			link_module_type;3676	u8			rq_batch;3677	u8			port_number;3678	char			port_name[2];3679	u16			rq_min_buf_size;3680	u32			rq_max_buf_size;3681	u8			topology;3682	u8			wwpn[8];3683	u8			wwnn[8];3684	u32			fw_rev[2];3685	u8			fw_name[2][16];3686	char			ipl_name[16];3687	u32			hw_rev[3];3688	char			modeldesc[64];3689	char			bios_version_string[32];3690	u32			wqe_size;3691	u32			vpd_length;3692	/*3693	 * Tracks the port resources using extents metaphor. For3694	 * devices that don't implement extents (i.e.3695	 * has_extents == FALSE), the code models each resource as3696	 * a single large extent.3697	 */3698	struct sli4_extent	ext[SLI4_RSRC_MAX];3699	u32			features;3700	struct sli4_params	params;3701	u32			sge_supported_length;3702	u32			sgl_page_sizes;3703	u32			max_sgl_pages;3704 3705	/*3706	 * Callback functions3707	 */3708	int			(*link)(void *ctx, void *event);3709	void			*link_arg;3710 3711	struct efc_dma		bmbx;3712 3713	/* Save pointer to physical memory descriptor for non-embedded3714	 * SLI_CONFIG commands for BMBX dumping purposes3715	 */3716	struct efc_dma		*bmbx_non_emb_pmd;3717 3718	struct efc_dma		vpd_data;3719};3720 3721static inline void3722sli_cmd_fill_hdr(struct sli4_rqst_hdr *hdr, u8 opc, u8 sub, u32 ver, __le32 len)3723{3724	hdr->opcode = opc;3725	hdr->subsystem = sub;3726	hdr->dw3_version = cpu_to_le32(ver);3727	hdr->request_length = len;3728}3729 3730/**3731 * Get / set parameter functions3732 */3733 3734static inline u323735sli_get_max_sge(struct sli4 *sli4)3736{3737	return sli4->sge_supported_length;3738}3739 3740static inline u323741sli_get_max_sgl(struct sli4 *sli4)3742{3743	if (sli4->sgl_page_sizes != 1) {3744		efc_log_err(sli4, "unsupported SGL page sizes %#x\n",3745			    sli4->sgl_page_sizes);3746		return 0;3747	}3748 3749	return (sli4->max_sgl_pages * SLI_PAGE_SIZE) / sizeof(struct sli4_sge);3750}3751 3752static inline enum sli4_link_medium3753sli_get_medium(struct sli4 *sli4)3754{3755	switch (sli4->topology) {3756	case SLI4_READ_CFG_TOPO_FC:3757	case SLI4_READ_CFG_TOPO_FC_AL:3758	case SLI4_READ_CFG_TOPO_NON_FC_AL:3759		return SLI4_LINK_MEDIUM_FC;3760	default:3761		return SLI4_LINK_MEDIUM_MAX;3762	}3763}3764 3765static inline u323766sli_get_lmt(struct sli4 *sli4)3767{3768	return sli4->link_module_type;3769}3770 3771static inline int3772sli_set_topology(struct sli4 *sli4, u32 value)3773{3774	int	rc = 0;3775 3776	switch (value) {3777	case SLI4_READ_CFG_TOPO_FC:3778	case SLI4_READ_CFG_TOPO_FC_AL:3779	case SLI4_READ_CFG_TOPO_NON_FC_AL:3780		sli4->topology = value;3781		break;3782	default:3783		efc_log_err(sli4, "unsupported topology %#x\n", value);3784		rc = -1;3785	}3786 3787	return rc;3788}3789 3790static inline u323791sli_convert_mask_to_count(u32 method, u32 mask)3792{3793	u32 count = 0;3794 3795	if (method) {3796		count = 1 << (31 - __builtin_clz(mask));3797		count *= 16;3798	} else {3799		count = mask;3800	}3801 3802	return count;3803}3804 3805static inline u323806sli_reg_read_status(struct sli4 *sli)3807{3808	return readl(sli->reg[0] + SLI4_PORT_STATUS_REGOFF);3809}3810 3811static inline int3812sli_fw_error_status(struct sli4 *sli4)3813{3814	return (sli_reg_read_status(sli4) & SLI4_PORT_STATUS_ERR) ? 1 : 0;3815}3816 3817static inline u323818sli_reg_read_err1(struct sli4 *sli)3819{3820	return readl(sli->reg[0] + SLI4_PORT_ERROR1);3821}3822 3823static inline u323824sli_reg_read_err2(struct sli4 *sli)3825{3826	return readl(sli->reg[0] + SLI4_PORT_ERROR2);3827}3828 3829static inline int3830sli_fc_rqe_length(struct sli4 *sli4, void *cqe, u32 *len_hdr,3831		  u32 *len_data)3832{3833	struct sli4_fc_async_rcqe	*rcqe = cqe;3834 3835	*len_hdr = *len_data = 0;3836 3837	if (rcqe->status == SLI4_FC_ASYNC_RQ_SUCCESS) {3838		*len_hdr  = rcqe->hdpl_byte & SLI4_RACQE_HDPL;3839		*len_data = le16_to_cpu(rcqe->data_placement_length);3840		return 0;3841	} else {3842		return -1;3843	}3844}3845 3846static inline u83847sli_fc_rqe_fcfi(struct sli4 *sli4, void *cqe)3848{3849	u8 code = ((u8 *)cqe)[SLI4_CQE_CODE_OFFSET];3850	u8 fcfi = U8_MAX;3851 3852	switch (code) {3853	case SLI4_CQE_CODE_RQ_ASYNC: {3854		struct sli4_fc_async_rcqe *rcqe = cqe;3855 3856		fcfi = le16_to_cpu(rcqe->fcfi_rq_id_word) & SLI4_RACQE_FCFI;3857		break;3858	}3859	case SLI4_CQE_CODE_RQ_ASYNC_V1: {3860		struct sli4_fc_async_rcqe_v1 *rcqev1 = cqe;3861 3862		fcfi = rcqev1->fcfi_byte & SLI4_RACQE_FCFI;3863		break;3864	}3865	case SLI4_CQE_CODE_OPTIMIZED_WRITE_CMD: {3866		struct sli4_fc_optimized_write_cmd_cqe *opt_wr = cqe;3867 3868		fcfi = opt_wr->flags0 & SLI4_OCQE_FCFI;3869		break;3870	}3871	}3872 3873	return fcfi;3874}3875 3876/****************************************************************************3877 * Function prototypes3878 */3879int3880sli_cmd_config_link(struct sli4 *sli4, void *buf);3881int3882sli_cmd_down_link(struct sli4 *sli4, void *buf);3883int3884sli_cmd_dump_type4(struct sli4 *sli4, void *buf, u16 wki);3885int3886sli_cmd_common_read_transceiver_data(struct sli4 *sli4, void *buf,3887				     u32 page_num, struct efc_dma *dma);3888int3889sli_cmd_read_link_stats(struct sli4 *sli4, void *buf, u8 req_stats,3890			u8 clear_overflow_flags, u8 clear_all_counters);3891int3892sli_cmd_read_status(struct sli4 *sli4, void *buf, u8 clear);3893int3894sli_cmd_init_link(struct sli4 *sli4, void *buf, u32 speed,3895		  u8 reset_alpa);3896int3897sli_cmd_init_vfi(struct sli4 *sli4, void *buf, u16 vfi, u16 fcfi,3898		 u16 vpi);3899int3900sli_cmd_init_vpi(struct sli4 *sli4, void *buf, u16 vpi, u16 vfi);3901int3902sli_cmd_post_xri(struct sli4 *sli4, void *buf, u16 base, u16 cnt);3903int3904sli_cmd_release_xri(struct sli4 *sli4, void *buf, u8 num_xri);3905int3906sli_cmd_read_sparm64(struct sli4 *sli4, void *buf,3907		     struct efc_dma *dma, u16 vpi);3908int3909sli_cmd_read_topology(struct sli4 *sli4, void *buf, struct efc_dma *dma);3910int3911sli_cmd_read_nvparms(struct sli4 *sli4, void *buf);3912int3913sli_cmd_write_nvparms(struct sli4 *sli4, void *buf, u8 *wwpn,3914		      u8 *wwnn, u8 hard_alpa, u32 preferred_d_id);3915int3916sli_cmd_reg_fcfi(struct sli4 *sli4, void *buf, u16 index,3917		 struct sli4_cmd_rq_cfg *rq_cfg);3918int3919sli_cmd_reg_fcfi_mrq(struct sli4 *sli4, void *buf, u8 mode, u16 index,3920		     u8 rq_selection_policy, u8 mrq_bit_mask, u16 num_mrqs,3921		     struct sli4_cmd_rq_cfg *rq_cfg);3922int3923sli_cmd_reg_rpi(struct sli4 *sli4, void *buf, u32 rpi, u32 vpi, u32 fc_id,3924		struct efc_dma *dma, u8 update, u8 enable_t10_pi);3925int3926sli_cmd_unreg_fcfi(struct sli4 *sli4, void *buf, u16 indicator);3927int3928sli_cmd_unreg_rpi(struct sli4 *sli4, void *buf, u16 indicator,3929		  enum sli4_resource which, u32 fc_id);3930int3931sli_cmd_reg_vpi(struct sli4 *sli4, void *buf, u32 fc_id,3932		__be64 sli_wwpn, u16 vpi, u16 vfi, bool update);3933int3934sli_cmd_reg_vfi(struct sli4 *sli4, void *buf, size_t size,3935		u16 vfi, u16 fcfi, struct efc_dma dma,3936		u16 vpi, __be64 sli_wwpn, u32 fc_id);3937int3938sli_cmd_unreg_vpi(struct sli4 *sli4, void *buf, u16 id, u32 type);3939int3940sli_cmd_unreg_vfi(struct sli4 *sli4, void *buf, u16 idx, u32 type);3941int3942sli_cmd_common_nop(struct sli4 *sli4, void *buf, uint64_t context);3943int3944sli_cmd_common_get_resource_extent_info(struct sli4 *sli4, void *buf,3945					u16 rtype);3946int3947sli_cmd_common_get_sli4_parameters(struct sli4 *sli4, void *buf);3948int3949sli_cmd_common_write_object(struct sli4 *sli4, void *buf, u16 noc,3950		u16 eof, u32 len, u32 offset, char *name, struct efc_dma *dma);3951int3952sli_cmd_common_delete_object(struct sli4 *sli4, void *buf, char *object_name);3953int3954sli_cmd_common_read_object(struct sli4 *sli4, void *buf,3955		u32 length, u32 offset, char *name, struct efc_dma *dma);3956int3957sli_cmd_dmtf_exec_clp_cmd(struct sli4 *sli4, void *buf,3958		struct efc_dma *cmd, struct efc_dma *resp);3959int3960sli_cmd_common_set_dump_location(struct sli4 *sli4, void *buf,3961		bool query, bool is_buffer_list, struct efc_dma *dma, u8 fdb);3962int3963sli_cmd_common_set_features(struct sli4 *sli4, void *buf,3964			    u32 feature, u32 param_len, void *parameter);3965 3966int sli_cqe_mq(struct sli4 *sli4, void *buf);3967int sli_cqe_async(struct sli4 *sli4, void *buf);3968 3969int3970sli_setup(struct sli4 *sli4, void *os, struct pci_dev *pdev, void __iomem *r[]);3971void sli_calc_max_qentries(struct sli4 *sli4);3972int sli_init(struct sli4 *sli4);3973int sli_reset(struct sli4 *sli4);3974int sli_fw_reset(struct sli4 *sli4);3975void sli_teardown(struct sli4 *sli4);3976int3977sli_callback(struct sli4 *sli4, enum sli4_callback cb, void *func, void *arg);3978int3979sli_bmbx_command(struct sli4 *sli4);3980int3981__sli_queue_init(struct sli4 *sli4, struct sli4_queue *q, u32 qtype,3982		 size_t size, u32 n_entries, u32 align);3983int3984__sli_create_queue(struct sli4 *sli4, struct sli4_queue *q);3985int3986sli_eq_modify_delay(struct sli4 *sli4, struct sli4_queue *eq, u32 num_eq,3987		    u32 shift, u32 delay_mult);3988int3989sli_queue_alloc(struct sli4 *sli4, u32 qtype, struct sli4_queue *q,3990		u32 n_entries, struct sli4_queue *assoc);3991int3992sli_cq_alloc_set(struct sli4 *sli4, struct sli4_queue *qs[], u32 num_cqs,3993		 u32 n_entries, struct sli4_queue *eqs[]);3994int3995sli_get_queue_entry_size(struct sli4 *sli4, u32 qtype);3996int3997sli_queue_free(struct sli4 *sli4, struct sli4_queue *q, u32 destroy_queues,3998	       u32 free_memory);3999int4000sli_queue_eq_arm(struct sli4 *sli4, struct sli4_queue *q, bool arm);4001int4002sli_queue_arm(struct sli4 *sli4, struct sli4_queue *q, bool arm);4003 4004int4005sli_wq_write(struct sli4 *sli4, struct sli4_queue *q, u8 *entry);4006int4007sli_mq_write(struct sli4 *sli4, struct sli4_queue *q, u8 *entry);4008int4009sli_rq_write(struct sli4 *sli4, struct sli4_queue *q, u8 *entry);4010int4011sli_eq_read(struct sli4 *sli4, struct sli4_queue *q, u8 *entry);4012int4013sli_cq_read(struct sli4 *sli4, struct sli4_queue *q, u8 *entry);4014int4015sli_mq_read(struct sli4 *sli4, struct sli4_queue *q, u8 *entry);4016int4017sli_resource_alloc(struct sli4 *sli4, enum sli4_resource rtype, u32 *rid,4018		   u32 *index);4019int4020sli_resource_free(struct sli4 *sli4, enum sli4_resource rtype, u32 rid);4021int4022sli_resource_reset(struct sli4 *sli4, enum sli4_resource rtype);4023int4024sli_eq_parse(struct sli4 *sli4, u8 *buf, u16 *cq_id);4025int4026sli_cq_parse(struct sli4 *sli4, struct sli4_queue *cq, u8 *cqe,4027	     enum sli4_qentry *etype, u16 *q_id);4028 4029int sli_raise_ue(struct sli4 *sli4, u8 dump);4030int sli_dump_is_ready(struct sli4 *sli4);4031bool sli_reset_required(struct sli4 *sli4);4032bool sli_fw_ready(struct sli4 *sli4);4033 4034int4035sli_fc_process_link_attention(struct sli4 *sli4, void *acqe);4036int4037sli_fc_cqe_parse(struct sli4 *sli4, struct sli4_queue *cq,4038		 u8 *cqe, enum sli4_qentry *etype,4039		 u16 *rid);4040u32 sli_fc_response_length(struct sli4 *sli4, u8 *cqe);4041u32 sli_fc_io_length(struct sli4 *sli4, u8 *cqe);4042int sli_fc_els_did(struct sli4 *sli4, u8 *cqe, u32 *d_id);4043u32 sli_fc_ext_status(struct sli4 *sli4, u8 *cqe);4044int4045sli_fc_rqe_rqid_and_index(struct sli4 *sli4, u8 *cqe, u16 *rq_id, u32 *index);4046int4047sli_cmd_wq_create(struct sli4 *sli4, void *buf,4048		  struct efc_dma *qmem, u16 cq_id);4049int sli_cmd_post_sgl_pages(struct sli4 *sli4, void *buf, u16 xri,4050		u32 xri_count, struct efc_dma *page0[], struct efc_dma *page1[],4051		struct efc_dma *dma);4052int4053sli_cmd_post_hdr_templates(struct sli4 *sli4, void *buf,4054		struct efc_dma *dma, u16 rpi, struct efc_dma *payload_dma);4055int4056sli_fc_rq_alloc(struct sli4 *sli4, struct sli4_queue *q, u32 n_entries,4057		u32 buffer_size, struct sli4_queue *cq, bool is_hdr);4058int4059sli_fc_rq_set_alloc(struct sli4 *sli4, u32 num_rq_pairs, struct sli4_queue *q[],4060		u32 base_cq_id, u32 num, u32 hdr_buf_size, u32 data_buf_size);4061u32 sli_fc_get_rpi_requirements(struct sli4 *sli4, u32 n_rpi);4062int4063sli_abort_wqe(struct sli4 *sli4, void *buf, enum sli4_abort_type type,4064	      bool send_abts, u32 ids, u32 mask, u16 tag, u16 cq_id);4065 4066int4067sli_send_frame_wqe(struct sli4 *sli4, void *buf, u8 sof, u8 eof,4068		   u32 *hdr, struct efc_dma *payload, u32 req_len, u8 timeout,4069		   u16 xri, u16 req_tag);4070 4071int4072sli_xmit_els_rsp64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *rsp,4073		       struct sli_els_params *params);4074 4075int4076sli_els_request64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *sgl,4077		      struct sli_els_params *params);4078 4079int4080sli_fcp_icmnd64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *sgl, u16 xri,4081		    u16 tag, u16 cq_id, u32 rpi, u32 rnode_fcid, u8 timeout);4082 4083int4084sli_fcp_iread64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *sgl,4085		    u32 first_data_sge, u32 xfer_len, u16 xri,4086		    u16 tag, u16 cq_id, u32 rpi, u32 rnode_fcid, u8 dif, u8 bs,4087		    u8 timeout);4088 4089int4090sli_fcp_iwrite64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *sgl,4091		     u32 first_data_sge, u32 xfer_len,4092		     u32 first_burst, u16 xri, u16 tag, u16 cq_id, u32 rpi,4093		     u32 rnode_fcid, u8 dif, u8 bs, u8 timeout);4094 4095int4096sli_fcp_treceive64_wqe(struct sli4 *sli, void *buf, struct efc_dma *sgl,4097		       u32 first_data_sge, u16 cq_id, u8 dif, u8 bs,4098		       struct sli_fcp_tgt_params *params);4099int4100sli_fcp_cont_treceive64_wqe(struct sli4 *sli, void *buf, struct efc_dma *sgl,4101			    u32 first_data_sge, u16 sec_xri, u16 cq_id, u8 dif,4102			    u8 bs, struct sli_fcp_tgt_params *params);4103 4104int4105sli_fcp_trsp64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *sgl,4106		   u16 cq_id, u8 port_owned, struct sli_fcp_tgt_params *params);4107 4108int4109sli_fcp_tsend64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *sgl,4110		    u32 first_data_sge, u16 cq_id, u8 dif, u8 bs,4111		    struct sli_fcp_tgt_params *params);4112int4113sli_gen_request64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *sgl,4114		      struct sli_ct_params *params);4115 4116int4117sli_xmit_bls_rsp64_wqe(struct sli4 *sli4, void *buf,4118		struct sli_bls_payload *payload, struct sli_bls_params *params);4119 4120int4121sli_xmit_sequence64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *payload,4122			struct sli_ct_params *params);4123 4124int4125sli_requeue_xri_wqe(struct sli4 *sli4, void *buf, u16 xri, u16 tag, u16 cq_id);4126void4127sli4_cmd_lowlevel_set_watchdog(struct sli4 *sli4, void *buf, size_t size,4128			       u16 timeout);4129 4130const char *sli_fc_get_status_string(u32 status);4131 4132#endif /* !_SLI4_H */4133