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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Driver for Broadcom MPI3 Storage Controllers4 *5 * Copyright (C) 2017-2023 Broadcom Inc.6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)7 *8 */9 10#ifndef MPI3MR_H_INCLUDED11#define MPI3MR_H_INCLUDED12 13#include <linux/blkdev.h>14#include <linux/blk-mq.h>15#include <linux/blk-mq-pci.h>16#include <linux/delay.h>17#include <linux/dmapool.h>18#include <linux/errno.h>19#include <linux/init.h>20#include <linux/io.h>21#include <linux/interrupt.h>22#include <linux/kernel.h>23#include <linux/miscdevice.h>24#include <linux/module.h>25#include <linux/pci.h>26#include <linux/aer.h>27#include <linux/poll.h>28#include <linux/sched.h>29#include <linux/slab.h>30#include <linux/types.h>31#include <linux/uaccess.h>32#include <linux/utsname.h>33#include <linux/workqueue.h>34#include <linux/unaligned.h>35#include <scsi/scsi.h>36#include <scsi/scsi_cmnd.h>37#include <scsi/scsi_dbg.h>38#include <scsi/scsi_device.h>39#include <scsi/scsi_host.h>40#include <scsi/scsi_tcq.h>41#include <uapi/scsi/scsi_bsg_mpi3mr.h>42#include <scsi/scsi_transport_sas.h>43 44#include "mpi/mpi30_transport.h"45#include "mpi/mpi30_cnfg.h"46#include "mpi/mpi30_image.h"47#include "mpi/mpi30_init.h"48#include "mpi/mpi30_ioc.h"49#include "mpi/mpi30_sas.h"50#include "mpi/mpi30_pci.h"51#include "mpi/mpi30_tool.h"52#include "mpi3mr_debug.h"53 54/* Global list and lock for storing multiple adapters managed by the driver */55extern spinlock_t mrioc_list_lock;56extern struct list_head mrioc_list;57extern int prot_mask;58extern atomic64_t event_counter;59 60#define MPI3MR_DRIVER_VERSION "8.12.0.0.50"61#define MPI3MR_DRIVER_RELDATE "05-Sept-2024"62 63#define MPI3MR_DRIVER_NAME "mpi3mr"64#define MPI3MR_DRIVER_LICENSE "GPL"65#define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"66#define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver"67 68#define MPI3MR_NAME_LENGTH 6469#define IOCNAME "%s: "70 71#define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024)72 73/* Definitions for internal SGL and Chain SGL buffers */74#define MPI3MR_PAGE_SIZE_4K 409675#define MPI3MR_DEFAULT_SGL_ENTRIES 25676#define MPI3MR_MAX_SGL_ENTRIES 204877 78/* Definitions for MAX values for shost */79#define MPI3MR_MAX_CMDS_LUN 12880#define MPI3MR_MAX_CDB_LENGTH 3281 82/* Admin queue management definitions */83#define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K)84#define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K)85#define MPI3MR_ADMIN_REQ_FRAME_SZ 12886#define MPI3MR_ADMIN_REPLY_FRAME_SZ 1687 88/* Operational queue management definitions */89#define MPI3MR_OP_REQ_Q_QD 51290#define MPI3MR_OP_REP_Q_QD 102491#define MPI3MR_OP_REP_Q_QD4K 409692#define MPI3MR_OP_REQ_Q_SEG_SIZE 409693#define MPI3MR_OP_REP_Q_SEG_SIZE 409694#define MPI3MR_MAX_SEG_LIST_SIZE 409695 96/* Reserved Host Tag definitions */97#define MPI3MR_HOSTTAG_INVALID 0xFFFF98#define MPI3MR_HOSTTAG_INITCMDS 199#define MPI3MR_HOSTTAG_BSG_CMDS 2100#define MPI3MR_HOSTTAG_PEL_ABORT 3101#define MPI3MR_HOSTTAG_PEL_WAIT 4102#define MPI3MR_HOSTTAG_BLK_TMS 5103#define MPI3MR_HOSTTAG_CFG_CMDS 6104#define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7105 106#define MPI3MR_NUM_DEVRMCMD 16107#define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1)108#define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \109 MPI3MR_NUM_DEVRMCMD - 1)110 111#define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX112#define MPI3MR_NUM_EVTACKCMD 4113#define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)114#define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \115 MPI3MR_NUM_EVTACKCMD - 1)116 117/* Reduced resource count definition for crash kernel */118#define MPI3MR_HOST_IOS_KDUMP 128119 120/* command/controller interaction timeout definitions in seconds */121#define MPI3MR_INTADMCMD_TIMEOUT 60122#define MPI3MR_PORTENABLE_TIMEOUT 300123#define MPI3MR_PORTENABLE_POLL_INTERVAL 5124#define MPI3MR_ABORTTM_TIMEOUT 60125#define MPI3MR_RESETTM_TIMEOUT 60126#define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5127#define MPI3MR_TSUPDATE_INTERVAL 900128#define MPI3MR_DEFAULT_SHUTDOWN_TIME 120129#define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180130#define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180131#define MPI3MR_RESET_ACK_TIMEOUT 30132#define MPI3MR_MUR_TIMEOUT 120133#define MPI3MR_RESET_TIMEOUT 510134 135#define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */136 137#define MPI3MR_DEFAULT_CFG_PAGE_SZ 1024 /* in bytes */138 139#define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10140 141#define MPI3MR_SCMD_TIMEOUT (60 * HZ)142#define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ)143 144/* Internal admin command state definitions*/145#define MPI3MR_CMD_NOTUSED 0x8000146#define MPI3MR_CMD_COMPLETE 0x0001147#define MPI3MR_CMD_PENDING 0x0002148#define MPI3MR_CMD_REPLY_VALID 0x0004149#define MPI3MR_CMD_RESET 0x0008150 151/* Definitions for Event replies and sense buffer allocated per controller */152#define MPI3MR_NUM_EVT_REPLIES 64153#define MPI3MR_SENSE_BUF_SZ 256154#define MPI3MR_SENSEBUF_FACTOR 3155#define MPI3MR_CHAINBUF_FACTOR 3156#define MPI3MR_CHAINBUFDIX_FACTOR 2157 158/* Invalid target device handle */159#define MPI3MR_INVALID_DEV_HANDLE 0xFFFF160 161/* Controller Reset related definitions */162#define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5163#define MPI3MR_MAX_RESET_RETRY_COUNT 3164 165/* ResponseCode definitions */166#define MPI3MR_RI_MASK_RESPCODE (0x000000FF)167#define MPI3MR_RSP_IO_QUEUED_ON_IOC \168 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC169 170#define MPI3MR_DEFAULT_MDTS (128 * 1024)171#define MPI3MR_DEFAULT_PGSZEXP (12)172 173/* Command retry count definitions */174#define MPI3MR_DEV_RMHS_RETRY_COUNT 3175#define MPI3MR_PEL_RETRY_COUNT 3176 177/* Default target device queue depth */178#define MPI3MR_DEFAULT_SDEV_QD 32179 180/* Definitions for Threaded IRQ poll*/181#define MPI3MR_IRQ_POLL_SLEEP 20182#define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8183 184/* Definitions for the controller security status*/185#define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C186#define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02187 188#define MPI3MR_INVALID_DEVICE 0x00189#define MPI3MR_CONFIG_SECURE_DEVICE 0x04190#define MPI3MR_HARD_SECURE_DEVICE 0x08191#define MPI3MR_TAMPERED_DEVICE 0x0C192 193#define MPI3MR_DEFAULT_HDB_MAX_SZ (4 * 1024 * 1024)194#define MPI3MR_DEFAULT_HDB_DEC_SZ (1 * 1024 * 1024)195#define MPI3MR_DEFAULT_HDB_MIN_SZ (2 * 1024 * 1024)196#define MPI3MR_MAX_NUM_HDB 2197 198#define MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN 0199#define MPI3MR_HDB_TRIGGER_TYPE_FAULT 1200#define MPI3MR_HDB_TRIGGER_TYPE_ELEMENT 2201#define MPI3MR_HDB_TRIGGER_TYPE_GLOBAL 3202#define MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET 4203#define MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED 5204 205#define MPI3MR_HDB_REFRESH_TYPE_RESERVED 0206#define MPI3MR_HDB_REFRESH_TYPE_CURRENT 1207#define MPI3MR_HDB_REFRESH_TYPE_DEFAULT 2208#define MPI3MR_HDB_HDB_REFRESH_TYPE_PERSISTENT 3209 210#define MPI3MR_DEFAULT_HDB_SZ (4 * 1024 * 1024)211#define MPI3MR_MAX_NUM_HDB 2212 213#define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_INDEX 0214#define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_DATA 1215 216#define MPI3MR_THRESHOLD_REPLY_COUNT 100217 218/* SGE Flag definition */219#define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \220 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \221 MPI3_SGE_FLAGS_END_OF_LIST)222 223/* MSI Index from Reply Queue Index */224#define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset)225 226/*227 * Maximum data transfer size definitions for management228 * application commands229 */230#define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024)231#define MPI3MR_MAX_APP_XFER_SEGMENTS 512232/*233 * 2048 sectors are for data buffers and additional 512 sectors for234 * other buffers235 */236#define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512)237 238#define MPI3MR_WRITE_SAME_MAX_LEN_256_BLKS 256239#define MPI3MR_WRITE_SAME_MAX_LEN_2048_BLKS 2048240 241#define MPI3MR_DRIVER_EVENT_PROCESS_TRIGGER (0xFFFD)242 243/**244 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe245 * Encapsulated commands.246 *247 * @base_addr: Physical address248 * @length: SGE length249 * @rsvd: Reserved250 * @rsvd1: Reserved251 * @sub_type: sgl sub type252 * @type: sgl type253 */254struct mpi3mr_nvme_pt_sge {255 __le64 base_addr;256 __le32 length;257 u16 rsvd;258 u8 rsvd1;259 u8 sub_type:4;260 u8 type:4;261};262 263/**264 * struct mpi3mr_buf_map - local structure to265 * track kernel and user buffers associated with an BSG266 * structure.267 *268 * @bsg_buf: BSG buffer virtual address269 * @bsg_buf_len: BSG buffer length270 * @kern_buf: Kernel buffer virtual address271 * @kern_buf_len: Kernel buffer length272 * @kern_buf_dma: Kernel buffer DMA address273 * @data_dir: Data direction.274 */275struct mpi3mr_buf_map {276 void *bsg_buf;277 u32 bsg_buf_len;278 void *kern_buf;279 u32 kern_buf_len;280 dma_addr_t kern_buf_dma;281 u8 data_dir;282 u16 num_dma_desc;283 struct dma_memory_desc *dma_desc;284};285 286/* IOC State definitions */287enum mpi3mr_iocstate {288 MRIOC_STATE_READY = 1,289 MRIOC_STATE_RESET,290 MRIOC_STATE_FAULT,291 MRIOC_STATE_BECOMING_READY,292 MRIOC_STATE_RESET_REQUESTED,293 MRIOC_STATE_UNRECOVERABLE,294};295 296/* Reset reason code definitions*/297enum mpi3mr_reset_reason {298 MPI3MR_RESET_FROM_BRINGUP = 1,299 MPI3MR_RESET_FROM_FAULT_WATCH = 2,300 MPI3MR_RESET_FROM_APP = 3,301 MPI3MR_RESET_FROM_EH_HOS = 4,302 MPI3MR_RESET_FROM_TM_TIMEOUT = 5,303 MPI3MR_RESET_FROM_APP_TIMEOUT = 6,304 MPI3MR_RESET_FROM_MUR_FAILURE = 7,305 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,306 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,307 MPI3MR_RESET_FROM_PE_TIMEOUT = 10,308 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,309 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,310 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,311 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,312 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,313 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,314 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,315 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,316 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,317 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,318 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,319 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,320 MPI3MR_RESET_FROM_SYSFS = 23,321 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,322 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25,323 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT = 26,324 MPI3MR_RESET_FROM_FIRMWARE = 27,325 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29,326 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30,327 MPI3MR_RESET_FROM_TRIGGER = 31,328};329 330#define MPI3MR_RESET_REASON_OSTYPE_LINUX 1331#define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28332#define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20333 334/* Queue type definitions */335enum queue_type {336 MPI3MR_DEFAULT_QUEUE = 0,337 MPI3MR_POLL_QUEUE,338};339 340/**341 * struct mpi3mr_compimg_ver - replica of component image342 * version defined in mpi30_image.h in host endianness343 *344 */345struct mpi3mr_compimg_ver {346 u16 build_num;347 u16 cust_id;348 u8 ph_minor;349 u8 ph_major;350 u8 gen_minor;351 u8 gen_major;352};353 354/**355 * struct mpi3mr_ioc_facs - replica of component image version356 * defined in mpi30_ioc.h in host endianness357 *358 */359struct mpi3mr_ioc_facts {360 u32 ioc_capabilities;361 struct mpi3mr_compimg_ver fw_ver;362 u32 mpi_version;363 u32 diag_trace_sz;364 u32 diag_fw_sz;365 u32 diag_drvr_sz;366 u16 max_reqs;367 u16 product_id;368 u16 op_req_sz;369 u16 reply_sz;370 u16 exceptions;371 u16 max_perids;372 u16 max_pds;373 u16 max_sasexpanders;374 u32 max_data_length;375 u16 max_sasinitiators;376 u16 max_enclosures;377 u16 max_pcie_switches;378 u16 max_nvme;379 u16 max_vds;380 u16 max_hpds;381 u16 max_advhpds;382 u16 max_raid_pds;383 u16 min_devhandle;384 u16 max_devhandle;385 u16 max_op_req_q;386 u16 max_op_reply_q;387 u16 shutdown_timeout;388 u8 ioc_num;389 u8 who_init;390 u16 max_msix_vectors;391 u8 personality;392 u8 dma_mask;393 u8 protocol_flags;394 u8 sge_mod_mask;395 u8 sge_mod_value;396 u8 sge_mod_shift;397 u8 max_dev_per_tg;398 u16 max_io_throttle_group;399 u16 io_throttle_data_length;400 u16 io_throttle_low;401 u16 io_throttle_high;402 403};404 405/**406 * struct segments - memory descriptor structure to store407 * virtual and dma addresses for operational queue segments.408 *409 * @segment: virtual address410 * @segment_dma: dma address411 */412struct segments {413 void *segment;414 dma_addr_t segment_dma;415};416 417/**418 * struct op_req_qinfo - Operational Request Queue Information419 *420 * @ci: consumer index421 * @pi: producer index422 * @num_request: Maximum number of entries in the queue423 * @qid: Queue Id starting from 1424 * @reply_qid: Associated reply queue Id425 * @num_segments: Number of discontiguous memory segments426 * @segment_qd: Depth of each segments427 * @q_lock: Concurrent queue access lock428 * @q_segments: Segment descriptor pointer429 * @q_segment_list: Segment list base virtual address430 * @q_segment_list_dma: Segment list base DMA address431 */432struct op_req_qinfo {433 u16 ci;434 u16 pi;435 u16 num_requests;436 u16 qid;437 u16 reply_qid;438 u16 num_segments;439 u16 segment_qd;440 spinlock_t q_lock;441 struct segments *q_segments;442 void *q_segment_list;443 dma_addr_t q_segment_list_dma;444};445 446/**447 * struct op_reply_qinfo - Operational Reply Queue Information448 *449 * @ci: consumer index450 * @qid: Queue Id starting from 1451 * @num_replies: Maximum number of entries in the queue452 * @num_segments: Number of discontiguous memory segments453 * @segment_qd: Depth of each segments454 * @q_segments: Segment descriptor pointer455 * @q_segment_list: Segment list base virtual address456 * @q_segment_list_dma: Segment list base DMA address457 * @ephase: Expected phased identifier for the reply queue458 * @pend_ios: Number of IOs pending in HW for this queue459 * @enable_irq_poll: Flag to indicate polling is enabled460 * @in_use: Queue is handled by poll/ISR461 * @qtype: Type of queue (types defined in enum queue_type)462 */463struct op_reply_qinfo {464 u16 ci;465 u16 qid;466 u16 num_replies;467 u16 num_segments;468 u16 segment_qd;469 struct segments *q_segments;470 void *q_segment_list;471 dma_addr_t q_segment_list_dma;472 u8 ephase;473 atomic_t pend_ios;474 bool enable_irq_poll;475 atomic_t in_use;476 enum queue_type qtype;477};478 479/**480 * struct mpi3mr_intr_info - Interrupt cookie information481 *482 * @mrioc: Adapter instance reference483 * @os_irq: irq number484 * @msix_index: MSIx index485 * @op_reply_q: Associated operational reply queue486 * @name: Dev name for the irq claiming device487 */488struct mpi3mr_intr_info {489 struct mpi3mr_ioc *mrioc;490 int os_irq;491 u16 msix_index;492 struct op_reply_qinfo *op_reply_q;493 char name[MPI3MR_NAME_LENGTH];494};495 496/**497 * struct mpi3mr_throttle_group_info - Throttle group info498 *499 * @io_divert: Flag indicates io divert is on or off for the TG500 * @need_qd_reduction: Flag to indicate QD reduction is needed501 * @qd_reduction: Queue Depth reduction in units of 10%502 * @fw_qd: QueueDepth value reported by the firmware503 * @modified_qd: Modified QueueDepth value due to throttling504 * @id: Throttle Group ID.505 * @high: High limit to turn on throttling in 512 byte blocks506 * @low: Low limit to turn off throttling in 512 byte blocks507 * @pend_large_data_sz: Counter to track pending large data508 */509struct mpi3mr_throttle_group_info {510 u8 io_divert;511 u8 need_qd_reduction;512 u8 qd_reduction;513 u16 fw_qd;514 u16 modified_qd;515 u16 id;516 u32 high;517 u32 low;518 atomic_t pend_large_data_sz;519};520 521/* HBA port flags */522#define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01523#define MPI3MR_HBA_PORT_FLAG_NEW 0x02524 525/* IOCTL data transfer sge*/526#define MPI3MR_NUM_IOCTL_SGE 256527#define MPI3MR_IOCTL_SGE_SIZE (8 * 1024)528 529/**530 * struct mpi3mr_hba_port - HBA's port information531 * @port_id: Port number532 * @flags: HBA port flags533 */534struct mpi3mr_hba_port {535 struct list_head list;536 u8 port_id;537 u8 flags;538};539 540/**541 * struct mpi3mr_sas_port - Internal SAS port information542 * @port_list: List of ports belonging to a SAS node543 * @num_phys: Number of phys associated with port544 * @marked_responding: used while refresing the sas ports545 * @lowest_phy: lowest phy ID of current sas port, valid for controller port546 * @phy_mask: phy_mask of current sas port, valid for controller port547 * @hba_port: HBA port entry548 * @remote_identify: Attached device identification549 * @rphy: SAS transport layer rphy object550 * @port: SAS transport layer port object551 * @phy_list: mpi3mr_sas_phy objects belonging to this port552 */553struct mpi3mr_sas_port {554 struct list_head port_list;555 u8 num_phys;556 u8 marked_responding;557 int lowest_phy;558 u64 phy_mask;559 struct mpi3mr_hba_port *hba_port;560 struct sas_identify remote_identify;561 struct sas_rphy *rphy;562 struct sas_port *port;563 struct list_head phy_list;564};565 566/**567 * struct mpi3mr_sas_phy - Internal SAS Phy information568 * @port_siblings: List of phys belonging to a port569 * @identify: Phy identification570 * @remote_identify: Attached device identification571 * @phy: SAS transport layer Phy object572 * @phy_id: Unique phy id within a port573 * @handle: Firmware device handle for this phy574 * @attached_handle: Firmware device handle for attached device575 * @phy_belongs_to_port: Flag to indicate phy belongs to port576 @hba_port: HBA port entry577 */578struct mpi3mr_sas_phy {579 struct list_head port_siblings;580 struct sas_identify identify;581 struct sas_identify remote_identify;582 struct sas_phy *phy;583 u8 phy_id;584 u16 handle;585 u16 attached_handle;586 u8 phy_belongs_to_port;587 struct mpi3mr_hba_port *hba_port;588};589 590/**591 * struct mpi3mr_sas_node - SAS host/expander information592 * @list: List of sas nodes in a controller593 * @parent_dev: Parent device class594 * @num_phys: Number phys belonging to sas_node595 * @sas_address: SAS address of sas_node596 * @handle: Firmware device handle for this sas_host/expander597 * @sas_address_parent: SAS address of parent expander or host598 * @enclosure_handle: Firmware handle of enclosure of this node599 * @device_info: Capabilities of this sas_host/expander600 * @non_responding: used to refresh the expander devices during reset601 * @host_node: Flag to indicate this is a host_node602 * @hba_port: HBA port entry603 * @phy: A list of phys that make up this sas_host/expander604 * @sas_port_list: List of internal ports of this node605 * @rphy: sas_rphy object of this expander node606 */607struct mpi3mr_sas_node {608 struct list_head list;609 struct device *parent_dev;610 u8 num_phys;611 u64 sas_address;612 u16 handle;613 u64 sas_address_parent;614 u16 enclosure_handle;615 u64 enclosure_logical_id;616 u8 non_responding;617 u8 host_node;618 struct mpi3mr_hba_port *hba_port;619 struct mpi3mr_sas_phy *phy;620 struct list_head sas_port_list;621 struct sas_rphy *rphy;622};623 624/**625 * struct mpi3mr_enclosure_node - enclosure information626 * @list: List of enclosures627 * @pg0: Enclosure page 0;628 */629struct mpi3mr_enclosure_node {630 struct list_head list;631 struct mpi3_enclosure_page0 pg0;632};633 634/**635 * struct tgt_dev_sas_sata - SAS/SATA device specific636 * information cached from firmware given data637 *638 * @sas_address: World wide unique SAS address639 * @sas_address_parent: Sas address of parent expander or host640 * @dev_info: Device information bits641 * @phy_id: Phy identifier provided in device page 0642 * @attached_phy_id: Attached phy identifier provided in device page 0643 * @sas_transport_attached: Is this device exposed to transport644 * @pend_sas_rphy_add: Flag to check device is in process of add645 * @hba_port: HBA port entry646 * @rphy: SAS transport layer rphy object647 */648struct tgt_dev_sas_sata {649 u64 sas_address;650 u64 sas_address_parent;651 u16 dev_info;652 u8 phy_id;653 u8 attached_phy_id;654 u8 sas_transport_attached;655 u8 pend_sas_rphy_add;656 struct mpi3mr_hba_port *hba_port;657 struct sas_rphy *rphy;658};659 660/**661 * struct tgt_dev_pcie - PCIe device specific information cached662 * from firmware given data663 *664 * @mdts: Maximum data transfer size665 * @capb: Device capabilities666 * @pgsz: Device page size667 * @abort_to: Timeout for abort TM668 * @reset_to: Timeout for Target/LUN reset TM669 * @dev_info: Device information bits670 */671struct tgt_dev_pcie {672 u32 mdts;673 u16 capb;674 u8 pgsz;675 u8 abort_to;676 u8 reset_to;677 u16 dev_info;678};679 680/**681 * struct tgt_dev_vd - virtual device specific information682 * cached from firmware given data683 *684 * @state: State of the VD685 * @tg_qd_reduction: Queue Depth reduction in units of 10%686 * @tg_id: VDs throttle group ID687 * @high: High limit to turn on throttling in 512 byte blocks688 * @low: Low limit to turn off throttling in 512 byte blocks689 * @tg: Pointer to throttle group info690 */691struct tgt_dev_vd {692 u8 state;693 u8 tg_qd_reduction;694 u16 tg_id;695 u32 tg_high;696 u32 tg_low;697 struct mpi3mr_throttle_group_info *tg;698};699 700 701/**702 * union _form_spec_inf - union of device specific information703 */704union _form_spec_inf {705 struct tgt_dev_sas_sata sas_sata_inf;706 struct tgt_dev_pcie pcie_inf;707 struct tgt_dev_vd vd_inf;708};709 710enum mpi3mr_dev_state {711 MPI3MR_DEV_CREATED = 1,712 MPI3MR_DEV_REMOVE_HS_STARTED = 2,713 MPI3MR_DEV_DELETED = 3,714};715 716/**717 * struct mpi3mr_tgt_dev - target device data structure718 *719 * @list: List pointer720 * @starget: Scsi_target pointer721 * @dev_handle: FW device handle722 * @parent_handle: FW parent device handle723 * @slot: Slot number724 * @encl_handle: FW enclosure handle725 * @perst_id: FW assigned Persistent ID726 * @devpg0_flag: Device Page0 flag727 * @dev_type: SAS/SATA/PCIE device type728 * @is_hidden: Should be exposed to upper layers or not729 * @host_exposed: Already exposed to host or not730 * @io_unit_port: IO Unit port ID731 * @non_stl: Is this device not to be attached with SAS TL732 * @io_throttle_enabled: I/O throttling needed or not733 * @wslen: Write same max length734 * @q_depth: Device specific Queue Depth735 * @wwid: World wide ID736 * @enclosure_logical_id: Enclosure logical identifier737 * @dev_spec: Device type specific information738 * @ref_count: Reference count739 * @state: device state740 */741struct mpi3mr_tgt_dev {742 struct list_head list;743 struct scsi_target *starget;744 u16 dev_handle;745 u16 parent_handle;746 u16 slot;747 u16 encl_handle;748 u16 perst_id;749 u16 devpg0_flag;750 u8 dev_type;751 u8 is_hidden;752 u8 host_exposed;753 u8 io_unit_port;754 u8 non_stl;755 u8 io_throttle_enabled;756 u16 wslen;757 u16 q_depth;758 u64 wwid;759 u64 enclosure_logical_id;760 union _form_spec_inf dev_spec;761 struct kref ref_count;762 enum mpi3mr_dev_state state;763};764 765/**766 * mpi3mr_tgtdev_get - k reference incrementor767 * @s: Target device reference768 *769 * Increment target device reference count.770 */771static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)772{773 kref_get(&s->ref_count);774}775 776/**777 * mpi3mr_free_tgtdev - target device memory dealloctor778 * @r: k reference pointer of the target device779 *780 * Free target device memory when no reference.781 */782static inline void mpi3mr_free_tgtdev(struct kref *r)783{784 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));785}786 787/**788 * mpi3mr_tgtdev_put - k reference decrementor789 * @s: Target device reference790 *791 * Decrement target device reference count.792 */793static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)794{795 kref_put(&s->ref_count, mpi3mr_free_tgtdev);796}797 798 799/**800 * struct mpi3mr_stgt_priv_data - SCSI target private structure801 *802 * @starget: Scsi_target pointer803 * @dev_handle: FW device handle804 * @perst_id: FW assigned Persistent ID805 * @num_luns: Number of Logical Units806 * @block_io: I/O blocked to the device or not807 * @dev_removed: Device removed in the Firmware808 * @dev_removedelay: Device is waiting to be removed in FW809 * @dev_type: Device type810 * @dev_nvme_dif: Device is NVMe DIF enabled811 * @wslen: Write same max length812 * @io_throttle_enabled: I/O throttling needed or not813 * @io_divert: Flag indicates io divert is on or off for the dev814 * @throttle_group: Pointer to throttle group info815 * @tgt_dev: Internal target device pointer816 * @pend_count: Counter to track pending I/Os during error817 * handling818 */819struct mpi3mr_stgt_priv_data {820 struct scsi_target *starget;821 u16 dev_handle;822 u16 perst_id;823 u32 num_luns;824 atomic_t block_io;825 u8 dev_removed;826 u8 dev_removedelay;827 u8 dev_type;828 u8 dev_nvme_dif;829 u16 wslen;830 u8 io_throttle_enabled;831 u8 io_divert;832 struct mpi3mr_throttle_group_info *throttle_group;833 struct mpi3mr_tgt_dev *tgt_dev;834 u32 pend_count;835};836 837/**838 * struct mpi3mr_stgt_priv_data - SCSI device private structure839 *840 * @tgt_priv_data: Scsi_target private data pointer841 * @lun_id: LUN ID of the device842 * @ncq_prio_enable: NCQ priority enable for SATA device843 * @pend_count: Counter to track pending I/Os during error844 * handling845 * @wslen: Write same max length846 */847struct mpi3mr_sdev_priv_data {848 struct mpi3mr_stgt_priv_data *tgt_priv_data;849 u32 lun_id;850 u8 ncq_prio_enable;851 u32 pend_count;852 u16 wslen;853};854 855/**856 * struct mpi3mr_drv_cmd - Internal command tracker857 *858 * @mutex: Command mutex859 * @done: Completeor for wakeup860 * @reply: Firmware reply for internal commands861 * @sensebuf: Sensebuf for SCSI IO commands862 * @iou_rc: IO Unit control reason code863 * @state: Command State864 * @dev_handle: Firmware handle for device specific commands865 * @ioc_status: IOC status from the firmware866 * @ioc_loginfo:IOC log info from the firmware867 * @is_waiting: Is the command issued in block mode868 * @is_sense: Is Sense data present869 * @retry_count: Retry count for retriable commands870 * @host_tag: Host tag used by the command871 * @callback: Callback for non blocking commands872 */873struct mpi3mr_drv_cmd {874 struct mutex mutex;875 struct completion done;876 void *reply;877 u8 *sensebuf;878 u8 iou_rc;879 u16 state;880 u16 dev_handle;881 u16 ioc_status;882 u32 ioc_loginfo;883 u8 is_waiting;884 u8 is_sense;885 u8 retry_count;886 u16 host_tag;887 888 void (*callback)(struct mpi3mr_ioc *mrioc,889 struct mpi3mr_drv_cmd *drv_cmd);890};891 892/**893 * union mpi3mr_trigger_data - Trigger data information894 * @fault: Fault code895 * @global: Global trigger data896 * @element: element trigger data897 */898union mpi3mr_trigger_data {899 u16 fault;900 u64 global;901 union mpi3_driver2_trigger_element element;902};903 904/**905 * struct trigger_event_data - store trigger related906 * information.907 *908 * @trace_hdb: Trace diag buffer descriptor reference909 * @fw_hdb: FW diag buffer descriptor reference910 * @trigger_type: Trigger type911 * @trigger_specific_data: Trigger specific data912 * @snapdump: Snapdump enable or disable flag913 */914struct trigger_event_data {915 struct diag_buffer_desc *trace_hdb;916 struct diag_buffer_desc *fw_hdb;917 u8 trigger_type;918 union mpi3mr_trigger_data trigger_specific_data;919 bool snapdump;920};921 922/**923 * struct diag_buffer_desc - memory descriptor structure to924 * store virtual, dma addresses, size, buffer status for host925 * diagnostic buffers.926 *927 * @type: Buffer type928 * @trigger_data: Trigger data929 * @trigger_type: Trigger type930 * @status: Buffer status931 * @size: Buffer size932 * @addr: Virtual address933 * @dma_addr: Buffer DMA address934 */935struct diag_buffer_desc {936 u8 type;937 union mpi3mr_trigger_data trigger_data;938 u8 trigger_type;939 u8 status;940 u32 size;941 void *addr;942 dma_addr_t dma_addr;943};944 945/**946 * struct dma_memory_desc - memory descriptor structure to store947 * virtual address, dma address and size for any generic dma948 * memory allocations in the driver.949 *950 * @size: buffer size951 * @addr: virtual address952 * @dma_addr: dma address953 */954struct dma_memory_desc {955 u32 size;956 void *addr;957 dma_addr_t dma_addr;958};959 960 961/**962 * struct chain_element - memory descriptor structure to store963 * virtual and dma addresses for chain elements.964 *965 * @addr: virtual address966 * @dma_addr: dma address967 */968struct chain_element {969 void *addr;970 dma_addr_t dma_addr;971};972 973/**974 * struct scmd_priv - SCSI command private data975 *976 * @host_tag: Host tag specific to operational queue977 * @in_lld_scope: Command in LLD scope or not978 * @meta_sg_valid: DIX command with meta data SGL or not979 * @scmd: SCSI Command pointer980 * @req_q_idx: Operational request queue index981 * @chain_idx: Chain frame index982 * @meta_chain_idx: Chain frame index of meta data SGL983 * @mpi3mr_scsiio_req: MPI SCSI IO request984 */985struct scmd_priv {986 u16 host_tag;987 u8 in_lld_scope;988 u8 meta_sg_valid;989 struct scsi_cmnd *scmd;990 u16 req_q_idx;991 int chain_idx;992 int meta_chain_idx;993 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];994};995 996/**997 * struct mpi3mr_ioc - Adapter anchor structure stored in shost998 * private data999 *1000 * @list: List pointer1001 * @pdev: PCI device pointer1002 * @shost: Scsi_Host pointer1003 * @id: Controller ID1004 * @cpu_count: Number of online CPUs1005 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll1006 * @name: Controller ASCII name1007 * @driver_name: Driver ASCII name1008 * @sysif_regs: System interface registers virtual address1009 * @sysif_regs_phys: System interface registers physical address1010 * @bars: PCI BARS1011 * @dma_mask: DMA mask1012 * @msix_count: Number of MSIX vectors used1013 * @intr_enabled: Is interrupts enabled1014 * @num_admin_req: Number of admin requests1015 * @admin_req_q_sz: Admin request queue size1016 * @admin_req_pi: Admin request queue producer index1017 * @admin_req_ci: Admin request queue consumer index1018 * @admin_req_base: Admin request queue base virtual address1019 * @admin_req_dma: Admin request queue base dma address1020 * @admin_req_lock: Admin queue access lock1021 * @num_admin_replies: Number of admin replies1022 * @admin_reply_q_sz: Admin reply queue size1023 * @admin_reply_ci: Admin reply queue consumer index1024 * @admin_reply_ephase:Admin reply queue expected phase1025 * @admin_reply_base: Admin reply queue base virtual address1026 * @admin_reply_dma: Admin reply queue base dma address1027 * @admin_reply_q_in_use: Queue is handled by poll/ISR1028 * @ready_timeout: Controller ready timeout1029 * @intr_info: Interrupt cookie pointer1030 * @intr_info_count: Number of interrupt cookies1031 * @is_intr_info_set: Flag to indicate intr info is setup1032 * @num_queues: Number of operational queues1033 * @num_op_req_q: Number of operational request queues1034 * @req_qinfo: Operational request queue info pointer1035 * @num_op_reply_q: Number of operational reply queues1036 * @op_reply_qinfo: Operational reply queue info pointer1037 * @init_cmds: Command tracker for initialization commands1038 * @cfg_cmds: Command tracker for configuration requests1039 * @facts: Cached IOC facts data1040 * @op_reply_desc_sz: Operational reply descriptor size1041 * @num_reply_bufs: Number of reply buffers allocated1042 * @reply_buf_pool: Reply buffer pool1043 * @reply_buf: Reply buffer base virtual address1044 * @reply_buf_dma: Reply buffer DMA address1045 * @reply_buf_dma_max_address: Reply DMA address max limit1046 * @reply_free_qsz: Reply free queue size1047 * @reply_free_q_pool: Reply free queue pool1048 * @reply_free_q: Reply free queue base virtual address1049 * @reply_free_q_dma: Reply free queue base DMA address1050 * @reply_free_queue_lock: Reply free queue lock1051 * @reply_free_queue_host_index: Reply free queue host index1052 * @num_sense_bufs: Number of sense buffers1053 * @sense_buf_pool: Sense buffer pool1054 * @sense_buf: Sense buffer base virtual address1055 * @sense_buf_dma: Sense buffer base DMA address1056 * @sense_buf_q_sz: Sense buffer queue size1057 * @sense_buf_q_pool: Sense buffer queue pool1058 * @sense_buf_q: Sense buffer queue virtual address1059 * @sense_buf_q_dma: Sense buffer queue DMA address1060 * @sbq_lock: Sense buffer queue lock1061 * @sbq_host_index: Sense buffer queuehost index1062 * @event_masks: Event mask bitmap1063 * @fwevt_worker_thread: Firmware event worker thread1064 * @fwevt_lock: Firmware event lock1065 * @fwevt_list: Firmware event list1066 * @watchdog_work_q_name: Fault watchdog worker thread name1067 * @watchdog_work_q: Fault watchdog worker thread1068 * @watchdog_work: Fault watchdog work1069 * @watchdog_lock: Fault watchdog lock1070 * @is_driver_loading: Is driver still loading1071 * @scan_started: Async scan started1072 * @scan_failed: Asycn scan failed1073 * @stop_drv_processing: Stop all command processing1074 * @device_refresh_on: Don't process the events until devices are refreshed1075 * @max_host_ios: Maximum host I/O count1076 * @max_sgl_entries: Max SGL entries per I/O1077 * @chain_buf_count: Chain buffer count1078 * @chain_buf_pool: Chain buffer pool1079 * @chain_sgl_list: Chain SGL list1080 * @chain_bitmap: Chain buffer allocator bitmap1081 * @chain_buf_lock: Chain buffer list lock1082 * @bsg_cmds: Command tracker for BSG command1083 * @host_tm_cmds: Command tracker for task management commands1084 * @dev_rmhs_cmds: Command tracker for device removal commands1085 * @evtack_cmds: Command tracker for event ack commands1086 * @devrem_bitmap: Device removal bitmap1087 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap1088 * @removepend_bitmap: Remove pending bitmap1089 * @delayed_rmhs_list: Delayed device removal list1090 * @evtack_cmds_bitmap: Event Ack bitmap1091 * @delayed_evtack_cmds_list: Delayed event acknowledgment list1092 * @ts_update_counter: Timestamp update counter1093 * @ts_update_interval: Timestamp update interval1094 * @reset_in_progress: Reset in progress flag1095 * @unrecoverable: Controller unrecoverable flag1096 * @prev_reset_result: Result of previous reset1097 * @reset_mutex: Controller reset mutex1098 * @reset_waitq: Controller reset wait queue1099 * @prepare_for_reset: Prepare for reset event received1100 * @prepare_for_reset_timeout_counter: Prepare for reset timeout1101 * @prp_list_virt: NVMe encapsulated PRP list virtual base1102 * @prp_list_dma: NVMe encapsulated PRP list DMA1103 * @prp_sz: NVME encapsulated PRP list size1104 * @diagsave_timeout: Diagnostic information save timeout1105 * @logging_level: Controller debug logging level1106 * @flush_io_count: I/O count to flush after reset1107 * @current_event: Firmware event currently in process1108 * @driver_info: Driver, Kernel, OS information to firmware1109 * @change_count: Topology change count1110 * @pel_enabled: Persistent Event Log(PEL) enabled or not1111 * @pel_abort_requested: PEL abort is requested or not1112 * @pel_class: PEL Class identifier1113 * @pel_locale: PEL Locale identifier1114 * @pel_cmds: Command tracker for PEL wait command1115 * @pel_abort_cmd: Command tracker for PEL abort command1116 * @pel_newest_seqnum: Newest PEL sequenece number1117 * @pel_seqnum_virt: PEL sequence number virtual address1118 * @pel_seqnum_dma: PEL sequence number DMA address1119 * @pel_seqnum_sz: PEL sequenece number size1120 * @op_reply_q_offset: Operational reply queue offset with MSIx1121 * @default_qcount: Total Default queues1122 * @active_poll_qcount: Currently active poll queue count1123 * @requested_poll_qcount: User requested poll queue count1124 * @bsg_dev: BSG device structure1125 * @bsg_queue: Request queue for BSG device1126 * @stop_bsgs: Stop BSG request flag1127 * @logdata_buf: Circular buffer to store log data entries1128 * @logdata_buf_idx: Index of entry in buffer to store1129 * @logdata_entry_sz: log data entry size1130 * @pend_large_data_sz: Counter to track pending large data1131 * @io_throttle_data_length: I/O size to track in 512b blocks1132 * @io_throttle_high: I/O size to start throttle in 512b blocks1133 * @io_throttle_low: I/O size to stop throttle in 512b blocks1134 * @num_io_throttle_group: Maximum number of throttle groups1135 * @throttle_groups: Pointer to throttle group info structures1136 * @cfg_page: Default memory for configuration pages1137 * @cfg_page_dma: Configuration page DMA address1138 * @cfg_page_sz: Default configuration page memory size1139 * @sas_transport_enabled: SAS transport enabled or not1140 * @scsi_device_channel: Channel ID for SCSI devices1141 * @transport_cmds: Command tracker for SAS transport commands1142 * @sas_hba: SAS node for the controller1143 * @sas_expander_list: SAS node list of expanders1144 * @sas_node_lock: Lock to protect SAS node list1145 * @hba_port_table_list: List of HBA Ports1146 * @enclosure_list: List of Enclosure objects1147 * @diag_buffers: Host diagnostic buffers1148 * @driver_pg2: Driver page 2 pointer1149 * @reply_trigger_present: Reply trigger present flag1150 * @event_trigger_present: Event trigger present flag1151 * @scsisense_trigger_present: Scsi sense trigger present flag1152 * @ioctl_dma_pool: DMA pool for IOCTL data buffers1153 * @ioctl_sge: DMA buffer descriptors for IOCTL data1154 * @ioctl_chain_sge: DMA buffer descriptor for IOCTL chain1155 * @ioctl_resp_sge: DMA buffer descriptor for Mgmt cmd response1156 * @ioctl_sges_allocated: Flag for IOCTL SGEs allocated or not1157 * @trace_release_trigger_active: Trace trigger active flag1158 * @fw_release_trigger_active: Fw release trigger active flag1159 * @snapdump_trigger_active: Snapdump trigger active flag1160 * @pci_err_recovery: PCI error recovery in progress1161 * @block_on_pci_err: Block IO during PCI error recovery1162 */1163struct mpi3mr_ioc {1164 struct list_head list;1165 struct pci_dev *pdev;1166 struct Scsi_Host *shost;1167 u8 id;1168 int cpu_count;1169 bool enable_segqueue;1170 u32 irqpoll_sleep;1171 1172 char name[MPI3MR_NAME_LENGTH];1173 char driver_name[MPI3MR_NAME_LENGTH];1174 1175 volatile struct mpi3_sysif_registers __iomem *sysif_regs;1176 resource_size_t sysif_regs_phys;1177 int bars;1178 u64 dma_mask;1179 1180 u16 msix_count;1181 u8 intr_enabled;1182 1183 u16 num_admin_req;1184 u32 admin_req_q_sz;1185 u16 admin_req_pi;1186 u16 admin_req_ci;1187 void *admin_req_base;1188 dma_addr_t admin_req_dma;1189 spinlock_t admin_req_lock;1190 1191 u16 num_admin_replies;1192 u32 admin_reply_q_sz;1193 u16 admin_reply_ci;1194 u8 admin_reply_ephase;1195 void *admin_reply_base;1196 dma_addr_t admin_reply_dma;1197 atomic_t admin_reply_q_in_use;1198 1199 u32 ready_timeout;1200 1201 struct mpi3mr_intr_info *intr_info;1202 u16 intr_info_count;1203 bool is_intr_info_set;1204 1205 u16 num_queues;1206 u16 num_op_req_q;1207 struct op_req_qinfo *req_qinfo;1208 1209 u16 num_op_reply_q;1210 struct op_reply_qinfo *op_reply_qinfo;1211 1212 struct mpi3mr_drv_cmd init_cmds;1213 struct mpi3mr_drv_cmd cfg_cmds;1214 struct mpi3mr_ioc_facts facts;1215 u16 op_reply_desc_sz;1216 1217 u32 num_reply_bufs;1218 struct dma_pool *reply_buf_pool;1219 u8 *reply_buf;1220 dma_addr_t reply_buf_dma;1221 dma_addr_t reply_buf_dma_max_address;1222 1223 u16 reply_free_qsz;1224 u16 reply_sz;1225 struct dma_pool *reply_free_q_pool;1226 __le64 *reply_free_q;1227 dma_addr_t reply_free_q_dma;1228 spinlock_t reply_free_queue_lock;1229 u32 reply_free_queue_host_index;1230 1231 u32 num_sense_bufs;1232 struct dma_pool *sense_buf_pool;1233 u8 *sense_buf;1234 dma_addr_t sense_buf_dma;1235 1236 u16 sense_buf_q_sz;1237 struct dma_pool *sense_buf_q_pool;1238 __le64 *sense_buf_q;1239 dma_addr_t sense_buf_q_dma;1240 spinlock_t sbq_lock;1241 u32 sbq_host_index;1242 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];1243 1244 struct workqueue_struct *fwevt_worker_thread;1245 spinlock_t fwevt_lock;1246 struct list_head fwevt_list;1247 1248 char watchdog_work_q_name[50];1249 struct workqueue_struct *watchdog_work_q;1250 struct delayed_work watchdog_work;1251 spinlock_t watchdog_lock;1252 1253 u8 is_driver_loading;1254 u8 scan_started;1255 u16 scan_failed;1256 u8 stop_drv_processing;1257 u8 device_refresh_on;1258 1259 u16 max_host_ios;1260 spinlock_t tgtdev_lock;1261 struct list_head tgtdev_list;1262 u16 max_sgl_entries;1263 1264 u32 chain_buf_count;1265 struct dma_pool *chain_buf_pool;1266 struct chain_element *chain_sgl_list;1267 unsigned long *chain_bitmap;1268 spinlock_t chain_buf_lock;1269 1270 struct mpi3mr_drv_cmd bsg_cmds;1271 struct mpi3mr_drv_cmd host_tm_cmds;1272 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];1273 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];1274 unsigned long *devrem_bitmap;1275 u16 dev_handle_bitmap_bits;1276 unsigned long *removepend_bitmap;1277 struct list_head delayed_rmhs_list;1278 unsigned long *evtack_cmds_bitmap;1279 struct list_head delayed_evtack_cmds_list;1280 1281 u16 ts_update_counter;1282 u16 ts_update_interval;1283 u8 reset_in_progress;1284 u8 unrecoverable;1285 int prev_reset_result;1286 struct mutex reset_mutex;1287 wait_queue_head_t reset_waitq;1288 1289 u8 prepare_for_reset;1290 u16 prepare_for_reset_timeout_counter;1291 1292 void *prp_list_virt;1293 dma_addr_t prp_list_dma;1294 u32 prp_sz;1295 1296 u16 diagsave_timeout;1297 int logging_level;1298 u16 flush_io_count;1299 1300 struct mpi3mr_fwevt *current_event;1301 struct mpi3_driver_info_layout driver_info;1302 u16 change_count;1303 1304 u8 pel_enabled;1305 u8 pel_abort_requested;1306 u8 pel_class;1307 u16 pel_locale;1308 struct mpi3mr_drv_cmd pel_cmds;1309 struct mpi3mr_drv_cmd pel_abort_cmd;1310 1311 u32 pel_newest_seqnum;1312 void *pel_seqnum_virt;1313 dma_addr_t pel_seqnum_dma;1314 u32 pel_seqnum_sz;1315 1316 u16 op_reply_q_offset;1317 u16 default_qcount;1318 u16 active_poll_qcount;1319 u16 requested_poll_qcount;1320 1321 struct device bsg_dev;1322 struct request_queue *bsg_queue;1323 u8 stop_bsgs;1324 u8 *logdata_buf;1325 u16 logdata_buf_idx;1326 u16 logdata_entry_sz;1327 1328 atomic_t pend_large_data_sz;1329 u32 io_throttle_data_length;1330 u32 io_throttle_high;1331 u32 io_throttle_low;1332 u16 num_io_throttle_group;1333 struct mpi3mr_throttle_group_info *throttle_groups;1334 1335 void *cfg_page;1336 dma_addr_t cfg_page_dma;1337 u16 cfg_page_sz;1338 1339 u8 sas_transport_enabled;1340 u8 scsi_device_channel;1341 struct mpi3mr_drv_cmd transport_cmds;1342 struct mpi3mr_sas_node sas_hba;1343 struct list_head sas_expander_list;1344 spinlock_t sas_node_lock;1345 struct list_head hba_port_table_list;1346 struct list_head enclosure_list;1347 1348 struct dma_pool *ioctl_dma_pool;1349 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE];1350 struct dma_memory_desc ioctl_chain_sge;1351 struct dma_memory_desc ioctl_resp_sge;1352 bool ioctl_sges_allocated;1353 bool reply_trigger_present;1354 bool event_trigger_present;1355 bool scsisense_trigger_present;1356 struct diag_buffer_desc diag_buffers[MPI3MR_MAX_NUM_HDB];1357 struct mpi3_driver_page2 *driver_pg2;1358 spinlock_t trigger_lock;1359 bool snapdump_trigger_active;1360 bool trace_release_trigger_active;1361 bool fw_release_trigger_active;1362 bool pci_err_recovery;1363 bool block_on_pci_err;1364};1365 1366/**1367 * struct mpi3mr_fwevt - Firmware event structure.1368 *1369 * @list: list head1370 * @work: Work structure1371 * @mrioc: Adapter instance reference1372 * @event_id: MPI3 firmware event ID1373 * @send_ack: Event acknowledgment required or not1374 * @process_evt: Bottomhalf processing required or not1375 * @evt_ctx: Event context to send in Ack1376 * @event_data_size: size of the event data in bytes1377 * @pending_at_sml: waiting for device add/remove API to complete1378 * @discard: discard this event1379 * @ref_count: kref count1380 * @event_data: Actual MPI3 event data1381 */1382struct mpi3mr_fwevt {1383 struct list_head list;1384 struct work_struct work;1385 struct mpi3mr_ioc *mrioc;1386 u16 event_id;1387 bool send_ack;1388 bool process_evt;1389 u32 evt_ctx;1390 u16 event_data_size;1391 bool pending_at_sml;1392 bool discard;1393 struct kref ref_count;1394 char event_data[] __aligned(4);1395};1396 1397 1398/**1399 * struct delayed_dev_rmhs_node - Delayed device removal node1400 *1401 * @list: list head1402 * @handle: Device handle1403 * @iou_rc: IO Unit Control Reason Code1404 */1405struct delayed_dev_rmhs_node {1406 struct list_head list;1407 u16 handle;1408 u8 iou_rc;1409};1410 1411/**1412 * struct delayed_evt_ack_node - Delayed event ack node1413 * @list: list head1414 * @event: MPI3 event ID1415 * @event_ctx: event context1416 */1417struct delayed_evt_ack_node {1418 struct list_head list;1419 u8 event;1420 u32 event_ctx;1421};1422 1423int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);1424void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);1425int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc);1426int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume);1427void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc);1428int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);1429int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,1430u16 admin_req_sz, u8 ignore_reset);1431int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,1432 struct op_req_qinfo *opreqq, u8 *req);1433void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,1434 dma_addr_t dma_addr);1435void mpi3mr_build_zero_len_sge(void *paddr);1436void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,1437 dma_addr_t phys_addr);1438void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,1439 dma_addr_t phys_addr);1440void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,1441 u64 sense_buf_dma);1442 1443void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);1444void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc);1445void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,1446 struct mpi3_event_notification_reply *event_reply);1447void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,1448 struct mpi3_default_reply_descriptor *reply_desc,1449 u64 *reply_dma, u16 qidx);1450void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);1451void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);1452 1453int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,1454 u16 reset_reason, u8 snapdump);1455void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);1456void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);1457 1458enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);1459int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,1460 u32 event_ctx);1461 1462void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);1463void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);1464void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);1465void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);1466void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);1467void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);1468void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);1469void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);1470int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,1471 struct op_reply_qinfo *op_reply_q);1472int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);1473void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc);1474void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc);1475int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,1476 u16 handle, uint lun, u16 htag, ulong timeout,1477 struct mpi3mr_drv_cmd *drv_cmd,1478 u8 *resp_code, struct scsi_cmnd *scmd);1479struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle(1480 struct mpi3mr_ioc *mrioc, u16 handle);1481void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,1482 struct mpi3mr_drv_cmd *drv_cmd);1483int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,1484 struct mpi3mr_drv_cmd *drv_cmd);1485void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data,1486 u16 event_data_size);1487struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle(1488 struct mpi3mr_ioc *mrioc, u16 handle);1489extern const struct attribute_group *mpi3mr_host_groups[];1490extern const struct attribute_group *mpi3mr_dev_groups[];1491 1492extern struct sas_function_template mpi3mr_transport_functions;1493extern struct scsi_transport_template *mpi3mr_transport_template;1494 1495int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,1496 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec);1497int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,1498 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,1499 u32 form_spec);1500int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,1501 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,1502 u32 form_spec);1503int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,1504 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,1505 u32 form_spec);1506int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,1507 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,1508 u32 form_spec);1509int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,1510 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,1511 u32 form_spec);1512int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,1513 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz);1514int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,1515 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);1516int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,1517 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);1518int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,1519 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz);1520int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc,1521 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_type);1522 1523u8 mpi3mr_is_expander_device(u16 device_info);1524int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle);1525void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address,1526 struct mpi3mr_hba_port *hba_port);1527struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc1528 *mrioc, u16 handle);1529struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc,1530 u8 port_id);1531void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc);1532void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc);1533void mpi3mr_update_links(struct mpi3mr_ioc *mrioc,1534 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate,1535 struct mpi3mr_hba_port *hba_port);1536void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc,1537 struct mpi3mr_tgt_dev *tgtdev);1538int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc,1539 struct mpi3mr_tgt_dev *tgtdev);1540void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc,1541 struct mpi3mr_tgt_dev *tgtdev);1542struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy(1543 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy);1544void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc,1545 bool device_add);1546void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc);1547void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc);1548void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc);1549void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc);1550void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc);1551void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc);1552int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc);1553void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc,1554 struct mpi3mr_sas_node *sas_expander);1555void mpi3mr_alloc_diag_bufs(struct mpi3mr_ioc *mrioc);1556int mpi3mr_post_diag_bufs(struct mpi3mr_ioc *mrioc);1557int mpi3mr_issue_diag_buf_release(struct mpi3mr_ioc *mrioc,1558 struct diag_buffer_desc *diag_buffer);1559void mpi3mr_release_diag_bufs(struct mpi3mr_ioc *mrioc, u8 skip_rel_action);1560void mpi3mr_set_trigger_data_in_hdb(struct diag_buffer_desc *hdb,1561 u8 type, union mpi3mr_trigger_data *trigger_data, bool force);1562int mpi3mr_refresh_trigger(struct mpi3mr_ioc *mrioc, u8 page_type);1563struct diag_buffer_desc *mpi3mr_diag_buffer_for_type(struct mpi3mr_ioc *mrioc,1564 u8 buf_type);1565int mpi3mr_issue_diag_buf_post(struct mpi3mr_ioc *mrioc,1566 struct diag_buffer_desc *diag_buffer);1567void mpi3mr_set_trigger_data_in_all_hdb(struct mpi3mr_ioc *mrioc,1568 u8 type, union mpi3mr_trigger_data *trigger_data, bool force);1569void mpi3mr_reply_trigger(struct mpi3mr_ioc *mrioc, u16 iocstatus,1570 u32 iocloginfo);1571void mpi3mr_hdb_trigger_data_event(struct mpi3mr_ioc *mrioc,1572 struct trigger_event_data *event_data);1573void mpi3mr_scsisense_trigger(struct mpi3mr_ioc *mrioc, u8 senseky, u8 asc,1574 u8 ascq);1575void mpi3mr_event_trigger(struct mpi3mr_ioc *mrioc, u8 event);1576void mpi3mr_global_trigger(struct mpi3mr_ioc *mrioc, u64 trigger_data);1577void mpi3mr_hdbstatuschg_evt_th(struct mpi3mr_ioc *mrioc,1578 struct mpi3_event_notification_reply *event_reply);1579#endif /*MPI3MR_H_INCLUDED*/1580