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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.4 *5 *6 * Name: mpi2_ioc.h7 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages8 * Creation Date: October 11, 20069 *10 * mpi2_ioc.h Version: 02.00.3711 *12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi2513 * prefix are for use only on MPI v2.5 products, and must not be used14 * with MPI v2.0 products. Unless otherwise noted, names beginning with15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.16 *17 * Version History18 * ---------------19 *20 * Date Version Description21 * -------- -------- ------------------------------------------------------22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.23 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to24 * MaxTargets.25 * Added TotalImageSize field to FWDownload Request.26 * Added reserved words to FWUpload Request.27 * 06-26-07 02.00.02 Added IR Configuration Change List Event.28 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit29 * request and replaced it with30 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.31 * Replaced the MinReplyQueueDepth field of the IOCFacts32 * reply with MaxReplyDescriptorPostQueueDepth.33 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum34 * depth for the Reply Descriptor Post Queue.35 * Added SASAddress field to Initiator Device Table36 * Overflow Event data.37 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING38 * for SAS Initiator Device Status Change Event data.39 * Modified Reason Code defines for SAS Topology Change40 * List Event data, including adding a bit for PHY Vacant41 * status, and adding a mask for the Reason Code.42 * Added define for43 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.44 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.45 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of46 * the IOCFacts Reply.47 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.48 * Moved MPI2_VERSION_UNION to mpi2.h.49 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks50 * instead of enables, and added SASBroadcastPrimitiveMasks51 * field.52 * Added Log Entry Added Event and related structure.53 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.54 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.55 * Added MaxVolumes and MaxPersistentEntries fields to56 * IOCFacts reply.57 * Added ProtocalFlags and IOCCapabilities fields to58 * MPI2_FW_IMAGE_HEADER.59 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.60 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to61 * a U16 (from a U32).62 * Removed extra 's' from EventMasks name.63 * 06-27-08 02.00.08 Fixed an offset in a comment.64 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.65 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and66 * renamed MinReplyFrameSize to ReplyFrameSize.67 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.68 * Added two new RAIDOperation values for Integrated RAID69 * Operations Status Event data.70 * Added four new IR Configuration Change List Event data71 * ReasonCode values.72 * Added two new ReasonCode defines for SAS Device Status73 * Change Event data.74 * Added three new DiscoveryStatus bits for the SAS75 * Discovery event data.76 * Added Multiplexing Status Change bit to the PhyStatus77 * field of the SAS Topology Change List event data.78 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.79 * BootFlags are now product-specific.80 * Added defines for the indivdual signature bytes81 * for MPI2_INIT_IMAGE_FOOTER.82 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.83 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR84 * define.85 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE86 * define.87 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.88 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.89 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.90 * Added two new reason codes for SAS Device Status Change91 * Event.92 * Added new event: SAS PHY Counter.93 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.94 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.95 * Added new product id family for 2208.96 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.97 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.98 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.99 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.100 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.101 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.102 * Added Host Based Discovery Phy Event data.103 * Added defines for ProductID Product field104 * (MPI2_FW_HEADER_PID_).105 * Modified values for SAS ProductID Family106 * (MPI2_FW_HEADER_PID_FAMILY_).107 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.108 * Added PowerManagementControl Request structures and109 * defines.110 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.111 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.112 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.113 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added114 * SASNotifyPrimitiveMasks field to115 * MPI2_EVENT_NOTIFICATION_REQUEST.116 * Added Temperature Threshold Event.117 * Added Host Message Event.118 * Added Send Host Message request and reply.119 * 05-25-11 02.00.18 For Extended Image Header, added120 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and121 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.122 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.123 * 08-24-11 02.00.19 Added PhysicalPort field to124 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.125 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.126 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5.127 * 03-29-12 02.00.21 Added a product specific range to event values.128 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.129 * Added ElapsedSeconds field to130 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.131 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE132 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.133 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.134 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.135 * Added Encrypted Hash Extended Image.136 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS.137 * 11-18-14 02.00.25 Updated copyright information.138 * 03-16-15 02.00.26 Updated for MPI v2.6.139 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and140 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.141 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and142 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS.143 * Added MPI26_CTRL_OP_SHUTDOWN.144 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines.145 * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event.146 * Added ConigurationFlags field to IOCInit message to147 * support NVMe SGL format control.148 * Added PCIe SRIOV support.149 * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support.150 * Added PCIe 4 16.0 GT/sec speec support.151 * Removed AHCI support.152 * Removed SOP support.153 * 07-01-16 02.00.29 Added Archclass for 4008 product.154 * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED155 * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload156 * Request Message.157 * Added new defines for the ImageType field of FWUpload158 * Request Message.159 * Added new values for the RegionType field in the Layout160 * Data sections of the FLASH Layout Extended Image Data.161 * Added new defines for the ReasonCode field of162 * Active Cable Exception Event.163 * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and164 * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE.165 * 11-23-16 02.00.31 Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and166 * MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR.167 * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP.168 * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related169 * defines for the ReasonCode field.170 * 06-13-17 02.00.33 Added MPI2_FW_DOWNLOAD_ITYPE_CPLD.171 * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED172 * to the ReasonCode field in PCIe Device Status Change173 * Event Data.174 * 07-22-18 02.00.35 Added FW_DOWNLOAD_ITYPE_CPLD and _PSOC.175 * Moved FW image definitions ionto new mpi2_image,h176 * 08-14-18 02.00.36 Fixed definition of MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)177 * 09-07-18 02.00.37 Added MPI26_EVENT_PCIE_TOPO_PI_16_LANES178 * 10-02-19 02.00.38 Added MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE179 * Added MPI26_IOCFACTS_CAPABILITY_COREDUMP_ENABLED180 * Added MPI2_FW_DOWNLOAD_ITYPE_COREDUMP181 * Added MPI2_FW_UPLOAD_ITYPE_COREDUMP182 * --------------------------------------------------------------------------183 */184 185#ifndef MPI2_IOC_H186#define MPI2_IOC_H187 188/*****************************************************************************189*190* IOC Messages191*192*****************************************************************************/193 194/****************************************************************************195* IOCInit message196****************************************************************************/197 198/*IOCInit Request message */199typedef struct _MPI2_IOC_INIT_REQUEST {200 U8 WhoInit; /*0x00 */201 U8 Reserved1; /*0x01 */202 U8 ChainOffset; /*0x02 */203 U8 Function; /*0x03 */204 U16 Reserved2; /*0x04 */205 U8 Reserved3; /*0x06 */206 U8 MsgFlags; /*0x07 */207 U8 VP_ID; /*0x08 */208 U8 VF_ID; /*0x09 */209 U16 Reserved4; /*0x0A */210 U16 MsgVersion; /*0x0C */211 U16 HeaderVersion; /*0x0E */212 U32 Reserved5; /*0x10 */213 U16 ConfigurationFlags; /* 0x14 */214 U8 HostPageSize; /*0x16 */215 U8 HostMSIxVectors; /*0x17 */216 U16 Reserved8; /*0x18 */217 U16 SystemRequestFrameSize; /*0x1A */218 U16 ReplyDescriptorPostQueueDepth; /*0x1C */219 U16 ReplyFreeQueueDepth; /*0x1E */220 U32 SenseBufferAddressHigh; /*0x20 */221 U32 SystemReplyAddressHigh; /*0x24 */222 U64 SystemRequestFrameBaseAddress; /*0x28 */223 U64 ReplyDescriptorPostQueueAddress; /*0x30 */224 U64 ReplyFreeQueueAddress; /*0x38 */225 U64 TimeStamp; /*0x40 */226} MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,227 Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;228 229/*WhoInit values */230#define MPI2_WHOINIT_NOT_INITIALIZED (0x00)231#define MPI2_WHOINIT_SYSTEM_BIOS (0x01)232#define MPI2_WHOINIT_ROM_BIOS (0x02)233#define MPI2_WHOINIT_PCI_PEER (0x03)234#define MPI2_WHOINIT_HOST_DRIVER (0x04)235#define MPI2_WHOINIT_MANUFACTURER (0x05)236 237/* MsgFlags */238#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)239 240 241/*MsgVersion */242#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)243#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)244#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)245#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)246 247/*HeaderVersion */248#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)249#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)250#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)251#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)252 253/*ConfigurationFlags */254#define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001)255#define MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE (0x0002)256 257/*minimum depth for a Reply Descriptor Post Queue */258#define MPI2_RDPQ_DEPTH_MIN (16)259 260/* Reply Descriptor Post Queue Array Entry */261typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {262 U64 RDPQBaseAddress; /* 0x00 */263 U32 Reserved1; /* 0x08 */264 U32 Reserved2; /* 0x0C */265} MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,266*PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,267Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry;268 269 270/*IOCInit Reply message */271typedef struct _MPI2_IOC_INIT_REPLY {272 U8 WhoInit; /*0x00 */273 U8 Reserved1; /*0x01 */274 U8 MsgLength; /*0x02 */275 U8 Function; /*0x03 */276 U16 Reserved2; /*0x04 */277 U8 Reserved3; /*0x06 */278 U8 MsgFlags; /*0x07 */279 U8 VP_ID; /*0x08 */280 U8 VF_ID; /*0x09 */281 U16 Reserved4; /*0x0A */282 U16 Reserved5; /*0x0C */283 U16 IOCStatus; /*0x0E */284 U32 IOCLogInfo; /*0x10 */285} MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,286 Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;287 288/****************************************************************************289* IOCFacts message290****************************************************************************/291 292/*IOCFacts Request message */293typedef struct _MPI2_IOC_FACTS_REQUEST {294 U16 Reserved1; /*0x00 */295 U8 ChainOffset; /*0x02 */296 U8 Function; /*0x03 */297 U16 Reserved2; /*0x04 */298 U8 Reserved3; /*0x06 */299 U8 MsgFlags; /*0x07 */300 U8 VP_ID; /*0x08 */301 U8 VF_ID; /*0x09 */302 U16 Reserved4; /*0x0A */303} MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,304 Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;305 306/*IOCFacts Reply message */307typedef struct _MPI2_IOC_FACTS_REPLY {308 U16 MsgVersion; /*0x00 */309 U8 MsgLength; /*0x02 */310 U8 Function; /*0x03 */311 U16 HeaderVersion; /*0x04 */312 U8 IOCNumber; /*0x06 */313 U8 MsgFlags; /*0x07 */314 U8 VP_ID; /*0x08 */315 U8 VF_ID; /*0x09 */316 U16 Reserved1; /*0x0A */317 U16 IOCExceptions; /*0x0C */318 U16 IOCStatus; /*0x0E */319 U32 IOCLogInfo; /*0x10 */320 U8 MaxChainDepth; /*0x14 */321 U8 WhoInit; /*0x15 */322 U8 NumberOfPorts; /*0x16 */323 U8 MaxMSIxVectors; /*0x17 */324 U16 RequestCredit; /*0x18 */325 U16 ProductID; /*0x1A */326 U32 IOCCapabilities; /*0x1C */327 MPI2_VERSION_UNION FWVersion; /*0x20 */328 U16 IOCRequestFrameSize; /*0x24 */329 U16 IOCMaxChainSegmentSize; /*0x26 */330 U16 MaxInitiators; /*0x28 */331 U16 MaxTargets; /*0x2A */332 U16 MaxSasExpanders; /*0x2C */333 U16 MaxEnclosures; /*0x2E */334 U16 ProtocolFlags; /*0x30 */335 U16 HighPriorityCredit; /*0x32 */336 U16 MaxReplyDescriptorPostQueueDepth; /*0x34 */337 U8 ReplyFrameSize; /*0x36 */338 U8 MaxVolumes; /*0x37 */339 U16 MaxDevHandle; /*0x38 */340 U16 MaxPersistentEntries; /*0x3A */341 U16 MinDevHandle; /*0x3C */342 U8 CurrentHostPageSize; /* 0x3E */343 U8 Reserved4; /* 0x3F */344 U8 SGEModifierMask; /*0x40 */345 U8 SGEModifierValue; /*0x41 */346 U8 SGEModifierShift; /*0x42 */347 U8 Reserved5; /*0x43 */348} MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,349 Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;350 351/*MsgVersion */352#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)353#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)354#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)355#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)356 357/*HeaderVersion */358#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)359#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)360#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)361#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)362 363/*IOCExceptions */364#define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400)365#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200)366#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)367 368#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)369#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)370#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)371#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)372#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)373 374#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)375#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)376#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)377#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)378#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)379 380/*defines for WhoInit field are after the IOCInit Request */381 382/*ProductID field uses MPI2_FW_HEADER_PID_ */383 384/*IOCCapabilities */385#define MPI26_IOCFACTS_CAPABILITY_COREDUMP_ENABLED (0x00200000)386#define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000)387#define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000)388#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000)389#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)390#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)391#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)392#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)393#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)394#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)395#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)396#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)397#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)398#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)399#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)400#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)401#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)402#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)403 404/*ProtocolFlags */405#define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008)406#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)407#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)408 409/****************************************************************************410* PortFacts message411****************************************************************************/412 413/*PortFacts Request message */414typedef struct _MPI2_PORT_FACTS_REQUEST {415 U16 Reserved1; /*0x00 */416 U8 ChainOffset; /*0x02 */417 U8 Function; /*0x03 */418 U16 Reserved2; /*0x04 */419 U8 PortNumber; /*0x06 */420 U8 MsgFlags; /*0x07 */421 U8 VP_ID; /*0x08 */422 U8 VF_ID; /*0x09 */423 U16 Reserved3; /*0x0A */424} MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,425 Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;426 427/*PortFacts Reply message */428typedef struct _MPI2_PORT_FACTS_REPLY {429 U16 Reserved1; /*0x00 */430 U8 MsgLength; /*0x02 */431 U8 Function; /*0x03 */432 U16 Reserved2; /*0x04 */433 U8 PortNumber; /*0x06 */434 U8 MsgFlags; /*0x07 */435 U8 VP_ID; /*0x08 */436 U8 VF_ID; /*0x09 */437 U16 Reserved3; /*0x0A */438 U16 Reserved4; /*0x0C */439 U16 IOCStatus; /*0x0E */440 U32 IOCLogInfo; /*0x10 */441 U8 Reserved5; /*0x14 */442 U8 PortType; /*0x15 */443 U16 Reserved6; /*0x16 */444 U16 MaxPostedCmdBuffers; /*0x18 */445 U16 Reserved7; /*0x1A */446} MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,447 Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;448 449/*PortType values */450#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)451#define MPI2_PORTFACTS_PORTTYPE_FC (0x10)452#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)453#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)454#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)455#define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40)456 457 458/****************************************************************************459* PortEnable message460****************************************************************************/461 462/*PortEnable Request message */463typedef struct _MPI2_PORT_ENABLE_REQUEST {464 U16 Reserved1; /*0x00 */465 U8 ChainOffset; /*0x02 */466 U8 Function; /*0x03 */467 U8 Reserved2; /*0x04 */468 U8 PortFlags; /*0x05 */469 U8 Reserved3; /*0x06 */470 U8 MsgFlags; /*0x07 */471 U8 VP_ID; /*0x08 */472 U8 VF_ID; /*0x09 */473 U16 Reserved4; /*0x0A */474} MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,475 Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;476 477/*PortEnable Reply message */478typedef struct _MPI2_PORT_ENABLE_REPLY {479 U16 Reserved1; /*0x00 */480 U8 MsgLength; /*0x02 */481 U8 Function; /*0x03 */482 U8 Reserved2; /*0x04 */483 U8 PortFlags; /*0x05 */484 U8 Reserved3; /*0x06 */485 U8 MsgFlags; /*0x07 */486 U8 VP_ID; /*0x08 */487 U8 VF_ID; /*0x09 */488 U16 Reserved4; /*0x0A */489 U16 Reserved5; /*0x0C */490 U16 IOCStatus; /*0x0E */491 U32 IOCLogInfo; /*0x10 */492} MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,493 Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;494 495/****************************************************************************496* EventNotification message497****************************************************************************/498 499/*EventNotification Request message */500#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)501 502typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {503 U16 Reserved1; /*0x00 */504 U8 ChainOffset; /*0x02 */505 U8 Function; /*0x03 */506 U16 Reserved2; /*0x04 */507 U8 Reserved3; /*0x06 */508 U8 MsgFlags; /*0x07 */509 U8 VP_ID; /*0x08 */510 U8 VF_ID; /*0x09 */511 U16 Reserved4; /*0x0A */512 U32 Reserved5; /*0x0C */513 U32 Reserved6; /*0x10 */514 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; /*0x14 */515 U16 SASBroadcastPrimitiveMasks; /*0x24 */516 U16 SASNotifyPrimitiveMasks; /*0x26 */517 U32 Reserved8; /*0x28 */518} MPI2_EVENT_NOTIFICATION_REQUEST,519 *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,520 Mpi2EventNotificationRequest_t,521 *pMpi2EventNotificationRequest_t;522 523/*EventNotification Reply message */524typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {525 U16 EventDataLength; /*0x00 */526 U8 MsgLength; /*0x02 */527 U8 Function; /*0x03 */528 U16 Reserved1; /*0x04 */529 U8 AckRequired; /*0x06 */530 U8 MsgFlags; /*0x07 */531 U8 VP_ID; /*0x08 */532 U8 VF_ID; /*0x09 */533 U16 Reserved2; /*0x0A */534 U16 Reserved3; /*0x0C */535 U16 IOCStatus; /*0x0E */536 U32 IOCLogInfo; /*0x10 */537 U16 Event; /*0x14 */538 U16 Reserved4; /*0x16 */539 U32 EventContext; /*0x18 */540 U32 EventData[]; /*0x1C */541} MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,542 Mpi2EventNotificationReply_t,543 *pMpi2EventNotificationReply_t;544 545/*AckRequired */546#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)547#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)548 549/*Event */550#define MPI2_EVENT_LOG_DATA (0x0001)551#define MPI2_EVENT_STATE_CHANGE (0x0002)552#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)553#define MPI2_EVENT_EVENT_CHANGE (0x000A)554#define MPI2_EVENT_TASK_SET_FULL (0x000E) /*obsolete */555#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)556#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)557#define MPI2_EVENT_SAS_DISCOVERY (0x0016)558#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)559#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)560#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)561#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)562#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)563#define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D)564#define MPI2_EVENT_IR_VOLUME (0x001E)565#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)566#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)567#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)568#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)569#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)570#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)571#define MPI2_EVENT_SAS_QUIESCE (0x0025)572#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)573#define MPI2_EVENT_TEMP_THRESHOLD (0x0027)574#define MPI2_EVENT_HOST_MESSAGE (0x0028)575#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)576#define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030)577#define MPI2_EVENT_PCIE_ENUMERATION (0x0031)578#define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032)579#define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033)580#define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034)581#define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x0035)582#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)583#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)584 585/*Log Entry Added Event data */586 587/*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */588#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)589 590typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {591 U64 TimeStamp; /*0x00 */592 U32 Reserved1; /*0x08 */593 U16 LogSequence; /*0x0C */594 U16 LogEntryQualifier; /*0x0E */595 U8 VP_ID; /*0x10 */596 U8 VF_ID; /*0x11 */597 U16 Reserved2; /*0x12 */598 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH]; /*0x14 */599} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,600 *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,601 Mpi2EventDataLogEntryAdded_t,602 *pMpi2EventDataLogEntryAdded_t;603 604/*GPIO Interrupt Event data */605 606typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {607 U8 GPIONum; /*0x00 */608 U8 Reserved1; /*0x01 */609 U16 Reserved2; /*0x02 */610} MPI2_EVENT_DATA_GPIO_INTERRUPT,611 *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,612 Mpi2EventDataGpioInterrupt_t,613 *pMpi2EventDataGpioInterrupt_t;614 615/*Temperature Threshold Event data */616 617typedef struct _MPI2_EVENT_DATA_TEMPERATURE {618 U16 Status; /*0x00 */619 U8 SensorNum; /*0x02 */620 U8 Reserved1; /*0x03 */621 U16 CurrentTemperature; /*0x04 */622 U16 Reserved2; /*0x06 */623 U32 Reserved3; /*0x08 */624 U32 Reserved4; /*0x0C */625} MPI2_EVENT_DATA_TEMPERATURE,626 *PTR_MPI2_EVENT_DATA_TEMPERATURE,627 Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;628 629/*Temperature Threshold Event data Status bits */630#define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)631#define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)632#define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)633#define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)634 635/*Host Message Event data */636 637typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {638 U8 SourceVF_ID; /*0x00 */639 U8 Reserved1; /*0x01 */640 U16 Reserved2; /*0x02 */641 U32 Reserved3; /*0x04 */642 U32 HostData[]; /*0x08 */643} MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,644 Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;645 646/*Power Performance Change Event data */647 648typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {649 U8 CurrentPowerMode; /*0x00 */650 U8 PreviousPowerMode; /*0x01 */651 U16 Reserved1; /*0x02 */652} MPI2_EVENT_DATA_POWER_PERF_CHANGE,653 *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,654 Mpi2EventDataPowerPerfChange_t,655 *pMpi2EventDataPowerPerfChange_t;656 657/*defines for CurrentPowerMode and PreviousPowerMode fields */658#define MPI2_EVENT_PM_INIT_MASK (0xC0)659#define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00)660#define MPI2_EVENT_PM_INIT_HOST (0x40)661#define MPI2_EVENT_PM_INIT_IO_UNIT (0x80)662#define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0)663 664#define MPI2_EVENT_PM_MODE_MASK (0x07)665#define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)666#define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)667#define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)668#define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)669#define MPI2_EVENT_PM_MODE_STANDBY (0x06)670 671/* Active Cable Exception Event data */672 673typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT {674 U32 ActiveCablePowerRequirement; /* 0x00 */675 U8 ReasonCode; /* 0x04 */676 U8 ReceptacleID; /* 0x05 */677 U16 Reserved1; /* 0x06 */678} MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,679 *PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,680 Mpi25EventDataActiveCableExcept_t,681 *pMpi25EventDataActiveCableExcept_t,682 MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,683 *PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,684 Mpi26EventDataActiveCableExcept_t,685 *pMpi26EventDataActiveCableExcept_t;686 687/*MPI2.5 defines for the ReasonCode field */688#define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)689#define MPI25_EVENT_ACTIVE_CABLE_PRESENT (0x01)690#define MPI25_EVENT_ACTIVE_CABLE_DEGRADED (0x02)691 692/* defines for ReasonCode field */693#define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)694#define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01)695#define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02)696 697/*Hard Reset Received Event data */698 699typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {700 U8 Reserved1; /*0x00 */701 U8 Port; /*0x01 */702 U16 Reserved2; /*0x02 */703} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,704 *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,705 Mpi2EventDataHardResetReceived_t,706 *pMpi2EventDataHardResetReceived_t;707 708/*Task Set Full Event data */709/* this event is obsolete */710 711typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {712 U16 DevHandle; /*0x00 */713 U16 CurrentDepth; /*0x02 */714} MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,715 Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;716 717/*SAS Device Status Change Event data */718 719typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {720 U16 TaskTag; /*0x00 */721 U8 ReasonCode; /*0x02 */722 U8 PhysicalPort; /*0x03 */723 U8 ASC; /*0x04 */724 U8 ASCQ; /*0x05 */725 U16 DevHandle; /*0x06 */726 U32 Reserved2; /*0x08 */727 U64 SASAddress; /*0x0C */728 U8 LUN[8]; /*0x14 */729} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,730 *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,731 Mpi2EventDataSasDeviceStatusChange_t,732 *pMpi2EventDataSasDeviceStatusChange_t;733 734/*SAS Device Status Change Event data ReasonCode values */735#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)736#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)737#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)738#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)739#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)740#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)741#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)742#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)743#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)744#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)745#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)746#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)747#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)748 749/*Integrated RAID Operation Status Event data */750 751typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {752 U16 VolDevHandle; /*0x00 */753 U16 Reserved1; /*0x02 */754 U8 RAIDOperation; /*0x04 */755 U8 PercentComplete; /*0x05 */756 U16 Reserved2; /*0x06 */757 U32 ElapsedSeconds; /*0x08 */758} MPI2_EVENT_DATA_IR_OPERATION_STATUS,759 *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,760 Mpi2EventDataIrOperationStatus_t,761 *pMpi2EventDataIrOperationStatus_t;762 763/*Integrated RAID Operation Status Event data RAIDOperation values */764#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)765#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)766#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)767#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)768#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)769 770/*Integrated RAID Volume Event data */771 772typedef struct _MPI2_EVENT_DATA_IR_VOLUME {773 U16 VolDevHandle; /*0x00 */774 U8 ReasonCode; /*0x02 */775 U8 Reserved1; /*0x03 */776 U32 NewValue; /*0x04 */777 U32 PreviousValue; /*0x08 */778} MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,779 Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;780 781/*Integrated RAID Volume Event data ReasonCode values */782#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)783#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)784#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)785 786/*Integrated RAID Physical Disk Event data */787 788typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {789 U16 Reserved1; /*0x00 */790 U8 ReasonCode; /*0x02 */791 U8 PhysDiskNum; /*0x03 */792 U16 PhysDiskDevHandle; /*0x04 */793 U16 Reserved2; /*0x06 */794 U16 Slot; /*0x08 */795 U16 EnclosureHandle; /*0x0A */796 U32 NewValue; /*0x0C */797 U32 PreviousValue; /*0x10 */798} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,799 *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,800 Mpi2EventDataIrPhysicalDisk_t,801 *pMpi2EventDataIrPhysicalDisk_t;802 803/*Integrated RAID Physical Disk Event data ReasonCode values */804#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)805#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)806#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)807 808/*Integrated RAID Configuration Change List Event data */809 810/*811 *Host code (drivers, BIOS, utilities, etc.) should check NumElements at812 *runtime before using ConfigElement[].813 */814 815typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {816 U16 ElementFlags; /*0x00 */817 U16 VolDevHandle; /*0x02 */818 U8 ReasonCode; /*0x04 */819 U8 PhysDiskNum; /*0x05 */820 U16 PhysDiskDevHandle; /*0x06 */821} MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,822 Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;823 824/*IR Configuration Change List Event data ElementFlags values */825#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)826#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)827#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)828#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)829 830/*IR Configuration Change List Event data ReasonCode values */831#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)832#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)833#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)834#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)835#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)836#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)837#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)838#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)839#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)840 841typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {842 U8 NumElements; /*0x00 */843 U8 Reserved1; /*0x01 */844 U8 Reserved2; /*0x02 */845 U8 ConfigNum; /*0x03 */846 U32 Flags; /*0x04 */847 MPI2_EVENT_IR_CONFIG_ELEMENT848 ConfigElement[];/*0x08 */849} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,850 *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,851 Mpi2EventDataIrConfigChangeList_t,852 *pMpi2EventDataIrConfigChangeList_t;853 854/*IR Configuration Change List Event data Flags values */855#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)856 857/*SAS Discovery Event data */858 859typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {860 U8 Flags; /*0x00 */861 U8 ReasonCode; /*0x01 */862 U8 PhysicalPort; /*0x02 */863 U8 Reserved1; /*0x03 */864 U32 DiscoveryStatus; /*0x04 */865} MPI2_EVENT_DATA_SAS_DISCOVERY,866 *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,867 Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;868 869/*SAS Discovery Event data Flags values */870#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)871#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)872 873/*SAS Discovery Event data ReasonCode values */874#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)875#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)876 877/*SAS Discovery Event data DiscoveryStatus values */878#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)879#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)880#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)881#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)882#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)883#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)884#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)885#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)886#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)887#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)888#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)889#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)890#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)891#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)892#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)893#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)894#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)895#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)896#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)897#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)898 899/*SAS Broadcast Primitive Event data */900 901typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {902 U8 PhyNum; /*0x00 */903 U8 Port; /*0x01 */904 U8 PortWidth; /*0x02 */905 U8 Primitive; /*0x03 */906} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,907 *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,908 Mpi2EventDataSasBroadcastPrimitive_t,909 *pMpi2EventDataSasBroadcastPrimitive_t;910 911/*defines for the Primitive field */912#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)913#define MPI2_EVENT_PRIMITIVE_SES (0x02)914#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)915#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)916#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)917#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)918#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)919#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)920 921/*SAS Notify Primitive Event data */922 923typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {924 U8 PhyNum; /*0x00 */925 U8 Port; /*0x01 */926 U8 Reserved1; /*0x02 */927 U8 Primitive; /*0x03 */928} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,929 *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,930 Mpi2EventDataSasNotifyPrimitive_t,931 *pMpi2EventDataSasNotifyPrimitive_t;932 933/*defines for the Primitive field */934#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)935#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)936#define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)937#define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)938 939/*SAS Initiator Device Status Change Event data */940 941typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {942 U8 ReasonCode; /*0x00 */943 U8 PhysicalPort; /*0x01 */944 U16 DevHandle; /*0x02 */945 U64 SASAddress; /*0x04 */946} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,947 *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,948 Mpi2EventDataSasInitDevStatusChange_t,949 *pMpi2EventDataSasInitDevStatusChange_t;950 951/*SAS Initiator Device Status Change event ReasonCode values */952#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)953#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)954 955/*SAS Initiator Device Table Overflow Event data */956 957typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {958 U16 MaxInit; /*0x00 */959 U16 CurrentInit; /*0x02 */960 U64 SASAddress; /*0x04 */961} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,962 *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,963 Mpi2EventDataSasInitTableOverflow_t,964 *pMpi2EventDataSasInitTableOverflow_t;965 966/*SAS Topology Change List Event data */967 968/*969 *Host code (drivers, BIOS, utilities, etc.) should check NumEntries at970 *runtime before using PHY[].971 */972 973typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {974 U16 AttachedDevHandle; /*0x00 */975 U8 LinkRate; /*0x02 */976 U8 PhyStatus; /*0x03 */977} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,978 Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;979 980typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {981 U16 EnclosureHandle; /*0x00 */982 U16 ExpanderDevHandle; /*0x02 */983 U8 NumPhys; /*0x04 */984 U8 Reserved1; /*0x05 */985 U16 Reserved2; /*0x06 */986 U8 NumEntries; /*0x08 */987 U8 StartPhyNum; /*0x09 */988 U8 ExpStatus; /*0x0A */989 U8 PhysicalPort; /*0x0B */990 MPI2_EVENT_SAS_TOPO_PHY_ENTRY991 PHY[]; /*0x0C */992} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,993 *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,994 Mpi2EventDataSasTopologyChangeList_t,995 *pMpi2EventDataSasTopologyChangeList_t;996 997/*values for the ExpStatus field */998#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)999#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)1000#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)1001#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)1002#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)1003 1004/*defines for the LinkRate field */1005#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)1006#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)1007#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)1008#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)1009 1010#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)1011#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)1012#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)1013#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)1014#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)1015#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)1016#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)1017#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)1018#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)1019#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)1020#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)1021#define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C)1022 1023/*values for the PhyStatus field */1024#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)1025#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)1026/*values for the PhyStatus ReasonCode sub-field */1027#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)1028#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)1029#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)1030#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)1031#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)1032#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)1033 1034/*SAS Enclosure Device Status Change Event data */1035 1036typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {1037 U16 EnclosureHandle; /*0x00 */1038 U8 ReasonCode; /*0x02 */1039 U8 PhysicalPort; /*0x03 */1040 U64 EnclosureLogicalID; /*0x04 */1041 U16 NumSlots; /*0x0C */1042 U16 StartSlot; /*0x0E */1043 U32 PhyBits; /*0x10 */1044} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,1045 *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,1046 Mpi2EventDataSasEnclDevStatusChange_t,1047 *pMpi2EventDataSasEnclDevStatusChange_t,1048 MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,1049 *PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,1050 Mpi26EventDataEnclDevStatusChange_t,1051 *pMpi26EventDataEnclDevStatusChange_t;1052 1053/*SAS Enclosure Device Status Change event ReasonCode values */1054#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)1055#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)1056 1057/*Enclosure Device Status Change event ReasonCode values */1058#define MPI26_EVENT_ENCL_RC_ADDED (0x01)1059#define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02)1060 1061 1062typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR {1063 U16 DevHandle; /*0x00 */1064 U8 ReasonCode; /*0x02 */1065 U8 PhysicalPort; /*0x03 */1066 U32 Reserved1[2]; /*0x04 */1067 U64 SASAddress; /*0x0C */1068 U32 Reserved2[2]; /*0x14 */1069} MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,1070 *PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,1071 Mpi25EventDataSasDeviceDiscoveryError_t,1072 *pMpi25EventDataSasDeviceDiscoveryError_t;1073 1074/*SAS Device Discovery Error Event data ReasonCode values */1075#define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED (0x01)1076#define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT (0x02)1077 1078/*SAS PHY Counter Event data */1079 1080typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {1081 U64 TimeStamp; /*0x00 */1082 U32 Reserved1; /*0x08 */1083 U8 PhyEventCode; /*0x0C */1084 U8 PhyNum; /*0x0D */1085 U16 Reserved2; /*0x0E */1086 U32 PhyEventInfo; /*0x10 */1087 U8 CounterType; /*0x14 */1088 U8 ThresholdWindow; /*0x15 */1089 U8 TimeUnits; /*0x16 */1090 U8 Reserved3; /*0x17 */1091 U32 EventThreshold; /*0x18 */1092 U16 ThresholdFlags; /*0x1C */1093 U16 Reserved4; /*0x1E */1094} MPI2_EVENT_DATA_SAS_PHY_COUNTER,1095 *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,1096 Mpi2EventDataSasPhyCounter_t,1097 *pMpi2EventDataSasPhyCounter_t;1098 1099/*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h1100 *for the PhyEventCode field */1101 1102/*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h1103 *for the CounterType field */1104 1105/*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h1106 *for the TimeUnits field */1107 1108/*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h1109 *for the ThresholdFlags field */1110 1111/*SAS Quiesce Event data */1112 1113typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {1114 U8 ReasonCode; /*0x00 */1115 U8 Reserved1; /*0x01 */1116 U16 Reserved2; /*0x02 */1117 U32 Reserved3; /*0x04 */1118} MPI2_EVENT_DATA_SAS_QUIESCE,1119 *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,1120 Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;1121 1122/*SAS Quiesce Event data ReasonCode values */1123#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)1124#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)1125 1126/*Host Based Discovery Phy Event data */1127 1128typedef struct _MPI2_EVENT_HBD_PHY_SAS {1129 U8 Flags; /*0x00 */1130 U8 NegotiatedLinkRate; /*0x01 */1131 U8 PhyNum; /*0x02 */1132 U8 PhysicalPort; /*0x03 */1133 U32 Reserved1; /*0x04 */1134 U8 InitialFrame[28]; /*0x08 */1135} MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,1136 Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;1137 1138/*values for the Flags field */1139#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)1140#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)1141 1142/*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h1143 *for the NegotiatedLinkRate field */1144 1145typedef union _MPI2_EVENT_HBD_DESCRIPTOR {1146 MPI2_EVENT_HBD_PHY_SAS Sas;1147} MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,1148 Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;1149 1150typedef struct _MPI2_EVENT_DATA_HBD_PHY {1151 U8 DescriptorType; /*0x00 */1152 U8 Reserved1; /*0x01 */1153 U16 Reserved2; /*0x02 */1154 U32 Reserved3; /*0x04 */1155 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */1156} MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,1157 Mpi2EventDataHbdPhy_t,1158 *pMpi2EventDataMpi2EventDataHbdPhy_t;1159 1160/*values for the DescriptorType field */1161#define MPI2_EVENT_HBD_DT_SAS (0x01)1162 1163 1164/*PCIe Device Status Change Event data (MPI v2.6 and later) */1165 1166typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE {1167 U16 TaskTag; /*0x00 */1168 U8 ReasonCode; /*0x02 */1169 U8 PhysicalPort; /*0x03 */1170 U8 ASC; /*0x04 */1171 U8 ASCQ; /*0x05 */1172 U16 DevHandle; /*0x06 */1173 U32 Reserved2; /*0x08 */1174 U64 WWID; /*0x0C */1175 U8 LUN[8]; /*0x14 */1176} MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,1177 *PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,1178 Mpi26EventDataPCIeDeviceStatusChange_t,1179 *pMpi26EventDataPCIeDeviceStatusChange_t;1180 1181/*PCIe Device Status Change Event data ReasonCode values */1182#define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05)1183#define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07)1184#define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)1185#define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)1186#define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)1187#define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)1188#define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)1189#define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)1190#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)1191#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)1192#define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10)1193#define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x11)1194 1195 1196/*PCIe Enumeration Event data (MPI v2.6 and later) */1197 1198typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION {1199 U8 Flags; /*0x00 */1200 U8 ReasonCode; /*0x01 */1201 U8 PhysicalPort; /*0x02 */1202 U8 Reserved1; /*0x03 */1203 U32 EnumerationStatus; /*0x04 */1204} MPI26_EVENT_DATA_PCIE_ENUMERATION,1205 *PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION,1206 Mpi26EventDataPCIeEnumeration_t,1207 *pMpi26EventDataPCIeEnumeration_t;1208 1209/*PCIe Enumeration Event data Flags values */1210#define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02)1211#define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01)1212 1213/*PCIe Enumeration Event data ReasonCode values */1214#define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01)1215#define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02)1216 1217/*PCIe Enumeration Event data EnumerationStatus values */1218#define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000)1219#define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000)1220#define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000)1221 1222 1223/*PCIe Topology Change List Event data (MPI v2.6 and later) */1224 1225/*1226 *Host code (drivers, BIOS, utilities, etc.) should check NumEntries at1227 *runtime before using PortEntry[].1228 */1229 1230typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY {1231 U16 AttachedDevHandle; /*0x00 */1232 U8 PortStatus; /*0x02 */1233 U8 Reserved1; /*0x03 */1234 U8 CurrentPortInfo; /*0x04 */1235 U8 Reserved2; /*0x05 */1236 U8 PreviousPortInfo; /*0x06 */1237 U8 Reserved3; /*0x07 */1238} MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,1239 *PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,1240 Mpi26EventPCIeTopoPortEntry_t,1241 *pMpi26EventPCIeTopoPortEntry_t;1242 1243/*PCIe Topology Change List Event data PortStatus values */1244#define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01)1245#define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02)1246#define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03)1247#define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04)1248#define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)1249 1250/*PCIe Topology Change List Event data defines for CurrentPortInfo and1251 *PreviousPortInfo1252 */1253#define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0)1254#define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)1255#define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10)1256#define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20)1257#define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30)1258#define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40)1259#define MPI26_EVENT_PCIE_TOPO_PI_16_LANES (0x50)1260 1261#define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F)1262#define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)1263#define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)1264#define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)1265#define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03)1266#define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04)1267#define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05)1268 1269typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST {1270 U16 EnclosureHandle; /*0x00 */1271 U16 SwitchDevHandle; /*0x02 */1272 U8 NumPorts; /*0x04 */1273 U8 Reserved1; /*0x05 */1274 U16 Reserved2; /*0x06 */1275 U8 NumEntries; /*0x08 */1276 U8 StartPortNum; /*0x09 */1277 U8 SwitchStatus; /*0x0A */1278 U8 PhysicalPort; /*0x0B */1279 MPI26_EVENT_PCIE_TOPO_PORT_ENTRY1280 PortEntry[]; /*0x0C */1281} MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,1282 *PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,1283 Mpi26EventDataPCIeTopologyChangeList_t,1284 *pMpi26EventDataPCIeTopologyChangeList_t;1285 1286/*PCIe Topology Change List Event data SwitchStatus values */1287#define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00)1288#define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01)1289#define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)1290#define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)1291#define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)1292 1293/*PCIe Link Counter Event data (MPI v2.6 and later) */1294 1295typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER {1296 U64 TimeStamp; /*0x00 */1297 U32 Reserved1; /*0x08 */1298 U8 LinkEventCode; /*0x0C */1299 U8 LinkNum; /*0x0D */1300 U16 Reserved2; /*0x0E */1301 U32 LinkEventInfo; /*0x10 */1302 U8 CounterType; /*0x14 */1303 U8 ThresholdWindow; /*0x15 */1304 U8 TimeUnits; /*0x16 */1305 U8 Reserved3; /*0x17 */1306 U32 EventThreshold; /*0x18 */1307 U16 ThresholdFlags; /*0x1C */1308 U16 Reserved4; /*0x1E */1309} MPI26_EVENT_DATA_PCIE_LINK_COUNTER,1310 *PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER,1311 Mpi26EventDataPcieLinkCounter_t, *pMpi26EventDataPcieLinkCounter_t;1312 1313 1314/*use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode1315 *field1316 */1317 1318/*use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType1319 *field1320 */1321 1322/*use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits1323 *field1324 */1325 1326/*use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags1327 *field1328 */1329 1330/****************************************************************************1331* EventAck message1332****************************************************************************/1333 1334/*EventAck Request message */1335typedef struct _MPI2_EVENT_ACK_REQUEST {1336 U16 Reserved1; /*0x00 */1337 U8 ChainOffset; /*0x02 */1338 U8 Function; /*0x03 */1339 U16 Reserved2; /*0x04 */1340 U8 Reserved3; /*0x06 */1341 U8 MsgFlags; /*0x07 */1342 U8 VP_ID; /*0x08 */1343 U8 VF_ID; /*0x09 */1344 U16 Reserved4; /*0x0A */1345 U16 Event; /*0x0C */1346 U16 Reserved5; /*0x0E */1347 U32 EventContext; /*0x10 */1348} MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,1349 Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;1350 1351/*EventAck Reply message */1352typedef struct _MPI2_EVENT_ACK_REPLY {1353 U16 Reserved1; /*0x00 */1354 U8 MsgLength; /*0x02 */1355 U8 Function; /*0x03 */1356 U16 Reserved2; /*0x04 */1357 U8 Reserved3; /*0x06 */1358 U8 MsgFlags; /*0x07 */1359 U8 VP_ID; /*0x08 */1360 U8 VF_ID; /*0x09 */1361 U16 Reserved4; /*0x0A */1362 U16 Reserved5; /*0x0C */1363 U16 IOCStatus; /*0x0E */1364 U32 IOCLogInfo; /*0x10 */1365} MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,1366 Mpi2EventAckReply_t, *pMpi2EventAckReply_t;1367 1368/****************************************************************************1369* SendHostMessage message1370****************************************************************************/1371 1372/*SendHostMessage Request message */1373typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {1374 U16 HostDataLength; /*0x00 */1375 U8 ChainOffset; /*0x02 */1376 U8 Function; /*0x03 */1377 U16 Reserved1; /*0x04 */1378 U8 Reserved2; /*0x06 */1379 U8 MsgFlags; /*0x07 */1380 U8 VP_ID; /*0x08 */1381 U8 VF_ID; /*0x09 */1382 U16 Reserved3; /*0x0A */1383 U8 Reserved4; /*0x0C */1384 U8 DestVF_ID; /*0x0D */1385 U16 Reserved5; /*0x0E */1386 U32 Reserved6; /*0x10 */1387 U32 Reserved7; /*0x14 */1388 U32 Reserved8; /*0x18 */1389 U32 Reserved9; /*0x1C */1390 U32 Reserved10; /*0x20 */1391 U32 HostData[]; /*0x24 */1392} MPI2_SEND_HOST_MESSAGE_REQUEST,1393 *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,1394 Mpi2SendHostMessageRequest_t,1395 *pMpi2SendHostMessageRequest_t;1396 1397/*SendHostMessage Reply message */1398typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {1399 U16 HostDataLength; /*0x00 */1400 U8 MsgLength; /*0x02 */1401 U8 Function; /*0x03 */1402 U16 Reserved1; /*0x04 */1403 U8 Reserved2; /*0x06 */1404 U8 MsgFlags; /*0x07 */1405 U8 VP_ID; /*0x08 */1406 U8 VF_ID; /*0x09 */1407 U16 Reserved3; /*0x0A */1408 U16 Reserved4; /*0x0C */1409 U16 IOCStatus; /*0x0E */1410 U32 IOCLogInfo; /*0x10 */1411} MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,1412 Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;1413 1414/****************************************************************************1415* FWDownload message1416****************************************************************************/1417 1418/*MPI v2.0 FWDownload Request message */1419typedef struct _MPI2_FW_DOWNLOAD_REQUEST {1420 U8 ImageType; /*0x00 */1421 U8 Reserved1; /*0x01 */1422 U8 ChainOffset; /*0x02 */1423 U8 Function; /*0x03 */1424 U16 Reserved2; /*0x04 */1425 U8 Reserved3; /*0x06 */1426 U8 MsgFlags; /*0x07 */1427 U8 VP_ID; /*0x08 */1428 U8 VF_ID; /*0x09 */1429 U16 Reserved4; /*0x0A */1430 U32 TotalImageSize; /*0x0C */1431 U32 Reserved5; /*0x10 */1432 MPI2_MPI_SGE_UNION SGL; /*0x14 */1433} MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,1434 Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;1435 1436#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)1437 1438#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)1439#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)1440#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)1441#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)1442#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)1443#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)1444#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)1445#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)1446#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C)1447#define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP (0x0D)1448#define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E)1449#define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F)1450#define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10)1451#define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11)1452#define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12)1453#define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13)1454#define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14)1455/*MPI v2.6 and newer */1456#define MPI2_FW_DOWNLOAD_ITYPE_CPLD (0x15)1457#define MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)1458#define MPI2_FW_DOWNLOAD_ITYPE_COREDUMP (0x17)1459#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)1460 1461/*MPI v2.0 FWDownload TransactionContext Element */1462typedef struct _MPI2_FW_DOWNLOAD_TCSGE {1463 U8 Reserved1; /*0x00 */1464 U8 ContextSize; /*0x01 */1465 U8 DetailsLength; /*0x02 */1466 U8 Flags; /*0x03 */1467 U32 Reserved2; /*0x04 */1468 U32 ImageOffset; /*0x08 */1469 U32 ImageSize; /*0x0C */1470} MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,1471 Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;1472 1473/*MPI v2.5 FWDownload Request message */1474typedef struct _MPI25_FW_DOWNLOAD_REQUEST {1475 U8 ImageType; /*0x00 */1476 U8 Reserved1; /*0x01 */1477 U8 ChainOffset; /*0x02 */1478 U8 Function; /*0x03 */1479 U16 Reserved2; /*0x04 */1480 U8 Reserved3; /*0x06 */1481 U8 MsgFlags; /*0x07 */1482 U8 VP_ID; /*0x08 */1483 U8 VF_ID; /*0x09 */1484 U16 Reserved4; /*0x0A */1485 U32 TotalImageSize; /*0x0C */1486 U32 Reserved5; /*0x10 */1487 U32 Reserved6; /*0x14 */1488 U32 ImageOffset; /*0x18 */1489 U32 ImageSize; /*0x1C */1490 MPI25_SGE_IO_UNION SGL; /*0x20 */1491} MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,1492 Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;1493 1494/*FWDownload Reply message */1495typedef struct _MPI2_FW_DOWNLOAD_REPLY {1496 U8 ImageType; /*0x00 */1497 U8 Reserved1; /*0x01 */1498 U8 MsgLength; /*0x02 */1499 U8 Function; /*0x03 */1500 U16 Reserved2; /*0x04 */1501 U8 Reserved3; /*0x06 */1502 U8 MsgFlags; /*0x07 */1503 U8 VP_ID; /*0x08 */1504 U8 VF_ID; /*0x09 */1505 U16 Reserved4; /*0x0A */1506 U16 Reserved5; /*0x0C */1507 U16 IOCStatus; /*0x0E */1508 U32 IOCLogInfo; /*0x10 */1509} MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,1510 Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;1511 1512/****************************************************************************1513* FWUpload message1514****************************************************************************/1515 1516/*MPI v2.0 FWUpload Request message */1517typedef struct _MPI2_FW_UPLOAD_REQUEST {1518 U8 ImageType; /*0x00 */1519 U8 Reserved1; /*0x01 */1520 U8 ChainOffset; /*0x02 */1521 U8 Function; /*0x03 */1522 U16 Reserved2; /*0x04 */1523 U8 Reserved3; /*0x06 */1524 U8 MsgFlags; /*0x07 */1525 U8 VP_ID; /*0x08 */1526 U8 VF_ID; /*0x09 */1527 U16 Reserved4; /*0x0A */1528 U32 Reserved5; /*0x0C */1529 U32 Reserved6; /*0x10 */1530 MPI2_MPI_SGE_UNION SGL; /*0x14 */1531} MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,1532 Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;1533 1534#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)1535#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)1536#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)1537#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)1538#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)1539#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)1540#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)1541#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)1542#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)1543#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)1544#define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D)1545#define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E)1546#define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F)1547#define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10)1548#define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11)1549#define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12)1550#define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13)1551#define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14)1552 1553 1554/*MPI v2.0 FWUpload TransactionContext Element */1555typedef struct _MPI2_FW_UPLOAD_TCSGE {1556 U8 Reserved1; /*0x00 */1557 U8 ContextSize; /*0x01 */1558 U8 DetailsLength; /*0x02 */1559 U8 Flags; /*0x03 */1560 U32 Reserved2; /*0x04 */1561 U32 ImageOffset; /*0x08 */1562 U32 ImageSize; /*0x0C */1563} MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,1564 Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;1565 1566/*MPI v2.5 FWUpload Request message */1567typedef struct _MPI25_FW_UPLOAD_REQUEST {1568 U8 ImageType; /*0x00 */1569 U8 Reserved1; /*0x01 */1570 U8 ChainOffset; /*0x02 */1571 U8 Function; /*0x03 */1572 U16 Reserved2; /*0x04 */1573 U8 Reserved3; /*0x06 */1574 U8 MsgFlags; /*0x07 */1575 U8 VP_ID; /*0x08 */1576 U8 VF_ID; /*0x09 */1577 U16 Reserved4; /*0x0A */1578 U32 Reserved5; /*0x0C */1579 U32 Reserved6; /*0x10 */1580 U32 Reserved7; /*0x14 */1581 U32 ImageOffset; /*0x18 */1582 U32 ImageSize; /*0x1C */1583 MPI25_SGE_IO_UNION SGL; /*0x20 */1584} MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,1585 Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;1586 1587/*FWUpload Reply message */1588typedef struct _MPI2_FW_UPLOAD_REPLY {1589 U8 ImageType; /*0x00 */1590 U8 Reserved1; /*0x01 */1591 U8 MsgLength; /*0x02 */1592 U8 Function; /*0x03 */1593 U16 Reserved2; /*0x04 */1594 U8 Reserved3; /*0x06 */1595 U8 MsgFlags; /*0x07 */1596 U8 VP_ID; /*0x08 */1597 U8 VF_ID; /*0x09 */1598 U16 Reserved4; /*0x0A */1599 U16 Reserved5; /*0x0C */1600 U16 IOCStatus; /*0x0E */1601 U32 IOCLogInfo; /*0x10 */1602 U32 ActualImageSize; /*0x14 */1603} MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,1604 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;1605 1606 1607/****************************************************************************1608* PowerManagementControl message1609****************************************************************************/1610 1611/*PowerManagementControl Request message */1612typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {1613 U8 Feature; /*0x00 */1614 U8 Reserved1; /*0x01 */1615 U8 ChainOffset; /*0x02 */1616 U8 Function; /*0x03 */1617 U16 Reserved2; /*0x04 */1618 U8 Reserved3; /*0x06 */1619 U8 MsgFlags; /*0x07 */1620 U8 VP_ID; /*0x08 */1621 U8 VF_ID; /*0x09 */1622 U16 Reserved4; /*0x0A */1623 U8 Parameter1; /*0x0C */1624 U8 Parameter2; /*0x0D */1625 U8 Parameter3; /*0x0E */1626 U8 Parameter4; /*0x0F */1627 U32 Reserved5; /*0x10 */1628 U32 Reserved6; /*0x14 */1629} MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,1630 Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;1631 1632/*defines for the Feature field */1633#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)1634#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)1635#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /*obsolete */1636#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)1637#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05)1638#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)1639#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)1640 1641/*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */1642/*Parameter1 contains a PHY number */1643/*Parameter2 indicates power condition action using these defines */1644#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)1645#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)1646#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)1647/*Parameter3 and Parameter4 are reserved */1648 1649/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION1650 * Feature */1651/*Parameter1 contains SAS port width modulation group number */1652/*Parameter2 indicates IOC action using these defines */1653#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)1654#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)1655#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)1656/*Parameter3 indicates desired modulation level using these defines */1657#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)1658#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)1659#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)1660#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)1661/*Parameter4 is reserved */1662 1663/*this next set (_PCIE_LINK) is obsolete */1664/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */1665/*Parameter1 indicates desired PCIe link speed using these defines */1666#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /*obsolete */1667#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /*obsolete */1668#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /*obsolete */1669/*Parameter2 indicates desired PCIe link width using these defines */1670#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /*obsolete */1671#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /*obsolete */1672#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /*obsolete */1673#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /*obsolete */1674/*Parameter3 and Parameter4 are reserved */1675 1676/*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */1677/*Parameter1 indicates desired IOC hardware clock speed using these defines */1678#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)1679#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)1680#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)1681#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)1682/*Parameter2, Parameter3, and Parameter4 are reserved */1683 1684/*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/1685/*Parameter1 indicates host action regarding global power management mode */1686#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01)1687#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02)1688#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03)1689/*Parameter2 indicates the requested global power management mode */1690#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01)1691#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08)1692#define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40)1693/*Parameter3 and Parameter4 are reserved */1694 1695/*PowerManagementControl Reply message */1696typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {1697 U8 Feature; /*0x00 */1698 U8 Reserved1; /*0x01 */1699 U8 MsgLength; /*0x02 */1700 U8 Function; /*0x03 */1701 U16 Reserved2; /*0x04 */1702 U8 Reserved3; /*0x06 */1703 U8 MsgFlags; /*0x07 */1704 U8 VP_ID; /*0x08 */1705 U8 VF_ID; /*0x09 */1706 U16 Reserved4; /*0x0A */1707 U16 Reserved5; /*0x0C */1708 U16 IOCStatus; /*0x0E */1709 U32 IOCLogInfo; /*0x10 */1710} MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,1711 Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;1712 1713/****************************************************************************1714* IO Unit Control messages (MPI v2.6 and later only.)1715****************************************************************************/1716 1717/* IO Unit Control Request Message */1718typedef struct _MPI26_IOUNIT_CONTROL_REQUEST {1719 U8 Operation; /* 0x00 */1720 U8 Reserved1; /* 0x01 */1721 U8 ChainOffset; /* 0x02 */1722 U8 Function; /* 0x03 */1723 U16 DevHandle; /* 0x04 */1724 U8 IOCParameter; /* 0x06 */1725 U8 MsgFlags; /* 0x07 */1726 U8 VP_ID; /* 0x08 */1727 U8 VF_ID; /* 0x09 */1728 U16 Reserved3; /* 0x0A */1729 U16 Reserved4; /* 0x0C */1730 U8 PhyNum; /* 0x0E */1731 U8 PrimFlags; /* 0x0F */1732 U32 Primitive; /* 0x10 */1733 U8 LookupMethod; /* 0x14 */1734 U8 Reserved5; /* 0x15 */1735 U16 SlotNumber; /* 0x16 */1736 U64 LookupAddress; /* 0x18 */1737 U32 IOCParameterValue; /* 0x20 */1738 U32 Reserved7; /* 0x24 */1739 U32 Reserved8; /* 0x28 */1740} MPI26_IOUNIT_CONTROL_REQUEST,1741 *PTR_MPI26_IOUNIT_CONTROL_REQUEST,1742 Mpi26IoUnitControlRequest_t,1743 *pMpi26IoUnitControlRequest_t;1744 1745/* values for the Operation field */1746#define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02)1747#define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06)1748#define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07)1749#define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08)1750#define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09)1751#define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A)1752#define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B)1753#define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D)1754#define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E)1755#define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F)1756#define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10)1757#define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11)1758#define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12)1759#define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13)1760#define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14)1761#define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15)1762#define MPI26_CTRL_OP_SHUTDOWN (0x16)1763#define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17)1764#define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18)1765#define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19)1766#define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A)1767#define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B)1768#define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80)1769 1770/* values for the PrimFlags field */1771#define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08)1772#define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02)1773#define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01)1774 1775/* values for the LookupMethod field */1776#define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)1777#define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)1778#define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)1779 1780 1781/* IO Unit Control Reply Message */1782typedef struct _MPI26_IOUNIT_CONTROL_REPLY {1783 U8 Operation; /* 0x00 */1784 U8 Reserved1; /* 0x01 */1785 U8 MsgLength; /* 0x02 */1786 U8 Function; /* 0x03 */1787 U16 DevHandle; /* 0x04 */1788 U8 IOCParameter; /* 0x06 */1789 U8 MsgFlags; /* 0x07 */1790 U8 VP_ID; /* 0x08 */1791 U8 VF_ID; /* 0x09 */1792 U16 Reserved3; /* 0x0A */1793 U16 Reserved4; /* 0x0C */1794 U16 IOCStatus; /* 0x0E */1795 U32 IOCLogInfo; /* 0x10 */1796} MPI26_IOUNIT_CONTROL_REPLY,1797 *PTR_MPI26_IOUNIT_CONTROL_REPLY,1798 Mpi26IoUnitControlReply_t,1799 *pMpi26IoUnitControlReply_t;1800 1801 1802#endif1803