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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Marvell 88SE64xx/88SE94xx pci init4 *5 * Copyright 2007 Red Hat, Inc.6 * Copyright 2008 Marvell. <kewei@marvell.com>7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>8*/9 10 11#include "mv_sas.h"12 13int interrupt_coalescing = 0x80;14 15static struct scsi_transport_template *mvs_stt;16static const struct mvs_chip_info mvs_chips[] = {17 [chip_6320] = { 1, 2, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },18 [chip_6440] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },19 [chip_6485] = { 1, 8, 0x800, 33, 32, 6, 10, &mvs_64xx_dispatch, },20 [chip_9180] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },21 [chip_9480] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },22 [chip_9445] = { 1, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },23 [chip_9485] = { 2, 4, 0x800, 17, 64, 8, 11, &mvs_94xx_dispatch, },24 [chip_1300] = { 1, 4, 0x400, 17, 16, 6, 9, &mvs_64xx_dispatch, },25 [chip_1320] = { 2, 4, 0x800, 17, 64, 8, 9, &mvs_94xx_dispatch, },26};27 28static const struct attribute_group *mvst_host_groups[];29static const struct attribute_group *mvst_sdev_groups[];30 31#define SOC_SAS_NUM 232 33static const struct scsi_host_template mvs_sht = {34 LIBSAS_SHT_BASE35 .scan_finished = mvs_scan_finished,36 .scan_start = mvs_scan_start,37 .can_queue = 1,38 .sg_tablesize = SG_ALL,39 .shost_groups = mvst_host_groups,40 .sdev_groups = mvst_sdev_groups,41 .track_queue_depth = 1,42};43 44static struct sas_domain_function_template mvs_transport_ops = {45 .lldd_dev_found = mvs_dev_found,46 .lldd_dev_gone = mvs_dev_gone,47 .lldd_execute_task = mvs_queue_command,48 .lldd_control_phy = mvs_phy_control,49 50 .lldd_abort_task = mvs_abort_task,51 .lldd_abort_task_set = sas_abort_task_set,52 .lldd_clear_task_set = sas_clear_task_set,53 .lldd_I_T_nexus_reset = mvs_I_T_nexus_reset,54 .lldd_lu_reset = mvs_lu_reset,55 .lldd_query_task = mvs_query_task,56 .lldd_port_formed = mvs_port_formed,57 .lldd_port_deformed = mvs_port_deformed,58 59 .lldd_write_gpio = mvs_gpio_write,60 61};62 63static void mvs_phy_init(struct mvs_info *mvi, int phy_id)64{65 struct mvs_phy *phy = &mvi->phy[phy_id];66 struct asd_sas_phy *sas_phy = &phy->sas_phy;67 68 phy->mvi = mvi;69 phy->port = NULL;70 timer_setup(&phy->timer, NULL, 0);71 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;72 sas_phy->iproto = SAS_PROTOCOL_ALL;73 sas_phy->tproto = 0;74 sas_phy->role = PHY_ROLE_INITIATOR;75 sas_phy->oob_mode = OOB_NOT_CONNECTED;76 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;77 78 sas_phy->id = phy_id;79 sas_phy->sas_addr = &mvi->sas_addr[0];80 sas_phy->frame_rcvd = &phy->frame_rcvd[0];81 sas_phy->ha = (struct sas_ha_struct *)mvi->shost->hostdata;82 sas_phy->lldd_phy = phy;83}84 85static void mvs_free(struct mvs_info *mvi)86{87 struct mvs_wq *mwq;88 int slot_nr;89 90 if (!mvi)91 return;92 93 if (mvi->flags & MVF_FLAG_SOC)94 slot_nr = MVS_SOC_SLOTS;95 else96 slot_nr = MVS_CHIP_SLOT_SZ;97 98 dma_pool_destroy(mvi->dma_pool);99 100 if (mvi->tx)101 dma_free_coherent(mvi->dev,102 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,103 mvi->tx, mvi->tx_dma);104 if (mvi->rx_fis)105 dma_free_coherent(mvi->dev, MVS_RX_FISL_SZ,106 mvi->rx_fis, mvi->rx_fis_dma);107 if (mvi->rx)108 dma_free_coherent(mvi->dev,109 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),110 mvi->rx, mvi->rx_dma);111 if (mvi->slot)112 dma_free_coherent(mvi->dev,113 sizeof(*mvi->slot) * slot_nr,114 mvi->slot, mvi->slot_dma);115 116 if (mvi->bulk_buffer)117 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,118 mvi->bulk_buffer, mvi->bulk_buffer_dma);119 if (mvi->bulk_buffer1)120 dma_free_coherent(mvi->dev, TRASH_BUCKET_SIZE,121 mvi->bulk_buffer1, mvi->bulk_buffer_dma1);122 123 MVS_CHIP_DISP->chip_iounmap(mvi);124 if (mvi->shost)125 scsi_host_put(mvi->shost);126 list_for_each_entry(mwq, &mvi->wq_list, entry)127 cancel_delayed_work(&mwq->work_q);128 kfree(mvi->rsvd_tags);129 kfree(mvi);130}131 132#ifdef CONFIG_SCSI_MVSAS_TASKLET133static void mvs_tasklet(unsigned long opaque)134{135 u32 stat;136 u16 core_nr, i = 0;137 138 struct mvs_info *mvi;139 struct sas_ha_struct *sha = (struct sas_ha_struct *)opaque;140 141 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;142 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];143 144 if (unlikely(!mvi))145 BUG_ON(1);146 147 stat = MVS_CHIP_DISP->isr_status(mvi, mvi->pdev->irq);148 if (!stat)149 goto out;150 151 for (i = 0; i < core_nr; i++) {152 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];153 MVS_CHIP_DISP->isr(mvi, mvi->pdev->irq, stat);154 }155out:156 MVS_CHIP_DISP->interrupt_enable(mvi);157 158}159#endif160 161static irqreturn_t mvs_interrupt(int irq, void *opaque)162{163 u32 stat;164 struct mvs_info *mvi;165 struct sas_ha_struct *sha = opaque;166#ifndef CONFIG_SCSI_MVSAS_TASKLET167 u32 i;168 u32 core_nr;169 170 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;171#endif172 173 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];174 175 if (unlikely(!mvi))176 return IRQ_NONE;177#ifdef CONFIG_SCSI_MVSAS_TASKLET178 MVS_CHIP_DISP->interrupt_disable(mvi);179#endif180 181 stat = MVS_CHIP_DISP->isr_status(mvi, irq);182 if (!stat) {183 #ifdef CONFIG_SCSI_MVSAS_TASKLET184 MVS_CHIP_DISP->interrupt_enable(mvi);185 #endif186 return IRQ_NONE;187 }188 189#ifdef CONFIG_SCSI_MVSAS_TASKLET190 tasklet_schedule(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);191#else192 for (i = 0; i < core_nr; i++) {193 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];194 MVS_CHIP_DISP->isr(mvi, irq, stat);195 }196#endif197 return IRQ_HANDLED;198}199 200static int mvs_alloc(struct mvs_info *mvi, struct Scsi_Host *shost)201{202 int i = 0, slot_nr;203 char pool_name[32];204 205 if (mvi->flags & MVF_FLAG_SOC)206 slot_nr = MVS_SOC_SLOTS;207 else208 slot_nr = MVS_CHIP_SLOT_SZ;209 210 spin_lock_init(&mvi->lock);211 for (i = 0; i < mvi->chip->n_phy; i++) {212 mvs_phy_init(mvi, i);213 mvi->port[i].wide_port_phymap = 0;214 mvi->port[i].port_attached = 0;215 INIT_LIST_HEAD(&mvi->port[i].list);216 }217 for (i = 0; i < MVS_MAX_DEVICES; i++) {218 mvi->devices[i].taskfileset = MVS_ID_NOT_MAPPED;219 mvi->devices[i].dev_type = SAS_PHY_UNUSED;220 mvi->devices[i].device_id = i;221 mvi->devices[i].dev_status = MVS_DEV_NORMAL;222 }223 224 /*225 * alloc and init our DMA areas226 */227 mvi->tx = dma_alloc_coherent(mvi->dev,228 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,229 &mvi->tx_dma, GFP_KERNEL);230 if (!mvi->tx)231 goto err_out;232 mvi->rx_fis = dma_alloc_coherent(mvi->dev, MVS_RX_FISL_SZ,233 &mvi->rx_fis_dma, GFP_KERNEL);234 if (!mvi->rx_fis)235 goto err_out;236 237 mvi->rx = dma_alloc_coherent(mvi->dev,238 sizeof(*mvi->rx) * (MVS_RX_RING_SZ + 1),239 &mvi->rx_dma, GFP_KERNEL);240 if (!mvi->rx)241 goto err_out;242 mvi->rx[0] = cpu_to_le32(0xfff);243 mvi->rx_cons = 0xfff;244 245 mvi->slot = dma_alloc_coherent(mvi->dev,246 sizeof(*mvi->slot) * slot_nr,247 &mvi->slot_dma, GFP_KERNEL);248 if (!mvi->slot)249 goto err_out;250 251 mvi->bulk_buffer = dma_alloc_coherent(mvi->dev,252 TRASH_BUCKET_SIZE,253 &mvi->bulk_buffer_dma, GFP_KERNEL);254 if (!mvi->bulk_buffer)255 goto err_out;256 257 mvi->bulk_buffer1 = dma_alloc_coherent(mvi->dev,258 TRASH_BUCKET_SIZE,259 &mvi->bulk_buffer_dma1, GFP_KERNEL);260 if (!mvi->bulk_buffer1)261 goto err_out;262 263 sprintf(pool_name, "%s%d", "mvs_dma_pool", mvi->id);264 mvi->dma_pool = dma_pool_create(pool_name, &mvi->pdev->dev,265 MVS_SLOT_BUF_SZ, 16, 0);266 if (!mvi->dma_pool) {267 printk(KERN_DEBUG "failed to create dma pool %s.\n", pool_name);268 goto err_out;269 }270 271 return 0;272err_out:273 return 1;274}275 276 277int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex)278{279 unsigned long res_start, res_len, res_flag_ex = 0;280 struct pci_dev *pdev = mvi->pdev;281 if (bar_ex != -1) {282 /*283 * ioremap main and peripheral registers284 */285 res_start = pci_resource_start(pdev, bar_ex);286 res_len = pci_resource_len(pdev, bar_ex);287 if (!res_start || !res_len)288 goto err_out;289 290 res_flag_ex = pci_resource_flags(pdev, bar_ex);291 if (res_flag_ex & IORESOURCE_MEM)292 mvi->regs_ex = ioremap(res_start, res_len);293 else294 mvi->regs_ex = (void *)res_start;295 if (!mvi->regs_ex)296 goto err_out;297 }298 299 res_start = pci_resource_start(pdev, bar);300 res_len = pci_resource_len(pdev, bar);301 if (!res_start || !res_len) {302 iounmap(mvi->regs_ex);303 mvi->regs_ex = NULL;304 goto err_out;305 }306 307 mvi->regs = ioremap(res_start, res_len);308 309 if (!mvi->regs) {310 if (mvi->regs_ex && (res_flag_ex & IORESOURCE_MEM))311 iounmap(mvi->regs_ex);312 mvi->regs_ex = NULL;313 goto err_out;314 }315 316 return 0;317err_out:318 return -1;319}320 321void mvs_iounmap(void __iomem *regs)322{323 iounmap(regs);324}325 326static struct mvs_info *mvs_pci_alloc(struct pci_dev *pdev,327 const struct pci_device_id *ent,328 struct Scsi_Host *shost, unsigned int id)329{330 struct mvs_info *mvi = NULL;331 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);332 333 mvi = kzalloc(sizeof(*mvi) +334 (1L << mvs_chips[ent->driver_data].slot_width) *335 sizeof(struct mvs_slot_info), GFP_KERNEL);336 if (!mvi)337 return NULL;338 339 mvi->pdev = pdev;340 mvi->dev = &pdev->dev;341 mvi->chip_id = ent->driver_data;342 mvi->chip = &mvs_chips[mvi->chip_id];343 INIT_LIST_HEAD(&mvi->wq_list);344 345 ((struct mvs_prv_info *)sha->lldd_ha)->mvi[id] = mvi;346 ((struct mvs_prv_info *)sha->lldd_ha)->n_phy = mvi->chip->n_phy;347 348 mvi->id = id;349 mvi->sas = sha;350 mvi->shost = shost;351 352 mvi->rsvd_tags = bitmap_zalloc(MVS_RSVD_SLOTS, GFP_KERNEL);353 if (!mvi->rsvd_tags)354 goto err_out;355 356 if (MVS_CHIP_DISP->chip_ioremap(mvi))357 goto err_out;358 if (!mvs_alloc(mvi, shost))359 return mvi;360err_out:361 mvs_free(mvi);362 return NULL;363}364 365static int pci_go_64(struct pci_dev *pdev)366{367 int rc;368 369 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));370 if (rc) {371 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));372 if (rc) {373 dev_printk(KERN_ERR, &pdev->dev,374 "32-bit DMA enable failed\n");375 return rc;376 }377 }378 379 return rc;380}381 382static int mvs_prep_sas_ha_init(struct Scsi_Host *shost,383 const struct mvs_chip_info *chip_info)384{385 int phy_nr, port_nr; unsigned short core_nr;386 struct asd_sas_phy **arr_phy;387 struct asd_sas_port **arr_port;388 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);389 390 core_nr = chip_info->n_host;391 phy_nr = core_nr * chip_info->n_phy;392 port_nr = phy_nr;393 394 memset(sha, 0x00, sizeof(struct sas_ha_struct));395 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);396 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);397 if (!arr_phy || !arr_port)398 goto exit_free;399 400 sha->sas_phy = arr_phy;401 sha->sas_port = arr_port;402 sha->shost = shost;403 404 sha->lldd_ha = kzalloc(sizeof(struct mvs_prv_info), GFP_KERNEL);405 if (!sha->lldd_ha)406 goto exit_free;407 408 ((struct mvs_prv_info *)sha->lldd_ha)->n_host = core_nr;409 410 shost->transportt = mvs_stt;411 shost->max_id = MVS_MAX_DEVICES;412 shost->max_lun = ~0;413 shost->max_channel = 1;414 shost->max_cmd_len = 16;415 416 return 0;417exit_free:418 kfree(arr_phy);419 kfree(arr_port);420 return -1;421 422}423 424static void mvs_post_sas_ha_init(struct Scsi_Host *shost,425 const struct mvs_chip_info *chip_info)426{427 int can_queue, i = 0, j = 0;428 struct mvs_info *mvi = NULL;429 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);430 unsigned short nr_core = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;431 432 for (j = 0; j < nr_core; j++) {433 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];434 for (i = 0; i < chip_info->n_phy; i++) {435 sha->sas_phy[j * chip_info->n_phy + i] =436 &mvi->phy[i].sas_phy;437 sha->sas_port[j * chip_info->n_phy + i] =438 &mvi->port[i].sas_port;439 }440 }441 442 sha->sas_ha_name = DRV_NAME;443 sha->dev = mvi->dev;444 sha->sas_addr = &mvi->sas_addr[0];445 446 sha->num_phys = nr_core * chip_info->n_phy;447 448 if (mvi->flags & MVF_FLAG_SOC)449 can_queue = MVS_SOC_CAN_QUEUE;450 else451 can_queue = MVS_CHIP_SLOT_SZ;452 453 can_queue -= MVS_RSVD_SLOTS;454 455 shost->sg_tablesize = min_t(u16, SG_ALL, MVS_MAX_SG);456 shost->can_queue = can_queue;457 mvi->shost->cmd_per_lun = MVS_QUEUE_SIZE;458 sha->shost = mvi->shost;459}460 461static void mvs_init_sas_add(struct mvs_info *mvi)462{463 u8 i;464 for (i = 0; i < mvi->chip->n_phy; i++) {465 mvi->phy[i].dev_sas_addr = 0x5005043011ab0000ULL;466 mvi->phy[i].dev_sas_addr =467 cpu_to_be64((u64)(*(u64 *)&mvi->phy[i].dev_sas_addr));468 }469 470 memcpy(mvi->sas_addr, &mvi->phy[0].dev_sas_addr, SAS_ADDR_SIZE);471}472 473static int mvs_pci_init(struct pci_dev *pdev, const struct pci_device_id *ent)474{475 unsigned int rc, nhost = 0;476 struct mvs_info *mvi;477 irq_handler_t irq_handler = mvs_interrupt;478 struct Scsi_Host *shost = NULL;479 const struct mvs_chip_info *chip;480 481 dev_printk(KERN_INFO, &pdev->dev,482 "mvsas: driver version %s\n", DRV_VERSION);483 rc = pci_enable_device(pdev);484 if (rc)485 goto err_out_enable;486 487 pci_set_master(pdev);488 489 rc = pci_request_regions(pdev, DRV_NAME);490 if (rc)491 goto err_out_disable;492 493 rc = pci_go_64(pdev);494 if (rc)495 goto err_out_regions;496 497 shost = scsi_host_alloc(&mvs_sht, sizeof(void *));498 if (!shost) {499 rc = -ENOMEM;500 goto err_out_regions;501 }502 503 chip = &mvs_chips[ent->driver_data];504 SHOST_TO_SAS_HA(shost) =505 kcalloc(1, sizeof(struct sas_ha_struct), GFP_KERNEL);506 if (!SHOST_TO_SAS_HA(shost)) {507 scsi_host_put(shost);508 rc = -ENOMEM;509 goto err_out_regions;510 }511 512 rc = mvs_prep_sas_ha_init(shost, chip);513 if (rc) {514 scsi_host_put(shost);515 rc = -ENOMEM;516 goto err_out_regions;517 }518 519 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));520 521 do {522 mvi = mvs_pci_alloc(pdev, ent, shost, nhost);523 if (!mvi) {524 rc = -ENOMEM;525 goto err_out_regions;526 }527 528 memset(&mvi->hba_info_param, 0xFF,529 sizeof(struct hba_info_page));530 531 mvs_init_sas_add(mvi);532 533 mvi->instance = nhost;534 rc = MVS_CHIP_DISP->chip_init(mvi);535 if (rc) {536 mvs_free(mvi);537 goto err_out_regions;538 }539 nhost++;540 } while (nhost < chip->n_host);541#ifdef CONFIG_SCSI_MVSAS_TASKLET542 {543 struct mvs_prv_info *mpi = SHOST_TO_SAS_HA(shost)->lldd_ha;544 545 tasklet_init(&(mpi->mv_tasklet), mvs_tasklet,546 (unsigned long)SHOST_TO_SAS_HA(shost));547 }548#endif549 550 mvs_post_sas_ha_init(shost, chip);551 552 rc = scsi_add_host(shost, &pdev->dev);553 if (rc)554 goto err_out_shost;555 556 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));557 if (rc)558 goto err_out_shost;559 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED,560 DRV_NAME, SHOST_TO_SAS_HA(shost));561 if (rc)562 goto err_not_sas;563 564 MVS_CHIP_DISP->interrupt_enable(mvi);565 566 scsi_scan_host(mvi->shost);567 568 return 0;569 570err_not_sas:571 sas_unregister_ha(SHOST_TO_SAS_HA(shost));572err_out_shost:573 scsi_remove_host(mvi->shost);574err_out_regions:575 pci_release_regions(pdev);576err_out_disable:577 pci_disable_device(pdev);578err_out_enable:579 return rc;580}581 582static void mvs_pci_remove(struct pci_dev *pdev)583{584 unsigned short core_nr, i = 0;585 struct sas_ha_struct *sha = pci_get_drvdata(pdev);586 struct mvs_info *mvi = NULL;587 588 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;589 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];590 591#ifdef CONFIG_SCSI_MVSAS_TASKLET592 tasklet_kill(&((struct mvs_prv_info *)sha->lldd_ha)->mv_tasklet);593#endif594 595 sas_unregister_ha(sha);596 sas_remove_host(mvi->shost);597 598 MVS_CHIP_DISP->interrupt_disable(mvi);599 free_irq(mvi->pdev->irq, sha);600 for (i = 0; i < core_nr; i++) {601 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];602 mvs_free(mvi);603 }604 kfree(sha->sas_phy);605 kfree(sha->sas_port);606 kfree(sha);607 pci_release_regions(pdev);608 pci_disable_device(pdev);609 return;610}611 612static struct pci_device_id mvs_pci_table[] = {613 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },614 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },615 {616 .vendor = PCI_VENDOR_ID_MARVELL,617 .device = 0x6440,618 .subvendor = PCI_ANY_ID,619 .subdevice = 0x6480,620 .class = 0,621 .class_mask = 0,622 .driver_data = chip_6485,623 },624 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },625 { PCI_VDEVICE(MARVELL, 0x6485), chip_6485 },626 { PCI_VDEVICE(MARVELL, 0x9480), chip_9480 },627 { PCI_VDEVICE(MARVELL, 0x9180), chip_9180 },628 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1300), chip_1300 },629 { PCI_VDEVICE(ARECA, PCI_DEVICE_ID_ARECA_1320), chip_1320 },630 { PCI_VDEVICE(ADAPTEC2, 0x0450), chip_6440 },631 { PCI_VDEVICE(TTI, 0x2640), chip_6440 },632 { PCI_VDEVICE(TTI, 0x2710), chip_9480 },633 { PCI_VDEVICE(TTI, 0x2720), chip_9480 },634 { PCI_VDEVICE(TTI, 0x2721), chip_9480 },635 { PCI_VDEVICE(TTI, 0x2722), chip_9480 },636 { PCI_VDEVICE(TTI, 0x2740), chip_9480 },637 { PCI_VDEVICE(TTI, 0x2744), chip_9480 },638 { PCI_VDEVICE(TTI, 0x2760), chip_9480 },639 {640 .vendor = PCI_VENDOR_ID_MARVELL_EXT,641 .device = 0x9480,642 .subvendor = PCI_ANY_ID,643 .subdevice = 0x9480,644 .class = 0,645 .class_mask = 0,646 .driver_data = chip_9480,647 },648 {649 .vendor = PCI_VENDOR_ID_MARVELL_EXT,650 .device = 0x9445,651 .subvendor = PCI_ANY_ID,652 .subdevice = 0x9480,653 .class = 0,654 .class_mask = 0,655 .driver_data = chip_9445,656 },657 { PCI_VDEVICE(MARVELL_EXT, 0x9485), chip_9485 }, /* Marvell 9480/9485 (any vendor/model) */658 { PCI_VDEVICE(OCZ, 0x1021), chip_9485}, /* OCZ RevoDrive3 */659 { PCI_VDEVICE(OCZ, 0x1022), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */660 { PCI_VDEVICE(OCZ, 0x1040), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */661 { PCI_VDEVICE(OCZ, 0x1041), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */662 { PCI_VDEVICE(OCZ, 0x1042), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */663 { PCI_VDEVICE(OCZ, 0x1043), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */664 { PCI_VDEVICE(OCZ, 0x1044), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */665 { PCI_VDEVICE(OCZ, 0x1080), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */666 { PCI_VDEVICE(OCZ, 0x1083), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */667 { PCI_VDEVICE(OCZ, 0x1084), chip_9485}, /* OCZ RevoDrive3/zDriveR4 (exact model unknown) */668 669 { } /* terminate list */670};671 672static struct pci_driver mvs_pci_driver = {673 .name = DRV_NAME,674 .id_table = mvs_pci_table,675 .probe = mvs_pci_init,676 .remove = mvs_pci_remove,677};678 679static DEVICE_STRING_ATTR_RO(driver_version, 0444, DRV_VERSION);680 681static ssize_t interrupt_coalescing_store(struct device *cdev,682 struct device_attribute *attr,683 const char *buffer, size_t size)684{685 unsigned int val = 0;686 struct mvs_info *mvi = NULL;687 struct Scsi_Host *shost = class_to_shost(cdev);688 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);689 u8 i, core_nr;690 if (buffer == NULL)691 return size;692 693 if (sscanf(buffer, "%u", &val) != 1)694 return -EINVAL;695 696 if (val >= 0x10000) {697 mv_dprintk("interrupt coalescing timer %d us is"698 "too long\n", val);699 return strlen(buffer);700 }701 702 interrupt_coalescing = val;703 704 core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;705 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[0];706 707 if (unlikely(!mvi))708 return -EINVAL;709 710 for (i = 0; i < core_nr; i++) {711 mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[i];712 if (MVS_CHIP_DISP->tune_interrupt)713 MVS_CHIP_DISP->tune_interrupt(mvi,714 interrupt_coalescing);715 }716 mv_dprintk("set interrupt coalescing time to %d us\n",717 interrupt_coalescing);718 return strlen(buffer);719}720 721static ssize_t interrupt_coalescing_show(struct device *cdev,722 struct device_attribute *attr, char *buffer)723{724 return sysfs_emit(buffer, "%d\n", interrupt_coalescing);725}726 727static DEVICE_ATTR_RW(interrupt_coalescing);728 729static int __init mvs_init(void)730{731 int rc;732 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);733 if (!mvs_stt)734 return -ENOMEM;735 736 rc = pci_register_driver(&mvs_pci_driver);737 if (rc)738 goto err_out;739 740 return 0;741 742err_out:743 sas_release_transport(mvs_stt);744 return rc;745}746 747static void __exit mvs_exit(void)748{749 pci_unregister_driver(&mvs_pci_driver);750 sas_release_transport(mvs_stt);751}752 753static struct attribute *mvst_host_attrs[] = {754 &dev_attr_driver_version.attr.attr,755 &dev_attr_interrupt_coalescing.attr,756 NULL,757};758 759ATTRIBUTE_GROUPS(mvst_host);760 761static const struct attribute_group *mvst_sdev_groups[] = {762 &sas_ata_sdev_attr_group,763 NULL764};765 766module_init(mvs_init);767module_exit(mvs_exit);768 769MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");770MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");771MODULE_VERSION(DRV_VERSION);772MODULE_LICENSE("GPL");773#ifdef CONFIG_PCI774MODULE_DEVICE_TABLE(pci, mvs_pci_table);775#endif776