1576 lines · c
1/*2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver3 *4 * Copyright (c) 2008-2009 USI Co., Ltd.5 * All rights reserved.6 *7 * Redistribution and use in source and binary forms, with or without8 * modification, are permitted provided that the following conditions9 * are met:10 * 1. Redistributions of source code must retain the above copyright11 * notice, this list of conditions, and the following disclaimer,12 * without modification.13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer14 * substantially similar to the "NO WARRANTY" disclaimer below15 * ("Disclaimer") and any redistribution must be conditioned upon16 * including a substantially similar Disclaimer requirement for further17 * binary redistribution.18 * 3. Neither the names of the above-listed copyright holders nor the names19 * of any contributors may be used to endorse or promote products derived20 * from this software without specific prior written permission.21 *22 * Alternatively, this software may be distributed under the terms of the23 * GNU General Public License ("GPL") version 2 as published by the Free24 * Software Foundation.25 *26 * NO WARRANTY27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE37 * POSSIBILITY OF SUCH DAMAGES.38 *39 */40 41#include <linux/slab.h>42#include "pm8001_sas.h"43#include "pm8001_chips.h"44#include "pm80xx_hwi.h"45 46static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING |47 PM8001_EVENT_LOGGING | PM8001_INIT_LOGGING;48module_param(logging_level, ulong, 0644);49MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");50 51static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;52module_param(link_rate, ulong, 0644);53MODULE_PARM_DESC(link_rate, "Enable link rate.\n"54 " 1: Link rate 1.5G\n"55 " 2: Link rate 3.0G\n"56 " 4: Link rate 6.0G\n"57 " 8: Link rate 12.0G\n");58 59bool pm8001_use_msix = true;60module_param_named(use_msix, pm8001_use_msix, bool, 0444);61MODULE_PARM_DESC(zoned, "Use MSIX interrupts. Default: true");62 63static bool pm8001_use_tasklet = true;64module_param_named(use_tasklet, pm8001_use_tasklet, bool, 0444);65MODULE_PARM_DESC(zoned, "Use MSIX interrupts. Default: true");66 67static bool pm8001_read_wwn = true;68module_param_named(read_wwn, pm8001_read_wwn, bool, 0444);69MODULE_PARM_DESC(zoned, "Get WWN from the controller. Default: true");70 71static struct scsi_transport_template *pm8001_stt;72static int pm8001_init_ccb_tag(struct pm8001_hba_info *);73 74/*75 * chip info structure to identify chip key functionality as76 * encryption available/not, no of ports, hw specific function ref77 */78static const struct pm8001_chip_info pm8001_chips[] = {79 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},80 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},81 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},82 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},83 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},84 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},85 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},86 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},87 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},88 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},89 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},90};91static int pm8001_id;92 93LIST_HEAD(hba_list);94 95struct workqueue_struct *pm8001_wq;96 97static void pm8001_map_queues(struct Scsi_Host *shost)98{99 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);100 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;101 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];102 103 if (pm8001_ha->number_of_intr > 1) {104 blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1);105 return;106 }107 108 blk_mq_map_queues(qmap);109}110 111/*112 * The main structure which LLDD must register for scsi core.113 */114static const struct scsi_host_template pm8001_sht = {115 LIBSAS_SHT_BASE116 .scan_finished = pm8001_scan_finished,117 .scan_start = pm8001_scan_start,118 .can_queue = 1,119 .sg_tablesize = PM8001_MAX_DMA_SG,120 .shost_groups = pm8001_host_groups,121 .sdev_groups = pm8001_sdev_groups,122 .track_queue_depth = 1,123 .cmd_per_lun = 32,124 .map_queues = pm8001_map_queues,125};126 127/*128 * Sas layer call this function to execute specific task.129 */130static struct sas_domain_function_template pm8001_transport_ops = {131 .lldd_dev_found = pm8001_dev_found,132 .lldd_dev_gone = pm8001_dev_gone,133 134 .lldd_execute_task = pm8001_queue_command,135 .lldd_control_phy = pm8001_phy_control,136 137 .lldd_abort_task = pm8001_abort_task,138 .lldd_abort_task_set = sas_abort_task_set,139 .lldd_clear_task_set = pm8001_clear_task_set,140 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,141 .lldd_lu_reset = pm8001_lu_reset,142 .lldd_query_task = pm8001_query_task,143 .lldd_port_formed = pm8001_port_formed,144 .lldd_tmf_exec_complete = pm8001_setds_completion,145 .lldd_tmf_aborted = pm8001_tmf_aborted,146};147 148/**149 * pm8001_phy_init - initiate our adapter phys150 * @pm8001_ha: our hba structure.151 * @phy_id: phy id.152 */153static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)154{155 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];156 struct asd_sas_phy *sas_phy = &phy->sas_phy;157 phy->phy_state = PHY_LINK_DISABLE;158 phy->pm8001_ha = pm8001_ha;159 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;160 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;161 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;162 sas_phy->iproto = SAS_PROTOCOL_ALL;163 sas_phy->tproto = 0;164 sas_phy->role = PHY_ROLE_INITIATOR;165 sas_phy->oob_mode = OOB_NOT_CONNECTED;166 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;167 sas_phy->id = phy_id;168 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;169 sas_phy->frame_rcvd = &phy->frame_rcvd[0];170 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;171 sas_phy->lldd_phy = phy;172}173 174/**175 * pm8001_free - free hba176 * @pm8001_ha: our hba structure.177 */178static void pm8001_free(struct pm8001_hba_info *pm8001_ha)179{180 int i;181 182 if (!pm8001_ha)183 return;184 185 for (i = 0; i < USI_MAX_MEMCNT; i++) {186 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {187 dma_free_coherent(&pm8001_ha->pdev->dev,188 (pm8001_ha->memoryMap.region[i].total_len +189 pm8001_ha->memoryMap.region[i].alignment),190 pm8001_ha->memoryMap.region[i].virt_ptr,191 pm8001_ha->memoryMap.region[i].phys_addr);192 }193 }194 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);195 flush_workqueue(pm8001_wq);196 bitmap_free(pm8001_ha->rsvd_tags);197 kfree(pm8001_ha);198}199 200/**201 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler202 * @opaque: the passed general host adapter struct203 * Note: pm8001_tasklet is common for pm8001 & pm80xx204 */205static void pm8001_tasklet(unsigned long opaque)206{207 struct isr_param *irq_vector = (struct isr_param *)opaque;208 struct pm8001_hba_info *pm8001_ha = irq_vector->drv_inst;209 210 if (WARN_ON_ONCE(!pm8001_ha))211 return;212 213 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);214}215 216static void pm8001_init_tasklet(struct pm8001_hba_info *pm8001_ha)217{218 int i;219 220 if (!pm8001_use_tasklet)221 return;222 223 /* Tasklet for non msi-x interrupt handler */224 if ((!pm8001_ha->pdev->msix_cap || !pci_msi_enabled()) ||225 (pm8001_ha->chip_id == chip_8001)) {226 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,227 (unsigned long)&(pm8001_ha->irq_vector[0]));228 return;229 }230 for (i = 0; i < PM8001_MAX_MSIX_VEC; i++)231 tasklet_init(&pm8001_ha->tasklet[i], pm8001_tasklet,232 (unsigned long)&(pm8001_ha->irq_vector[i]));233}234 235static void pm8001_kill_tasklet(struct pm8001_hba_info *pm8001_ha)236{237 int i;238 239 if (!pm8001_use_tasklet)240 return;241 242 /* For non-msix and msix interrupts */243 if ((!pm8001_ha->pdev->msix_cap || !pci_msi_enabled()) ||244 (pm8001_ha->chip_id == chip_8001)) {245 tasklet_kill(&pm8001_ha->tasklet[0]);246 return;247 }248 249 for (i = 0; i < PM8001_MAX_MSIX_VEC; i++)250 tasklet_kill(&pm8001_ha->tasklet[i]);251}252 253static irqreturn_t pm8001_handle_irq(struct pm8001_hba_info *pm8001_ha,254 int irq)255{256 if (unlikely(!pm8001_ha))257 return IRQ_NONE;258 259 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))260 return IRQ_NONE;261 262 if (!pm8001_use_tasklet)263 return PM8001_CHIP_DISP->isr(pm8001_ha, irq);264 265 tasklet_schedule(&pm8001_ha->tasklet[irq]);266 return IRQ_HANDLED;267}268 269/**270 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.271 * It obtains the vector number and calls the equivalent bottom272 * half or services directly.273 * @irq: interrupt number274 * @opaque: the passed outbound queue/vector. Host structure is275 * retrieved from the same.276 */277static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)278{279 struct isr_param *irq_vector = (struct isr_param *)opaque;280 struct pm8001_hba_info *pm8001_ha = irq_vector->drv_inst;281 282 return pm8001_handle_irq(pm8001_ha, irq_vector->irq_id);283}284 285/**286 * pm8001_interrupt_handler_intx - main INTx interrupt handler.287 * @irq: interrupt number288 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.289 */290 291static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)292{293 struct sas_ha_struct *sha = dev_id;294 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;295 296 return pm8001_handle_irq(pm8001_ha, 0);297}298 299static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);300static void pm8001_free_irq(struct pm8001_hba_info *pm8001_ha);301 302/**303 * pm8001_alloc - initiate our hba structure and 6 DMAs area.304 * @pm8001_ha: our hba structure.305 * @ent: PCI device ID structure to match on306 */307static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,308 const struct pci_device_id *ent)309{310 int i, count = 0, rc = 0;311 u32 ci_offset, ib_offset, ob_offset, pi_offset;312 struct inbound_queue_table *ibq;313 struct outbound_queue_table *obq;314 315 spin_lock_init(&pm8001_ha->lock);316 spin_lock_init(&pm8001_ha->bitmap_lock);317 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",318 pm8001_ha->chip->n_phy);319 320 /* Request Interrupt */321 rc = pm8001_request_irq(pm8001_ha);322 if (rc)323 goto err_out;324 325 count = pm8001_ha->max_q_num;326 /* Queues are chosen based on the number of cores/msix availability */327 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE;328 ci_offset = pm8001_ha->ci_offset = ib_offset + count;329 ob_offset = pm8001_ha->ob_offset = ci_offset + count;330 pi_offset = pm8001_ha->pi_offset = ob_offset + count;331 pm8001_ha->max_memcnt = pi_offset + count;332 333 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {334 pm8001_phy_init(pm8001_ha, i);335 pm8001_ha->port[i].wide_port_phymap = 0;336 pm8001_ha->port[i].port_attached = 0;337 pm8001_ha->port[i].port_state = 0;338 INIT_LIST_HEAD(&pm8001_ha->port[i].list);339 }340 341 /* MPI Memory region 1 for AAP Event Log for fw */342 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;343 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;344 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;345 pm8001_ha->memoryMap.region[AAP1].alignment = 32;346 347 /* MPI Memory region 2 for IOP Event Log for fw */348 pm8001_ha->memoryMap.region[IOP].num_elements = 1;349 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;350 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;351 pm8001_ha->memoryMap.region[IOP].alignment = 32;352 353 for (i = 0; i < count; i++) {354 ibq = &pm8001_ha->inbnd_q_tbl[i];355 spin_lock_init(&ibq->iq_lock);356 /* MPI Memory region 3 for consumer Index of inbound queues */357 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;358 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;359 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;360 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;361 362 if ((ent->driver_data) != chip_8001) {363 /* MPI Memory region 5 inbound queues */364 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =365 PM8001_MPI_QUEUE;366 pm8001_ha->memoryMap.region[ib_offset+i].element_size367 = 128;368 pm8001_ha->memoryMap.region[ib_offset+i].total_len =369 PM8001_MPI_QUEUE * 128;370 pm8001_ha->memoryMap.region[ib_offset+i].alignment371 = 128;372 } else {373 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =374 PM8001_MPI_QUEUE;375 pm8001_ha->memoryMap.region[ib_offset+i].element_size376 = 64;377 pm8001_ha->memoryMap.region[ib_offset+i].total_len =378 PM8001_MPI_QUEUE * 64;379 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;380 }381 }382 383 for (i = 0; i < count; i++) {384 obq = &pm8001_ha->outbnd_q_tbl[i];385 spin_lock_init(&obq->oq_lock);386 /* MPI Memory region 4 for producer Index of outbound queues */387 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;388 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;389 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;390 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;391 392 if (ent->driver_data != chip_8001) {393 /* MPI Memory region 6 Outbound queues */394 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =395 PM8001_MPI_QUEUE;396 pm8001_ha->memoryMap.region[ob_offset+i].element_size397 = 128;398 pm8001_ha->memoryMap.region[ob_offset+i].total_len =399 PM8001_MPI_QUEUE * 128;400 pm8001_ha->memoryMap.region[ob_offset+i].alignment401 = 128;402 } else {403 /* MPI Memory region 6 Outbound queues */404 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =405 PM8001_MPI_QUEUE;406 pm8001_ha->memoryMap.region[ob_offset+i].element_size407 = 64;408 pm8001_ha->memoryMap.region[ob_offset+i].total_len =409 PM8001_MPI_QUEUE * 64;410 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;411 }412 413 }414 /* Memory region write DMA*/415 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;416 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;417 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;418 419 /* Memory region for fw flash */420 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;421 422 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;423 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;424 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;425 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;426 for (i = 0; i < pm8001_ha->max_memcnt; i++) {427 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];428 429 if (pm8001_mem_alloc(pm8001_ha->pdev,430 ®ion->virt_ptr,431 ®ion->phys_addr,432 ®ion->phys_addr_hi,433 ®ion->phys_addr_lo,434 region->total_len,435 region->alignment) != 0) {436 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);437 goto err_out;438 }439 }440 441 /* Memory region for devices*/442 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES443 * sizeof(struct pm8001_device), GFP_KERNEL);444 if (!pm8001_ha->devices) {445 rc = -ENOMEM;446 goto err_out_nodev;447 }448 for (i = 0; i < PM8001_MAX_DEVICES; i++) {449 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;450 pm8001_ha->devices[i].id = i;451 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;452 atomic_set(&pm8001_ha->devices[i].running_req, 0);453 }454 pm8001_ha->flags = PM8001F_INIT_TIME;455 return 0;456 457err_out_nodev:458 for (i = 0; i < pm8001_ha->max_memcnt; i++) {459 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {460 dma_free_coherent(&pm8001_ha->pdev->dev,461 (pm8001_ha->memoryMap.region[i].total_len +462 pm8001_ha->memoryMap.region[i].alignment),463 pm8001_ha->memoryMap.region[i].virt_ptr,464 pm8001_ha->memoryMap.region[i].phys_addr);465 }466 }467err_out:468 return 1;469}470 471/**472 * pm8001_ioremap - remap the pci high physical address to kernel virtual473 * address so that we can access them.474 * @pm8001_ha: our hba structure.475 */476static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)477{478 u32 bar;479 u32 logicalBar = 0;480 struct pci_dev *pdev;481 482 pdev = pm8001_ha->pdev;483 /* map pci mem (PMC pci base 0-3)*/484 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {485 /*486 ** logical BARs for SPC:487 ** bar 0 and 1 - logical BAR0488 ** bar 2 and 3 - logical BAR1489 ** bar4 - logical BAR2490 ** bar5 - logical BAR3491 ** Skip the appropriate assignments:492 */493 if ((bar == 1) || (bar == 3))494 continue;495 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {496 pm8001_ha->io_mem[logicalBar].membase =497 pci_resource_start(pdev, bar);498 pm8001_ha->io_mem[logicalBar].memsize =499 pci_resource_len(pdev, bar);500 pm8001_ha->io_mem[logicalBar].memvirtaddr =501 ioremap(pm8001_ha->io_mem[logicalBar].membase,502 pm8001_ha->io_mem[logicalBar].memsize);503 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {504 pm8001_dbg(pm8001_ha, INIT,505 "Failed to ioremap bar %d, logicalBar %d",506 bar, logicalBar);507 return -ENOMEM;508 }509 pm8001_dbg(pm8001_ha, INIT,510 "base addr %llx virt_addr=%llx len=%d\n",511 (u64)pm8001_ha->io_mem[logicalBar].membase,512 (u64)(unsigned long)513 pm8001_ha->io_mem[logicalBar].memvirtaddr,514 pm8001_ha->io_mem[logicalBar].memsize);515 } else {516 pm8001_ha->io_mem[logicalBar].membase = 0;517 pm8001_ha->io_mem[logicalBar].memsize = 0;518 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;519 }520 logicalBar++;521 }522 return 0;523}524 525/**526 * pm8001_pci_alloc - initialize our ha card structure527 * @pdev: pci device.528 * @ent: ent529 * @shost: scsi host struct which has been initialized before.530 */531static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,532 const struct pci_device_id *ent,533 struct Scsi_Host *shost)534 535{536 struct pm8001_hba_info *pm8001_ha;537 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);538 539 pm8001_ha = sha->lldd_ha;540 if (!pm8001_ha)541 return NULL;542 543 pm8001_ha->pdev = pdev;544 pm8001_ha->dev = &pdev->dev;545 pm8001_ha->chip_id = ent->driver_data;546 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];547 pm8001_ha->irq = pdev->irq;548 pm8001_ha->sas = sha;549 pm8001_ha->shost = shost;550 pm8001_ha->id = pm8001_id++;551 pm8001_ha->logging_level = logging_level;552 pm8001_ha->non_fatal_count = 0;553 if (link_rate >= 1 && link_rate <= 15)554 pm8001_ha->link_rate = (link_rate << 8);555 else {556 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |557 LINKRATE_60 | LINKRATE_120;558 pm8001_dbg(pm8001_ha, FAIL,559 "Setting link rate to default value\n");560 }561 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);562 /* IOMB size is 128 for 8088/89 controllers */563 if (pm8001_ha->chip_id != chip_8001)564 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;565 else566 pm8001_ha->iomb_size = IOMB_SIZE_SPC;567 568 pm8001_init_tasklet(pm8001_ha);569 570 if (pm8001_ioremap(pm8001_ha))571 goto failed_pci_alloc;572 if (!pm8001_alloc(pm8001_ha, ent))573 return pm8001_ha;574failed_pci_alloc:575 pm8001_free(pm8001_ha);576 return NULL;577}578 579/**580 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit581 * @pdev: pci device.582 */583static int pci_go_44(struct pci_dev *pdev)584{585 int rc;586 587 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));588 if (rc) {589 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));590 if (rc)591 dev_printk(KERN_ERR, &pdev->dev,592 "32-bit DMA enable failed\n");593 }594 return rc;595}596 597/**598 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.599 * @shost: scsi host which has been allocated outside.600 * @chip_info: our ha struct.601 */602static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,603 const struct pm8001_chip_info *chip_info)604{605 int phy_nr, port_nr;606 struct asd_sas_phy **arr_phy;607 struct asd_sas_port **arr_port;608 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);609 610 phy_nr = chip_info->n_phy;611 port_nr = phy_nr;612 memset(sha, 0x00, sizeof(*sha));613 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);614 if (!arr_phy)615 goto exit;616 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);617 if (!arr_port)618 goto exit_free2;619 620 sha->sas_phy = arr_phy;621 sha->sas_port = arr_port;622 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);623 if (!sha->lldd_ha)624 goto exit_free1;625 626 shost->transportt = pm8001_stt;627 shost->max_id = PM8001_MAX_DEVICES;628 shost->unique_id = pm8001_id;629 shost->max_cmd_len = 16;630 return 0;631exit_free1:632 kfree(arr_port);633exit_free2:634 kfree(arr_phy);635exit:636 return -1;637}638 639/**640 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas641 * @shost: scsi host which has been allocated outside642 * @chip_info: our ha struct.643 */644static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,645 const struct pm8001_chip_info *chip_info)646{647 int i = 0;648 struct pm8001_hba_info *pm8001_ha;649 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);650 651 pm8001_ha = sha->lldd_ha;652 for (i = 0; i < chip_info->n_phy; i++) {653 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;654 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;655 sha->sas_phy[i]->sas_addr =656 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;657 }658 sha->sas_ha_name = DRV_NAME;659 sha->dev = pm8001_ha->dev;660 sha->strict_wide_ports = 1;661 sha->sas_addr = &pm8001_ha->sas_addr[0];662 sha->num_phys = chip_info->n_phy;663 sha->shost = shost;664}665 666/**667 * pm8001_init_sas_add - initialize sas address668 * @pm8001_ha: our ha struct.669 *670 * Currently we just set the fixed SAS address to our HBA, for manufacture,671 * it should read from the EEPROM672 */673static int pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)674{675 DECLARE_COMPLETION_ONSTACK(completion);676 struct pm8001_ioctl_payload payload;677 unsigned long time_remaining;678 u8 sas_add[8];679 u16 deviceid;680 int rc;681 u8 i, j;682 683 if (!pm8001_read_wwn) {684 __be64 dev_sas_addr = cpu_to_be64(0x50010c600047f9d0ULL);685 686 for (i = 0; i < pm8001_ha->chip->n_phy; i++)687 memcpy(&pm8001_ha->phy[i].dev_sas_addr, &dev_sas_addr,688 SAS_ADDR_SIZE);689 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,690 SAS_ADDR_SIZE);691 return 0;692 }693 694 /*695 * For new SPC controllers WWN is stored in flash vpd. For SPC/SPCve696 * controllers WWN is stored in EEPROM. And for Older SPC WWN is stored697 * in NVMD.698 */699 if (PM8001_CHIP_DISP->fatal_errors(pm8001_ha)) {700 pm8001_dbg(pm8001_ha, FAIL, "controller is in fatal error state\n");701 return -EIO;702 }703 704 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);705 pm8001_ha->nvmd_completion = &completion;706 707 if (pm8001_ha->chip_id == chip_8001) {708 if (deviceid == 0x8081 || deviceid == 0x0042) {709 payload.minor_function = 4;710 payload.rd_length = 4096;711 } else {712 payload.minor_function = 0;713 payload.rd_length = 128;714 }715 } else if ((pm8001_ha->chip_id == chip_8070 ||716 pm8001_ha->chip_id == chip_8072) &&717 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {718 payload.minor_function = 4;719 payload.rd_length = 4096;720 } else {721 payload.minor_function = 1;722 payload.rd_length = 4096;723 }724 payload.offset = 0;725 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);726 if (!payload.func_specific) {727 pm8001_dbg(pm8001_ha, FAIL, "mem alloc fail\n");728 return -ENOMEM;729 }730 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);731 if (rc) {732 kfree(payload.func_specific);733 pm8001_dbg(pm8001_ha, FAIL, "nvmd failed\n");734 return -EIO;735 }736 time_remaining = wait_for_completion_timeout(&completion,737 msecs_to_jiffies(60*1000)); // 1 min738 if (!time_remaining) {739 kfree(payload.func_specific);740 pm8001_dbg(pm8001_ha, FAIL, "get_nvmd_req timeout\n");741 return -EIO;742 }743 744 745 for (i = 0, j = 0; i <= 7; i++, j++) {746 if (pm8001_ha->chip_id == chip_8001) {747 if (deviceid == 0x8081)748 pm8001_ha->sas_addr[j] =749 payload.func_specific[0x704 + i];750 else if (deviceid == 0x0042)751 pm8001_ha->sas_addr[j] =752 payload.func_specific[0x010 + i];753 } else if ((pm8001_ha->chip_id == chip_8070 ||754 pm8001_ha->chip_id == chip_8072) &&755 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {756 pm8001_ha->sas_addr[j] =757 payload.func_specific[0x010 + i];758 } else759 pm8001_ha->sas_addr[j] =760 payload.func_specific[0x804 + i];761 }762 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);763 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {764 if (i && ((i % 4) == 0))765 sas_add[7] = sas_add[7] + 4;766 memcpy(&pm8001_ha->phy[i].dev_sas_addr,767 sas_add, SAS_ADDR_SIZE);768 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,769 pm8001_ha->phy[i].dev_sas_addr);770 }771 kfree(payload.func_specific);772 773 return 0;774}775 776/*777 * pm8001_get_phy_settings_info : Read phy setting values.778 * @pm8001_ha : our hba.779 */780static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)781{782 DECLARE_COMPLETION_ONSTACK(completion);783 struct pm8001_ioctl_payload payload;784 int rc;785 786 if (!pm8001_read_wwn)787 return 0;788 789 pm8001_ha->nvmd_completion = &completion;790 /* SAS ADDRESS read from flash / EEPROM */791 payload.minor_function = 6;792 payload.offset = 0;793 payload.rd_length = 4096;794 payload.func_specific = kzalloc(4096, GFP_KERNEL);795 if (!payload.func_specific)796 return -ENOMEM;797 /* Read phy setting values from flash */798 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);799 if (rc) {800 kfree(payload.func_specific);801 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");802 return -ENOMEM;803 }804 wait_for_completion(&completion);805 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);806 kfree(payload.func_specific);807 808 return 0;809}810 811struct pm8001_mpi3_phy_pg_trx_config {812 u32 LaneLosCfg;813 u32 LanePgaCfg1;814 u32 LanePisoCfg1;815 u32 LanePisoCfg2;816 u32 LanePisoCfg3;817 u32 LanePisoCfg4;818 u32 LanePisoCfg5;819 u32 LanePisoCfg6;820 u32 LaneBctCtrl;821};822 823/**824 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings825 * @pm8001_ha : our adapter826 * @phycfg : PHY config page to populate827 */828static829void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,830 struct pm8001_mpi3_phy_pg_trx_config *phycfg)831{832 phycfg->LaneLosCfg = 0x00000132;833 phycfg->LanePgaCfg1 = 0x00203949;834 phycfg->LanePisoCfg1 = 0x000000FF;835 phycfg->LanePisoCfg2 = 0xFF000001;836 phycfg->LanePisoCfg3 = 0xE7011300;837 phycfg->LanePisoCfg4 = 0x631C40C0;838 phycfg->LanePisoCfg5 = 0xF8102036;839 phycfg->LanePisoCfg6 = 0xF74A1000;840 phycfg->LaneBctCtrl = 0x00FB33F8;841}842 843/**844 * pm8001_get_external_phy_settings - Retrieves the external PHY settings845 * @pm8001_ha : our adapter846 * @phycfg : PHY config page to populate847 */848static849void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,850 struct pm8001_mpi3_phy_pg_trx_config *phycfg)851{852 phycfg->LaneLosCfg = 0x00000132;853 phycfg->LanePgaCfg1 = 0x00203949;854 phycfg->LanePisoCfg1 = 0x000000FF;855 phycfg->LanePisoCfg2 = 0xFF000001;856 phycfg->LanePisoCfg3 = 0xE7011300;857 phycfg->LanePisoCfg4 = 0x63349140;858 phycfg->LanePisoCfg5 = 0xF8102036;859 phycfg->LanePisoCfg6 = 0xF80D9300;860 phycfg->LaneBctCtrl = 0x00FB33F8;861}862 863/**864 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext865 * @pm8001_ha : our adapter866 * @phymask : The PHY mask867 */868static869void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)870{871 switch (pm8001_ha->pdev->subsystem_device) {872 case 0x0070: /* H1280 - 8 external 0 internal */873 case 0x0072: /* H12F0 - 16 external 0 internal */874 *phymask = 0x0000;875 break;876 877 case 0x0071: /* H1208 - 0 external 8 internal */878 case 0x0073: /* H120F - 0 external 16 internal */879 *phymask = 0xFFFF;880 break;881 882 case 0x0080: /* H1244 - 4 external 4 internal */883 *phymask = 0x00F0;884 break;885 886 case 0x0081: /* H1248 - 4 external 8 internal */887 *phymask = 0x0FF0;888 break;889 890 case 0x0082: /* H1288 - 8 external 8 internal */891 *phymask = 0xFF00;892 break;893 894 default:895 pm8001_dbg(pm8001_ha, INIT,896 "Unknown subsystem device=0x%.04x\n",897 pm8001_ha->pdev->subsystem_device);898 }899}900 901/**902 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings903 * @pm8001_ha : our adapter904 */905static906int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)907{908 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;909 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;910 int phymask = 0;911 int i = 0;912 913 memset(&phycfg_int, 0, sizeof(phycfg_int));914 memset(&phycfg_ext, 0, sizeof(phycfg_ext));915 916 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);917 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);918 pm8001_get_phy_mask(pm8001_ha, &phymask);919 920 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {921 if (phymask & (1 << i)) {/* Internal PHY */922 pm8001_set_phy_profile_single(pm8001_ha, i,923 sizeof(phycfg_int) / sizeof(u32),924 (u32 *)&phycfg_int);925 926 } else { /* External PHY */927 pm8001_set_phy_profile_single(pm8001_ha, i,928 sizeof(phycfg_ext) / sizeof(u32),929 (u32 *)&phycfg_ext);930 }931 }932 933 return 0;934}935 936/**937 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.938 * @pm8001_ha : our hba.939 */940static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)941{942 switch (pm8001_ha->pdev->subsystem_vendor) {943 case PCI_VENDOR_ID_ATTO:944 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */945 return 0;946 else947 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);948 949 case PCI_VENDOR_ID_ADAPTEC2:950 case 0:951 return 0;952 953 default:954 return pm8001_get_phy_settings_info(pm8001_ha);955 }956}957 958/**959 * pm8001_setup_msix - enable MSI-X interrupt960 * @pm8001_ha: our ha struct.961 */962static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)963{964 unsigned int allocated_irq_vectors;965 int rc;966 967 /* SPCv controllers supports 64 msi-x */968 if (pm8001_ha->chip_id == chip_8001) {969 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1,970 PCI_IRQ_MSIX);971 } else {972 /*973 * Queue index #0 is used always for housekeeping, so don't974 * include in the affinity spreading.975 */976 struct irq_affinity desc = {977 .pre_vectors = 1,978 };979 rc = pci_alloc_irq_vectors_affinity(980 pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC,981 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc);982 }983 984 allocated_irq_vectors = rc;985 if (rc < 0)986 return rc;987 988 /* Assigns the number of interrupts */989 pm8001_ha->number_of_intr = allocated_irq_vectors;990 991 /* Maximum queue number updating in HBA structure */992 pm8001_ha->max_q_num = allocated_irq_vectors;993 994 pm8001_dbg(pm8001_ha, INIT,995 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",996 rc, pm8001_ha->number_of_intr);997 return 0;998}999 1000static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)1001{1002 u32 i = 0, j = 0;1003 int flag = 0, rc = 0;1004 int nr_irqs = pm8001_ha->number_of_intr;1005 1006 if (pm8001_ha->chip_id != chip_8001)1007 flag &= ~IRQF_SHARED;1008 1009 pm8001_dbg(pm8001_ha, INIT,1010 "pci_enable_msix request number of intr %d\n",1011 pm8001_ha->number_of_intr);1012 1013 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))1014 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);1015 1016 for (i = 0; i < nr_irqs; i++) {1017 snprintf(pm8001_ha->intr_drvname[i],1018 sizeof(pm8001_ha->intr_drvname[0]),1019 "%s-%d", pm8001_ha->name, i);1020 pm8001_ha->irq_vector[i].irq_id = i;1021 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;1022 1023 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),1024 pm8001_interrupt_handler_msix, flag,1025 pm8001_ha->intr_drvname[i],1026 &(pm8001_ha->irq_vector[i]));1027 if (rc) {1028 for (j = 0; j < i; j++) {1029 free_irq(pci_irq_vector(pm8001_ha->pdev, i),1030 &(pm8001_ha->irq_vector[i]));1031 }1032 pci_free_irq_vectors(pm8001_ha->pdev);1033 break;1034 }1035 }1036 1037 return rc;1038}1039 1040/**1041 * pm8001_request_irq - register interrupt1042 * @pm8001_ha: our ha struct.1043 */1044static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)1045{1046 struct pci_dev *pdev = pm8001_ha->pdev;1047 int rc;1048 1049 if (pm8001_use_msix && pci_find_capability(pdev, PCI_CAP_ID_MSIX)) {1050 rc = pm8001_setup_msix(pm8001_ha);1051 if (rc) {1052 pm8001_dbg(pm8001_ha, FAIL,1053 "pm8001_setup_irq failed [ret: %d]\n", rc);1054 return rc;1055 }1056 1057 if (!pdev->msix_cap || !pci_msi_enabled())1058 goto use_intx;1059 1060 rc = pm8001_request_msix(pm8001_ha);1061 if (rc)1062 return rc;1063 1064 pm8001_ha->use_msix = true;1065 1066 return 0;1067 }1068 1069use_intx:1070 /* Initialize the INT-X interrupt */1071 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");1072 pm8001_ha->use_msix = false;1073 pm8001_ha->irq_vector[0].irq_id = 0;1074 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;1075 1076 return request_irq(pdev->irq, pm8001_interrupt_handler_intx,1077 IRQF_SHARED, pm8001_ha->name,1078 SHOST_TO_SAS_HA(pm8001_ha->shost));1079}1080 1081static void pm8001_free_irq(struct pm8001_hba_info *pm8001_ha)1082{1083 struct pci_dev *pdev = pm8001_ha->pdev;1084 int i;1085 1086 if (pm8001_ha->use_msix) {1087 for (i = 0; i < pm8001_ha->number_of_intr; i++)1088 synchronize_irq(pci_irq_vector(pdev, i));1089 1090 for (i = 0; i < pm8001_ha->number_of_intr; i++)1091 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);1092 1093 pci_free_irq_vectors(pdev);1094 return;1095 }1096 1097 /* INT-X */1098 free_irq(pm8001_ha->irq, pm8001_ha->sas);1099}1100 1101/**1102 * pm8001_pci_probe - probe supported device1103 * @pdev: pci device which kernel has been prepared for.1104 * @ent: pci device id1105 *1106 * This function is the main initialization function, when register a new1107 * pci driver it is invoked, all struct and hardware initialization should be1108 * done here, also, register interrupt.1109 */1110static int pm8001_pci_probe(struct pci_dev *pdev,1111 const struct pci_device_id *ent)1112{1113 unsigned int rc;1114 u32 pci_reg;1115 u8 i = 0;1116 struct pm8001_hba_info *pm8001_ha;1117 struct Scsi_Host *shost = NULL;1118 const struct pm8001_chip_info *chip;1119 struct sas_ha_struct *sha;1120 1121 dev_printk(KERN_INFO, &pdev->dev,1122 "pm80xx: driver version %s\n", DRV_VERSION);1123 rc = pci_enable_device(pdev);1124 if (rc)1125 goto err_out_enable;1126 pci_set_master(pdev);1127 /*1128 * Enable pci slot busmaster by setting pci command register.1129 * This is required by FW for Cyclone card.1130 */1131 1132 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);1133 pci_reg |= 0x157;1134 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);1135 rc = pci_request_regions(pdev, DRV_NAME);1136 if (rc)1137 goto err_out_disable;1138 rc = pci_go_44(pdev);1139 if (rc)1140 goto err_out_regions;1141 1142 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));1143 if (!shost) {1144 rc = -ENOMEM;1145 goto err_out_regions;1146 }1147 chip = &pm8001_chips[ent->driver_data];1148 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);1149 if (!sha) {1150 rc = -ENOMEM;1151 goto err_out_free_host;1152 }1153 SHOST_TO_SAS_HA(shost) = sha;1154 1155 rc = pm8001_prep_sas_ha_init(shost, chip);1156 if (rc) {1157 rc = -ENOMEM;1158 goto err_out_free;1159 }1160 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));1161 /* ent->driver variable is used to differentiate between controllers */1162 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);1163 if (!pm8001_ha) {1164 rc = -ENOMEM;1165 goto err_out_free;1166 }1167 1168 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);1169 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);1170 if (rc) {1171 pm8001_dbg(pm8001_ha, FAIL,1172 "chip_init failed [ret: %d]\n", rc);1173 goto err_out_ha_free;1174 }1175 1176 rc = pm8001_init_ccb_tag(pm8001_ha);1177 if (rc)1178 goto err_out_enable;1179 1180 1181 PM8001_CHIP_DISP->chip_post_init(pm8001_ha);1182 1183 if (pm8001_ha->number_of_intr > 1) {1184 shost->nr_hw_queues = pm8001_ha->number_of_intr - 1;1185 /*1186 * For now, ensure we're not sent too many commands by setting1187 * host_tagset. This is also required if we start using request1188 * tag.1189 */1190 shost->host_tagset = 1;1191 }1192 1193 rc = scsi_add_host(shost, &pdev->dev);1194 if (rc)1195 goto err_out_ha_free;1196 1197 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);1198 if (pm8001_ha->chip_id != chip_8001) {1199 for (i = 1; i < pm8001_ha->number_of_intr; i++)1200 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);1201 /* setup thermal configuration. */1202 pm80xx_set_thermal_config(pm8001_ha);1203 }1204 1205 rc = pm8001_init_sas_add(pm8001_ha);1206 if (rc)1207 goto err_out_shost;1208 /* phy setting support for motherboard controller */1209 rc = pm8001_configure_phy_settings(pm8001_ha);1210 if (rc)1211 goto err_out_shost;1212 1213 pm8001_post_sas_ha_init(shost, chip);1214 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));1215 if (rc) {1216 pm8001_dbg(pm8001_ha, FAIL,1217 "sas_register_ha failed [ret: %d]\n", rc);1218 goto err_out_shost;1219 }1220 list_add_tail(&pm8001_ha->list, &hba_list);1221 pm8001_ha->flags = PM8001F_RUN_TIME;1222 scsi_scan_host(pm8001_ha->shost);1223 return 0;1224 1225err_out_shost:1226 scsi_remove_host(pm8001_ha->shost);1227err_out_ha_free:1228 pm8001_free(pm8001_ha);1229err_out_free:1230 kfree(sha);1231err_out_free_host:1232 scsi_host_put(shost);1233err_out_regions:1234 pci_release_regions(pdev);1235err_out_disable:1236 pci_disable_device(pdev);1237err_out_enable:1238 return rc;1239}1240 1241/**1242 * pm8001_init_ccb_tag - allocate memory to CCB and tag.1243 * @pm8001_ha: our hba card information.1244 */1245static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha)1246{1247 struct Scsi_Host *shost = pm8001_ha->shost;1248 struct device *dev = pm8001_ha->dev;1249 u32 max_out_io, ccb_count;1250 int i;1251 1252 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;1253 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);1254 1255 shost->can_queue = ccb_count - PM8001_RESERVE_SLOT;1256 1257 pm8001_ha->rsvd_tags = bitmap_zalloc(PM8001_RESERVE_SLOT, GFP_KERNEL);1258 if (!pm8001_ha->rsvd_tags)1259 goto err_out;1260 1261 /* Memory region for ccb_info*/1262 pm8001_ha->ccb_count = ccb_count;1263 pm8001_ha->ccb_info =1264 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);1265 if (!pm8001_ha->ccb_info) {1266 pm8001_dbg(pm8001_ha, FAIL,1267 "Unable to allocate memory for ccb\n");1268 goto err_out_noccb;1269 }1270 for (i = 0; i < ccb_count; i++) {1271 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev,1272 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,1273 &pm8001_ha->ccb_info[i].ccb_dma_handle,1274 GFP_KERNEL);1275 if (!pm8001_ha->ccb_info[i].buf_prd) {1276 pm8001_dbg(pm8001_ha, FAIL,1277 "ccb prd memory allocation error\n");1278 goto err_out;1279 }1280 pm8001_ha->ccb_info[i].task = NULL;1281 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;1282 pm8001_ha->ccb_info[i].device = NULL;1283 }1284 1285 return 0;1286 1287err_out_noccb:1288 kfree(pm8001_ha->devices);1289err_out:1290 return -ENOMEM;1291}1292 1293static void pm8001_pci_remove(struct pci_dev *pdev)1294{1295 struct sas_ha_struct *sha = pci_get_drvdata(pdev);1296 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;1297 int i;1298 1299 sas_unregister_ha(sha);1300 sas_remove_host(pm8001_ha->shost);1301 list_del(&pm8001_ha->list);1302 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);1303 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);1304 1305 pm8001_free_irq(pm8001_ha);1306 pm8001_kill_tasklet(pm8001_ha);1307 scsi_host_put(pm8001_ha->shost);1308 1309 for (i = 0; i < pm8001_ha->ccb_count; i++) {1310 dma_free_coherent(&pm8001_ha->pdev->dev,1311 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,1312 pm8001_ha->ccb_info[i].buf_prd,1313 pm8001_ha->ccb_info[i].ccb_dma_handle);1314 }1315 kfree(pm8001_ha->ccb_info);1316 kfree(pm8001_ha->devices);1317 1318 pm8001_free(pm8001_ha);1319 kfree(sha->sas_phy);1320 kfree(sha->sas_port);1321 kfree(sha);1322 pci_release_regions(pdev);1323 pci_disable_device(pdev);1324}1325 1326/**1327 * pm8001_pci_suspend - power management suspend main entry point1328 * @dev: Device struct1329 *1330 * Return: 0 on success, anything else on error.1331 */1332static int __maybe_unused pm8001_pci_suspend(struct device *dev)1333{1334 struct pci_dev *pdev = to_pci_dev(dev);1335 struct sas_ha_struct *sha = pci_get_drvdata(pdev);1336 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;1337 1338 sas_suspend_ha(sha);1339 flush_workqueue(pm8001_wq);1340 scsi_block_requests(pm8001_ha->shost);1341 if (!pdev->pm_cap) {1342 dev_err(dev, " PCI PM not supported\n");1343 return -ENODEV;1344 }1345 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);1346 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);1347 1348 pm8001_free_irq(pm8001_ha);1349 pm8001_kill_tasklet(pm8001_ha);1350 1351 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "1352 "suspended state\n", pdev,1353 pm8001_ha->name);1354 return 0;1355}1356 1357/**1358 * pm8001_pci_resume - power management resume main entry point1359 * @dev: Device struct1360 *1361 * Return: 0 on success, anything else on error.1362 */1363static int __maybe_unused pm8001_pci_resume(struct device *dev)1364{1365 struct pci_dev *pdev = to_pci_dev(dev);1366 struct sas_ha_struct *sha = pci_get_drvdata(pdev);1367 struct pm8001_hba_info *pm8001_ha;1368 int rc;1369 u8 i = 0;1370 DECLARE_COMPLETION_ONSTACK(completion);1371 1372 pm8001_ha = sha->lldd_ha;1373 1374 pm8001_info(pm8001_ha,1375 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",1376 pdev, pm8001_ha->name, pdev->current_state);1377 1378 rc = pci_go_44(pdev);1379 if (rc)1380 goto err_out_disable;1381 sas_prep_resume_ha(sha);1382 /* chip soft rst only for spc */1383 if (pm8001_ha->chip_id == chip_8001) {1384 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);1385 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");1386 }1387 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);1388 if (rc)1389 goto err_out_disable;1390 1391 /* disable all the interrupt bits */1392 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);1393 1394 rc = pm8001_request_irq(pm8001_ha);1395 if (rc)1396 goto err_out_disable;1397 1398 pm8001_init_tasklet(pm8001_ha);1399 1400 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);1401 if (pm8001_ha->chip_id != chip_8001) {1402 for (i = 1; i < pm8001_ha->number_of_intr; i++)1403 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);1404 }1405 1406 /* Chip documentation for the 8070 and 8072 SPCv */1407 /* states that a 500ms minimum delay is required */1408 /* before issuing commands. Otherwise, the firmware */1409 /* will enter an unrecoverable state. */1410 1411 if (pm8001_ha->chip_id == chip_8070 ||1412 pm8001_ha->chip_id == chip_8072) {1413 mdelay(500);1414 }1415 1416 /* Spin up the PHYs */1417 1418 pm8001_ha->flags = PM8001F_RUN_TIME;1419 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {1420 pm8001_ha->phy[i].enable_completion = &completion;1421 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);1422 wait_for_completion(&completion);1423 }1424 sas_resume_ha(sha);1425 return 0;1426 1427err_out_disable:1428 scsi_remove_host(pm8001_ha->shost);1429 1430 return rc;1431}1432 1433/* update of pci device, vendor id and driver data with1434 * unique value for each of the controller1435 */1436static struct pci_device_id pm8001_pci_table[] = {1437 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },1438 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },1439 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },1440 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },1441 /* Support for SPC/SPCv/SPCve controllers */1442 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },1443 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },1444 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },1445 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },1446 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },1447 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },1448 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },1449 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },1450 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },1451 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },1452 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },1453 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },1454 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },1455 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },1456 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },1457 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,1458 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },1459 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,1460 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },1461 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,1462 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },1463 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,1464 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },1465 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,1466 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },1467 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,1468 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },1469 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,1470 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },1471 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,1472 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },1473 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,1474 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },1475 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,1476 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },1477 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,1478 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },1479 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,1480 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },1481 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,1482 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },1483 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,1484 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },1485 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,1486 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },1487 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,1488 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },1489 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,1490 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },1491 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,1492 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },1493 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,1494 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },1495 { PCI_VENDOR_ID_ATTO, 0x8070,1496 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },1497 { PCI_VENDOR_ID_ATTO, 0x8070,1498 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },1499 { PCI_VENDOR_ID_ATTO, 0x8072,1500 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },1501 { PCI_VENDOR_ID_ATTO, 0x8072,1502 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },1503 { PCI_VENDOR_ID_ATTO, 0x8070,1504 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },1505 { PCI_VENDOR_ID_ATTO, 0x8072,1506 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },1507 { PCI_VENDOR_ID_ATTO, 0x8072,1508 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },1509 {} /* terminate list */1510};1511 1512static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,1513 pm8001_pci_suspend,1514 pm8001_pci_resume);1515 1516static struct pci_driver pm8001_pci_driver = {1517 .name = DRV_NAME,1518 .id_table = pm8001_pci_table,1519 .probe = pm8001_pci_probe,1520 .remove = pm8001_pci_remove,1521 .driver.pm = &pm8001_pci_pm_ops,1522};1523 1524/**1525 * pm8001_init - initialize scsi transport template1526 */1527static int __init pm8001_init(void)1528{1529 int rc = -ENOMEM;1530 1531 if (pm8001_use_tasklet && !pm8001_use_msix)1532 pm8001_use_tasklet = false;1533 1534 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);1535 if (!pm8001_wq)1536 goto err;1537 1538 pm8001_id = 0;1539 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);1540 if (!pm8001_stt)1541 goto err_wq;1542 rc = pci_register_driver(&pm8001_pci_driver);1543 if (rc)1544 goto err_tp;1545 return 0;1546 1547err_tp:1548 sas_release_transport(pm8001_stt);1549err_wq:1550 destroy_workqueue(pm8001_wq);1551err:1552 return rc;1553}1554 1555static void __exit pm8001_exit(void)1556{1557 pci_unregister_driver(&pm8001_pci_driver);1558 sas_release_transport(pm8001_stt);1559 destroy_workqueue(pm8001_wq);1560}1561 1562module_init(pm8001_init);1563module_exit(pm8001_exit);1564 1565MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");1566MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");1567MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");1568MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");1569MODULE_DESCRIPTION(1570 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "1571 "SAS/SATA controller driver");1572MODULE_VERSION(DRV_VERSION);1573MODULE_LICENSE("GPL");1574MODULE_DEVICE_TABLE(pci, pm8001_pci_table);1575 1576