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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * QLogic Fibre Channel HBA Driver4 * Copyright (c) 2003-2014 QLogic Corporation5 */6#ifndef __QLA_BSG_H7#define __QLA_BSG_H8 9/* BSG Vendor specific commands */10#define QL_VND_LOOPBACK 0x0111#define QL_VND_A84_RESET 0x0212#define QL_VND_A84_UPDATE_FW 0x0313#define QL_VND_A84_MGMT_CMD 0x0414#define QL_VND_IIDMA 0x0515#define QL_VND_FCP_PRIO_CFG_CMD 0x0616#define QL_VND_READ_FLASH 0x0717#define QL_VND_UPDATE_FLASH 0x0818#define QL_VND_SET_FRU_VERSION 0x0B19#define QL_VND_READ_FRU_STATUS 0x0C20#define QL_VND_WRITE_FRU_STATUS 0x0D21#define QL_VND_DIAG_IO_CMD 0x0A22#define QL_VND_WRITE_I2C 0x1023#define QL_VND_READ_I2C 0x1124#define QL_VND_FX00_MGMT_CMD 0x1225#define QL_VND_SERDES_OP 0x1326#define QL_VND_SERDES_OP_EX 0x1427#define QL_VND_GET_FLASH_UPDATE_CAPS 0x1528#define QL_VND_SET_FLASH_UPDATE_CAPS 0x1629#define QL_VND_GET_BBCR_DATA 0x1730#define QL_VND_GET_PRIV_STATS 0x1831#define QL_VND_DPORT_DIAGNOSTICS 0x1932#define QL_VND_GET_PRIV_STATS_EX 0x1A33#define QL_VND_SS_GET_FLASH_IMAGE_STATUS 0x1E34#define QL_VND_EDIF_MGMT 0X1F35#define QL_VND_MANAGE_HOST_STATS 0x2336#define QL_VND_GET_HOST_STATS 0x2437#define QL_VND_GET_TGT_STATS 0x2538#define QL_VND_MANAGE_HOST_PORT 0x2639#define QL_VND_MBX_PASSTHRU 0x2B40#define QL_VND_DPORT_DIAGNOSTICS_V2 0x2C41 42/* BSG Vendor specific subcode returns */43#define EXT_STATUS_OK 044#define EXT_STATUS_ERR 145#define EXT_STATUS_BUSY 246#define EXT_STATUS_INVALID_PARAM 647#define EXT_STATUS_DATA_OVERRUN 748#define EXT_STATUS_DATA_UNDERRUN 849#define EXT_STATUS_MAILBOX 1150#define EXT_STATUS_BUFFER_TOO_SMALL 1651#define EXT_STATUS_NO_MEMORY 1752#define EXT_STATUS_DEVICE_OFFLINE 2253 54/*55 * To support bidirectional iocb56 * BSG Vendor specific returns57 */58#define EXT_STATUS_NOT_SUPPORTED 2759#define EXT_STATUS_INVALID_CFG 2860#define EXT_STATUS_DMA_ERR 2961#define EXT_STATUS_TIMEOUT 3062#define EXT_STATUS_THREAD_FAILED 3163#define EXT_STATUS_DATA_CMP_FAILED 3264#define EXT_STATUS_DPORT_DIAG_ERR 4065#define EXT_STATUS_DPORT_DIAG_IN_PROCESS 4166#define EXT_STATUS_DPORT_DIAG_NOT_RUNNING 4267 68/* BSG definations for interpreting CommandSent field */69#define INT_DEF_LB_LOOPBACK_CMD 070#define INT_DEF_LB_ECHO_CMD 171 72/* Loopback related definations */73#define INTERNAL_LOOPBACK 0xF174#define EXTERNAL_LOOPBACK 0xF275#define ENABLE_INTERNAL_LOOPBACK 0x0276#define ENABLE_EXTERNAL_LOOPBACK 0x0477#define INTERNAL_LOOPBACK_MASK 0x000E78#define MAX_ELS_FRAME_PAYLOAD 25279#define ELS_OPCODE_BYTE 0x1080 81/* BSG Vendor specific definations */82#define A84_ISSUE_WRITE_TYPE_CMD 083#define A84_ISSUE_READ_TYPE_CMD 184#define A84_CLEANUP_CMD 285#define A84_ISSUE_RESET_OP_FW 386#define A84_ISSUE_RESET_DIAG_FW 487#define A84_ISSUE_UPDATE_OPFW_CMD 588#define A84_ISSUE_UPDATE_DIAGFW_CMD 689 90struct qla84_mgmt_param {91 union {92 struct {93 uint32_t start_addr;94 } mem; /* for QLA84_MGMT_READ/WRITE_MEM */95 struct {96 uint32_t id;97#define QLA84_MGMT_CONFIG_ID_UIF 198#define QLA84_MGMT_CONFIG_ID_FCOE_COS 299#define QLA84_MGMT_CONFIG_ID_PAUSE 3100#define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4101 102 uint32_t param0;103 uint32_t param1;104 } config; /* for QLA84_MGMT_CHNG_CONFIG */105 106 struct {107 uint32_t type;108#define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */109#define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */110#define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */111#define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */112#define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */113#define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */114#define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */115 116 uint32_t context;117/*118* context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA119*/120#define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0121#define IC_LOG_DATA_LOG_ID_LEARN_LOG 1122#define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2123#define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3124#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4125#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5126#define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6127#define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7128#define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8129#define IC_LOG_DATA_LOG_ID_DCX_LOG 9130 131/*132* context definitions for QLA84_MGMT_INFO_PORT_STAT133*/134#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0135#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1136#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2137#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3138#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4139#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5140 141 142/*143* context definitions for QLA84_MGMT_INFO_LIF_STAT144*/145#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0146#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1147#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2148#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3149#define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6150 151 } info; /* for QLA84_MGMT_GET_INFO */152 } u;153};154 155struct qla84_msg_mgmt {156 uint16_t cmd;157#define QLA84_MGMT_READ_MEM 0x00158#define QLA84_MGMT_WRITE_MEM 0x01159#define QLA84_MGMT_CHNG_CONFIG 0x02160#define QLA84_MGMT_GET_INFO 0x03161 uint16_t rsrvd;162 struct qla84_mgmt_param mgmtp;/* parameters for cmd */163 uint32_t len; /* bytes in payload following this struct */164 uint8_t payload[]; /* payload for cmd */165};166 167struct qla_bsg_a84_mgmt {168 struct qla84_msg_mgmt mgmt;169} __attribute__ ((packed));170 171struct qla_scsi_addr {172 uint16_t bus;173 uint16_t target;174} __attribute__ ((packed));175 176struct qla_ext_dest_addr {177 union {178 uint8_t wwnn[8];179 uint8_t wwpn[8];180 uint8_t id[4];181 struct qla_scsi_addr scsi_addr;182 } dest_addr;183 uint16_t dest_type;184#define EXT_DEF_TYPE_WWPN 2185 uint16_t lun;186 uint16_t padding[2];187} __attribute__ ((packed));188 189struct qla_port_param {190 struct qla_ext_dest_addr fc_scsi_addr;191 uint16_t mode;192 uint16_t speed;193} __attribute__ ((packed));194 195struct qla_mbx_passthru {196 uint16_t reserved1[2];197 uint16_t mbx_in[32];198 uint16_t mbx_out[32];199 uint32_t reserved2[16];200} __packed;201 202/* FRU VPD */203 204#define MAX_FRU_SIZE 36205 206struct qla_field_address {207 uint16_t offset;208 uint16_t device;209 uint16_t option;210} __packed;211 212struct qla_field_info {213 uint8_t version[MAX_FRU_SIZE];214} __packed;215 216struct qla_image_version {217 struct qla_field_address field_address;218 struct qla_field_info field_info;219} __packed;220 221struct qla_image_version_list {222 uint32_t count;223 struct qla_image_version version[];224} __packed;225 226struct qla_status_reg {227 struct qla_field_address field_address;228 uint8_t status_reg;229 uint8_t reserved[7];230} __packed;231 232struct qla_i2c_access {233 uint16_t device;234 uint16_t offset;235 uint16_t option;236 uint16_t length;237 uint8_t buffer[0x40];238} __packed;239 240/* 26xx serdes register interface */241 242/* serdes reg commands */243#define INT_SC_SERDES_READ_REG 1244#define INT_SC_SERDES_WRITE_REG 2245 246struct qla_serdes_reg {247 uint16_t cmd;248 uint16_t addr;249 uint16_t val;250} __packed;251 252struct qla_serdes_reg_ex {253 uint16_t cmd;254 uint32_t addr;255 uint32_t val;256} __packed;257 258struct qla_flash_update_caps {259 uint64_t capabilities;260 uint32_t outage_duration;261 uint8_t reserved[20];262} __packed;263 264/* BB_CR Status */265#define QLA_BBCR_STATUS_DISABLED 0266#define QLA_BBCR_STATUS_ENABLED 1267#define QLA_BBCR_STATUS_UNKNOWN 2268 269/* BB_CR State */270#define QLA_BBCR_STATE_OFFLINE 0271#define QLA_BBCR_STATE_ONLINE 1272 273/* BB_CR Offline Reason Code */274#define QLA_BBCR_REASON_PORT_SPEED 1275#define QLA_BBCR_REASON_PEER_PORT 2276#define QLA_BBCR_REASON_SWITCH 3277#define QLA_BBCR_REASON_LOGIN_REJECT 4278 279struct qla_bbcr_data {280 uint8_t status; /* 1 - enabled, 0 - Disabled */281 uint8_t state; /* 1 - online, 0 - offline */282 uint8_t configured_bbscn; /* 0-15 */283 uint8_t negotiated_bbscn; /* 0-15 */284 uint8_t offline_reason_code;285 uint16_t mbx1; /* Port state */286 uint8_t reserved[9];287} __packed;288 289struct qla_dport_diag {290 uint16_t options;291 uint32_t buf[16];292 uint8_t unused[62];293} __packed;294 295#define QLA_GET_DPORT_RESULT_V2 0 /* Get Result */296#define QLA_RESTART_DPORT_TEST_V2 1 /* Restart test */297#define QLA_START_DPORT_TEST_V2 2 /* Start test */298struct qla_dport_diag_v2 {299 uint16_t options;300 uint16_t mbx1;301 uint16_t mbx2;302 uint8_t unused[58];303 uint8_t buf[1024]; /* Test Result */304} __packed;305 306/* D_Port options */307#define QLA_DPORT_RESULT 0x0308#define QLA_DPORT_START 0x2309 310/* active images in flash */311struct qla_active_regions {312 uint8_t global_image;313 uint8_t board_config;314 uint8_t vpd_nvram;315 uint8_t npiv_config_0_1;316 uint8_t npiv_config_2_3;317 uint8_t nvme_params;318 uint8_t reserved[31];319} __packed;320 321#include "qla_edif_bsg.h"322 323#endif324