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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * QLogic iSCSI HBA Driver4 * Copyright (c) 2003-2013 QLogic Corporation5 */6#ifndef __QLA_NX_H7#define __QLA_NX_H8 9/*10 * Following are the states of the Phantom. Phantom will set them and11 * Host will read to check if the fields are correct.12*/13#define PHAN_INITIALIZE_FAILED 0xffff14#define PHAN_INITIALIZE_COMPLETE 0xff0115 16/* Host writes the following to notify that it has done the init-handshake */17#define PHAN_INITIALIZE_ACK 0xf00f18#define PHAN_PEG_RCV_INITIALIZED 0xff0119 20/*CRB_RELATED*/21#define QLA82XX_CRB_BASE (QLA82XX_CAM_RAM(0x200))22#define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X))23#define CRB_CMDPEG_STATE QLA82XX_REG(0x50)24#define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)25#define CRB_DMA_SHIFT QLA82XX_REG(0xcc)26#define CRB_TEMP_STATE QLA82XX_REG(0x1b4)27#define CRB_CMDPEG_CHECK_RETRY_COUNT 6028#define CRB_CMDPEG_CHECK_DELAY 50029 30#define qla82xx_get_temp_val(x) ((x) >> 16)31#define qla82xx_get_temp_state(x) ((x) & 0xffff)32#define qla82xx_encode_temp(val, state) (((val) << 16) | (state))33 34/*35 * Temperature control.36 */37enum {38 QLA82XX_TEMP_NORMAL = 0x1, /* Normal operating range */39 QLA82XX_TEMP_WARN, /* Sound alert, temperature getting high */40 QLA82XX_TEMP_PANIC /* Fatal error, hardware has shut down. */41};42 43#define CRB_NIU_XG_PAUSE_CTL_P0 0x144#define CRB_NIU_XG_PAUSE_CTL_P1 0x845 46#define QLA82XX_HW_H0_CH_HUB_ADR 0x0547#define QLA82XX_HW_H1_CH_HUB_ADR 0x0E48#define QLA82XX_HW_H2_CH_HUB_ADR 0x0349#define QLA82XX_HW_H3_CH_HUB_ADR 0x0150#define QLA82XX_HW_H4_CH_HUB_ADR 0x0651#define QLA82XX_HW_H5_CH_HUB_ADR 0x0752#define QLA82XX_HW_H6_CH_HUB_ADR 0x0853 54/* Hub 0 */55#define QLA82XX_HW_MN_CRB_AGT_ADR 0x1556#define QLA82XX_HW_MS_CRB_AGT_ADR 0x2557 58/* Hub 1 */59#define QLA82XX_HW_PS_CRB_AGT_ADR 0x7360#define QLA82XX_HW_QMS_CRB_AGT_ADR 0x0061#define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b62#define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x0163#define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x0264#define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x0365#define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x0466#define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x5867#define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x5968#define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a69#define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a70#define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c71#define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f72#define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x1273#define QLA82XX_HW_SMB_CRB_AGT_ADR 0x1874 75/* Hub 2 */76#define QLA82XX_HW_NIU_CRB_AGT_ADR 0x3177#define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x1978#define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x2979 80#define QLA82XX_HW_SN_CRB_AGT_ADR 0x1081#define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x2082#define QLA82XX_HW_LPC_CRB_AGT_ADR 0x2283#define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x2184#define QLA82XX_HW_QM_CRB_AGT_ADR 0x6685#define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x6086#define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x6187#define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x6288#define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x6389#define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x0990#define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d91#define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e92#define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x1193 94/* Hub 3 */95#define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A96#define QLA82XX_HW_SRE_CRB_AGT_ADR 0x5097#define QLA82XX_HW_EG_CRB_AGT_ADR 0x5198#define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x0899 100/* Hub 4 */101#define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40102#define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41103#define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42104#define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43105#define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44106#define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45107#define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46108#define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47109#define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48110#define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49111#define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a112#define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b113 114/* Hub 5 */115#define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40116#define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41117#define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42118#define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43119 120#define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44121#define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45122#define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46123 124/* Hub 6 */125#define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46126#define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47127#define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48128#define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49129#define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16130#define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17131#define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05132#define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06133#define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07134 135/* This field defines PCI/X adr [25:20] of agents on the CRB */136/* */137#define QLA82XX_HW_PX_MAP_CRB_PH 0138#define QLA82XX_HW_PX_MAP_CRB_PS 1139#define QLA82XX_HW_PX_MAP_CRB_MN 2140#define QLA82XX_HW_PX_MAP_CRB_MS 3141#define QLA82XX_HW_PX_MAP_CRB_SRE 5142#define QLA82XX_HW_PX_MAP_CRB_NIU 6143#define QLA82XX_HW_PX_MAP_CRB_QMN 7144#define QLA82XX_HW_PX_MAP_CRB_SQN0 8145#define QLA82XX_HW_PX_MAP_CRB_SQN1 9146#define QLA82XX_HW_PX_MAP_CRB_SQN2 10147#define QLA82XX_HW_PX_MAP_CRB_SQN3 11148#define QLA82XX_HW_PX_MAP_CRB_QMS 12149#define QLA82XX_HW_PX_MAP_CRB_SQS0 13150#define QLA82XX_HW_PX_MAP_CRB_SQS1 14151#define QLA82XX_HW_PX_MAP_CRB_SQS2 15152#define QLA82XX_HW_PX_MAP_CRB_SQS3 16153#define QLA82XX_HW_PX_MAP_CRB_PGN0 17154#define QLA82XX_HW_PX_MAP_CRB_PGN1 18155#define QLA82XX_HW_PX_MAP_CRB_PGN2 19156#define QLA82XX_HW_PX_MAP_CRB_PGN3 20157#define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2158#define QLA82XX_HW_PX_MAP_CRB_PGND 21159#define QLA82XX_HW_PX_MAP_CRB_PGNI 22160#define QLA82XX_HW_PX_MAP_CRB_PGS0 23161#define QLA82XX_HW_PX_MAP_CRB_PGS1 24162#define QLA82XX_HW_PX_MAP_CRB_PGS2 25163#define QLA82XX_HW_PX_MAP_CRB_PGS3 26164#define QLA82XX_HW_PX_MAP_CRB_PGSD 27165#define QLA82XX_HW_PX_MAP_CRB_PGSI 28166#define QLA82XX_HW_PX_MAP_CRB_SN 29167#define QLA82XX_HW_PX_MAP_CRB_EG 31168#define QLA82XX_HW_PX_MAP_CRB_PH2 32169#define QLA82XX_HW_PX_MAP_CRB_PS2 33170#define QLA82XX_HW_PX_MAP_CRB_CAM 34171#define QLA82XX_HW_PX_MAP_CRB_CAS0 35172#define QLA82XX_HW_PX_MAP_CRB_CAS1 36173#define QLA82XX_HW_PX_MAP_CRB_CAS2 37174#define QLA82XX_HW_PX_MAP_CRB_C2C0 38175#define QLA82XX_HW_PX_MAP_CRB_C2C1 39176#define QLA82XX_HW_PX_MAP_CRB_TIMR 40177#define QLA82XX_HW_PX_MAP_CRB_RPMX1 42178#define QLA82XX_HW_PX_MAP_CRB_RPMX2 43179#define QLA82XX_HW_PX_MAP_CRB_RPMX3 44180#define QLA82XX_HW_PX_MAP_CRB_RPMX4 45181#define QLA82XX_HW_PX_MAP_CRB_RPMX5 46182#define QLA82XX_HW_PX_MAP_CRB_RPMX6 47183#define QLA82XX_HW_PX_MAP_CRB_RPMX7 48184#define QLA82XX_HW_PX_MAP_CRB_XDMA 49185#define QLA82XX_HW_PX_MAP_CRB_I2Q 50186#define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51187#define QLA82XX_HW_PX_MAP_CRB_CAS3 52188#define QLA82XX_HW_PX_MAP_CRB_RPMX0 53189#define QLA82XX_HW_PX_MAP_CRB_RPMX8 54190#define QLA82XX_HW_PX_MAP_CRB_RPMX9 55191#define QLA82XX_HW_PX_MAP_CRB_OCM0 56192#define QLA82XX_HW_PX_MAP_CRB_OCM1 57193#define QLA82XX_HW_PX_MAP_CRB_SMB 58194#define QLA82XX_HW_PX_MAP_CRB_I2C0 59195#define QLA82XX_HW_PX_MAP_CRB_I2C1 60196#define QLA82XX_HW_PX_MAP_CRB_LPC 61197#define QLA82XX_HW_PX_MAP_CRB_PGNC 62198#define QLA82XX_HW_PX_MAP_CRB_PGR0 63199#define QLA82XX_HW_PX_MAP_CRB_PGR1 4200#define QLA82XX_HW_PX_MAP_CRB_PGR2 30201#define QLA82XX_HW_PX_MAP_CRB_PGR3 41202 203/* This field defines CRB adr [31:20] of the agents */204/* */205 206#define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \207 QLA82XX_HW_MN_CRB_AGT_ADR)208#define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \209 QLA82XX_HW_PH_CRB_AGT_ADR)210#define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \211 QLA82XX_HW_MS_CRB_AGT_ADR)212#define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \213 QLA82XX_HW_PS_CRB_AGT_ADR)214#define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \215 QLA82XX_HW_SS_CRB_AGT_ADR)216#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \217 QLA82XX_HW_RPMX3_CRB_AGT_ADR)218#define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \219 QLA82XX_HW_QMS_CRB_AGT_ADR)220#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \221 QLA82XX_HW_SQGS0_CRB_AGT_ADR)222#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \223 QLA82XX_HW_SQGS1_CRB_AGT_ADR)224#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \225 QLA82XX_HW_SQGS2_CRB_AGT_ADR)226#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \227 QLA82XX_HW_SQGS3_CRB_AGT_ADR)228#define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \229 QLA82XX_HW_C2C0_CRB_AGT_ADR)230#define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \231 QLA82XX_HW_C2C1_CRB_AGT_ADR)232#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \233 QLA82XX_HW_RPMX2_CRB_AGT_ADR)234#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \235 QLA82XX_HW_RPMX4_CRB_AGT_ADR)236#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \237 QLA82XX_HW_RPMX7_CRB_AGT_ADR)238#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \239 QLA82XX_HW_RPMX9_CRB_AGT_ADR)240#define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \241 QLA82XX_HW_SMB_CRB_AGT_ADR)242 243#define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \244 QLA82XX_HW_NIU_CRB_AGT_ADR)245#define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \246 QLA82XX_HW_I2C0_CRB_AGT_ADR)247#define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \248 QLA82XX_HW_I2C1_CRB_AGT_ADR)249 250#define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \251 QLA82XX_HW_SRE_CRB_AGT_ADR)252#define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \253 QLA82XX_HW_EG_CRB_AGT_ADR)254#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \255 QLA82XX_HW_RPMX0_CRB_AGT_ADR)256#define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \257 QLA82XX_HW_QM_CRB_AGT_ADR)258#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \259 QLA82XX_HW_SQG0_CRB_AGT_ADR)260#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \261 QLA82XX_HW_SQG1_CRB_AGT_ADR)262#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \263 QLA82XX_HW_SQG2_CRB_AGT_ADR)264#define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \265 QLA82XX_HW_SQG3_CRB_AGT_ADR)266#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \267 QLA82XX_HW_RPMX1_CRB_AGT_ADR)268#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \269 QLA82XX_HW_RPMX5_CRB_AGT_ADR)270#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \271 QLA82XX_HW_RPMX6_CRB_AGT_ADR)272#define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \273 QLA82XX_HW_RPMX8_CRB_AGT_ADR)274#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \275 QLA82XX_HW_CAS0_CRB_AGT_ADR)276#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \277 QLA82XX_HW_CAS1_CRB_AGT_ADR)278#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \279 QLA82XX_HW_CAS2_CRB_AGT_ADR)280#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \281 QLA82XX_HW_CAS3_CRB_AGT_ADR)282 283#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \284 QLA82XX_HW_PEGNI_CRB_AGT_ADR)285#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \286 QLA82XX_HW_PEGND_CRB_AGT_ADR)287#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \288 QLA82XX_HW_PEGN0_CRB_AGT_ADR)289#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \290 QLA82XX_HW_PEGN1_CRB_AGT_ADR)291#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \292 QLA82XX_HW_PEGN2_CRB_AGT_ADR)293#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \294 QLA82XX_HW_PEGN3_CRB_AGT_ADR)295#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \296 QLA82XX_HW_PEGN4_CRB_AGT_ADR)297 298#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \299 QLA82XX_HW_PEGNC_CRB_AGT_ADR)300#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \301 QLA82XX_HW_PEGR0_CRB_AGT_ADR)302#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \303 QLA82XX_HW_PEGR1_CRB_AGT_ADR)304#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \305 QLA82XX_HW_PEGR2_CRB_AGT_ADR)306#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \307 QLA82XX_HW_PEGR3_CRB_AGT_ADR)308 309#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \310 QLA82XX_HW_PEGSI_CRB_AGT_ADR)311#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \312 QLA82XX_HW_PEGSD_CRB_AGT_ADR)313#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \314 QLA82XX_HW_PEGS0_CRB_AGT_ADR)315#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \316 QLA82XX_HW_PEGS1_CRB_AGT_ADR)317#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \318 QLA82XX_HW_PEGS2_CRB_AGT_ADR)319#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \320 QLA82XX_HW_PEGS3_CRB_AGT_ADR)321#define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \322 QLA82XX_HW_PEGSC_CRB_AGT_ADR)323 324#define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \325 QLA82XX_HW_NCM_CRB_AGT_ADR)326#define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \327 QLA82XX_HW_TMR_CRB_AGT_ADR)328#define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \329 QLA82XX_HW_XDMA_CRB_AGT_ADR)330#define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \331 QLA82XX_HW_SN_CRB_AGT_ADR)332#define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \333 QLA82XX_HW_I2Q_CRB_AGT_ADR)334#define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \335 QLA82XX_HW_ROMUSB_CRB_AGT_ADR)336#define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \337 QLA82XX_HW_OCM0_CRB_AGT_ADR)338#define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \339 QLA82XX_HW_OCM1_CRB_AGT_ADR)340#define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \341 QLA82XX_HW_LPC_CRB_AGT_ADR)342 343#define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)344#define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)345#define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)346#define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)347#define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)348#define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)349#define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)350#define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)351#define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)352 353#define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)354#define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)355#define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)356 357/* Lock IDs for ROM lock */358#define ROM_LOCK_DRIVER 0x0d417340359 360#define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */361#define QLA82XX_PCI_CRB_WINDOW(A) (QLA82XX_PCI_CRBSPACE + \362 (A)*QLA82XX_PCI_CRB_WINDOWSIZE)363 364#define QLA82XX_CRB_C2C_0 \365 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)366#define QLA82XX_CRB_C2C_1 \367 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)368#define QLA82XX_CRB_C2C_2 \369 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)370#define QLA82XX_CRB_CAM \371 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)372#define QLA82XX_CRB_CASPER \373 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)374#define QLA82XX_CRB_CASPER_0 \375 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)376#define QLA82XX_CRB_CASPER_1 \377 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)378#define QLA82XX_CRB_CASPER_2 \379 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)380#define QLA82XX_CRB_DDR_MD \381 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)382#define QLA82XX_CRB_DDR_NET \383 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)384#define QLA82XX_CRB_EPG \385 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)386#define QLA82XX_CRB_I2Q \387 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)388#define QLA82XX_CRB_NIU \389 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)390/* HACK upon HACK upon HACK (for PCIE builds) */391#define QLA82XX_CRB_PCIX_HOST \392 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)393#define QLA82XX_CRB_PCIX_HOST2 \394 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)395#define QLA82XX_CRB_PCIX_MD \396 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)397#define QLA82XX_CRB_PCIE QLA82XX_CRB_PCIX_MD398/* window 1 pcie slot */399#define QLA82XX_CRB_PCIE2 \400 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)401 402#define QLA82XX_CRB_PEG_MD_0 \403 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)404#define QLA82XX_CRB_PEG_MD_1 \405 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)406#define QLA82XX_CRB_PEG_MD_2 \407 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)408#define QLA82XX_CRB_PEG_MD_3 \409 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)410#define QLA82XX_CRB_PEG_MD_3 \411 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)412#define QLA82XX_CRB_PEG_MD_D \413 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)414#define QLA82XX_CRB_PEG_MD_I \415 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)416#define QLA82XX_CRB_PEG_NET_0 \417 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)418#define QLA82XX_CRB_PEG_NET_1 \419 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)420#define QLA82XX_CRB_PEG_NET_2 \421 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)422#define QLA82XX_CRB_PEG_NET_3 \423 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)424#define QLA82XX_CRB_PEG_NET_4 \425 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)426#define QLA82XX_CRB_PEG_NET_D \427 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)428#define QLA82XX_CRB_PEG_NET_I \429 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)430#define QLA82XX_CRB_PQM_MD \431 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)432#define QLA82XX_CRB_PQM_NET \433 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)434#define QLA82XX_CRB_QDR_MD \435 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)436#define QLA82XX_CRB_QDR_NET \437 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)438#define QLA82XX_CRB_ROMUSB \439 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)440#define QLA82XX_CRB_RPMX_0 \441 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)442#define QLA82XX_CRB_RPMX_1 \443 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)444#define QLA82XX_CRB_RPMX_2 \445 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)446#define QLA82XX_CRB_RPMX_3 \447 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)448#define QLA82XX_CRB_RPMX_4 \449 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)450#define QLA82XX_CRB_RPMX_5 \451 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)452#define QLA82XX_CRB_RPMX_6 \453 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)454#define QLA82XX_CRB_RPMX_7 \455 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)456#define QLA82XX_CRB_SQM_MD_0 \457 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)458#define QLA82XX_CRB_SQM_MD_1 \459 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)460#define QLA82XX_CRB_SQM_MD_2 \461 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)462#define QLA82XX_CRB_SQM_MD_3 \463 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)464#define QLA82XX_CRB_SQM_NET_0 \465 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)466#define QLA82XX_CRB_SQM_NET_1 \467 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)468#define QLA82XX_CRB_SQM_NET_2 \469 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)470#define QLA82XX_CRB_SQM_NET_3 \471 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)472#define QLA82XX_CRB_SRE \473 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)474#define QLA82XX_CRB_TIMER \475 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)476#define QLA82XX_CRB_XDMA \477 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)478#define QLA82XX_CRB_I2C0 \479 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)480#define QLA82XX_CRB_I2C1 \481 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)482#define QLA82XX_CRB_OCM0 \483 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)484#define QLA82XX_CRB_SMB \485 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)486 487#define QLA82XX_CRB_MAX QLA82XX_PCI_CRB_WINDOW(64)488 489/*490 * ====================== BASE ADDRESSES ON-CHIP ======================491 * Base addresses of major components on-chip.492 * ====================== BASE ADDRESSES ON-CHIP ======================493 */494#define QLA8XXX_ADDR_DDR_NET (0x0000000000000000ULL)495#define QLA8XXX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)496 497/* Imbus address bit used to indicate a host address. This bit is498 * eliminated by the pcie bar and bar select before presentation499 * over pcie. */500/* host memory via IMBUS */501#define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)502#define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)503#define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)504#define QLA8XXX_ADDR_OCM0 (0x0000000200000000ULL)505#define QLA8XXX_ADDR_OCM0_MAX (0x00000002000fffffULL)506#define QLA8XXX_ADDR_OCM1 (0x0000000200400000ULL)507#define QLA8XXX_ADDR_OCM1_MAX (0x00000002004fffffULL)508#define QLA8XXX_ADDR_QDR_NET (0x0000000300000000ULL)509 510#define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)511#define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)512#define QLA8XXX_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)513 514#define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000515#define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000516#define QLA82XX_PCI_CAMQM (unsigned long)0x04800000517#define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff518#define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000519#define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000520#define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff521 522/* PCI Windowing for DDR regions. */523#define QLA8XXX_ADDR_IN_RANGE(addr, low, high) \524 (((addr) <= (high)) && ((addr) >= (low)))525 526/*527 * Register offsets for MN528 */529#define MIU_CONTROL (0x000)530#define MIU_TAG (0x004)531#define MIU_TEST_AGT_CTRL (0x090)532#define MIU_TEST_AGT_ADDR_LO (0x094)533#define MIU_TEST_AGT_ADDR_HI (0x098)534#define MIU_TEST_AGT_WRDATA_LO (0x0a0)535#define MIU_TEST_AGT_WRDATA_HI (0x0a4)536#define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))537#define MIU_TEST_AGT_RDDATA_LO (0x0a8)538#define MIU_TEST_AGT_RDDATA_HI (0x0ac)539#define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))540#define MIU_TEST_AGT_ADDR_MASK 0xfffffff8541#define MIU_TEST_AGT_UPPER_ADDR(off) (0)542 543/* MIU_TEST_AGT_CTRL flags. work for SIU as well */544#define MIU_TA_CTL_START 1545#define MIU_TA_CTL_ENABLE 2546#define MIU_TA_CTL_WRITE 4547#define MIU_TA_CTL_BUSY 8548 549#define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)550#define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE |\551 MIU_TA_CTL_START)552#define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)553 554/*CAM RAM */555# define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)556# define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg))557 558#define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))559#define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))560#define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))561#define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))562#define QLA82XX_CAM_RAM_DB1 (QLA82XX_CAM_RAM(0x1b0))563#define QLA82XX_CAM_RAM_DB2 (QLA82XX_CAM_RAM(0x1b4))564 565#define HALT_STATUS_UNRECOVERABLE 0x80000000566#define HALT_STATUS_RECOVERABLE 0x40000000567 568 569#define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))570#define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))571#define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))572#define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))573#define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))574#define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg))575 576/* Driver Coexistence Defines */577#define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))578#define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))579#define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))580#define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))581#define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))582#define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))583 584enum qla_regs {585 QLA8XXX_PEG_HALT_STATUS1 = 0,586 QLA8XXX_PEG_HALT_STATUS2,587 QLA8XXX_PEG_ALIVE_COUNTER,588 QLA8XXX_CRB_DRV_ACTIVE,589 QLA8XXX_CRB_DEV_STATE,590 QLA8XXX_CRB_DRV_STATE,591 QLA8XXX_CRB_DRV_SCRATCH,592 QLA8XXX_CRB_DEV_PART_INFO,593 QLA8XXX_CRB_DRV_IDC_VERSION,594 QLA8XXX_FW_VERSION_MAJOR,595 QLA8XXX_FW_VERSION_MINOR,596 QLA8XXX_FW_VERSION_SUB,597 QLA8XXX_CRB_CMDPEG_STATE,598 QLA8XXX_CRB_TEMP_STATE,599};600 601/* Every driver should use these Device State */602#define QLA8XXX_DEV_COLD 1603#define QLA8XXX_DEV_INITIALIZING 2604#define QLA8XXX_DEV_READY 3605#define QLA8XXX_DEV_NEED_RESET 4606#define QLA8XXX_DEV_NEED_QUIESCENT 5607#define QLA8XXX_DEV_FAILED 6608#define QLA8XXX_DEV_QUIESCENT 7609#define MAX_STATES 8 /* Increment if new state added */610 611#define QLA82XX_IDC_VERSION 0x1612#define ROM_DEV_INIT_TIMEOUT 30613#define ROM_DRV_RESET_ACK_TIMEOUT 10614 615#define PCIE_SETUP_FUNCTION (0x12040)616#define PCIE_SETUP_FUNCTION2 (0x12048)617 618#define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg))619#define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg))620 621#define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */622#define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */623#define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */624#define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */625#define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */626#define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/627 628/*629 * The PCI VendorID and DeviceID for our board.630 */631#define QLA82XX_MSIX_TBL_SPACE 8192632#define QLA82XX_PCI_REG_MSIX_TBL 0x44633#define QLA82XX_PCI_MSIX_CONTROL 0x40634 635struct crb_128M_2M_sub_block_map {636 unsigned valid;637 unsigned start_128M;638 unsigned end_128M;639 unsigned start_2M;640};641 642struct crb_128M_2M_block_map {643 struct crb_128M_2M_sub_block_map sub_block[16];644};645 646struct crb_addr_pair {647 long addr;648 long data;649};650 651#define ADDR_ERROR ((unsigned long) 0xffffffff)652#define MAX_CTL_CHECK 1000653#define QLA82XX_FWERROR_CODE(code) ((code >> 8) & 0x1fffff)654 655/***************************************************************************656 * PCI related defines.657 **************************************************************************/658 659/*660 * Interrupt related defines.661 */662#define PCIX_TARGET_STATUS (0x10118)663#define PCIX_TARGET_STATUS_F1 (0x10160)664#define PCIX_TARGET_STATUS_F2 (0x10164)665#define PCIX_TARGET_STATUS_F3 (0x10168)666#define PCIX_TARGET_STATUS_F4 (0x10360)667#define PCIX_TARGET_STATUS_F5 (0x10364)668#define PCIX_TARGET_STATUS_F6 (0x10368)669#define PCIX_TARGET_STATUS_F7 (0x1036c)670 671#define PCIX_TARGET_MASK (0x10128)672#define PCIX_TARGET_MASK_F1 (0x10170)673#define PCIX_TARGET_MASK_F2 (0x10174)674#define PCIX_TARGET_MASK_F3 (0x10178)675#define PCIX_TARGET_MASK_F4 (0x10370)676#define PCIX_TARGET_MASK_F5 (0x10374)677#define PCIX_TARGET_MASK_F6 (0x10378)678#define PCIX_TARGET_MASK_F7 (0x1037c)679 680/*681 * Message Signaled Interrupts682 */683#define PCIX_MSI_F0 (0x13000)684#define PCIX_MSI_F1 (0x13004)685#define PCIX_MSI_F2 (0x13008)686#define PCIX_MSI_F3 (0x1300c)687#define PCIX_MSI_F4 (0x13010)688#define PCIX_MSI_F5 (0x13014)689#define PCIX_MSI_F6 (0x13018)690#define PCIX_MSI_F7 (0x1301c)691#define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))692 693/*694 *695 */696#define PCIX_INT_VECTOR (0x10100)697#define PCIX_INT_MASK (0x10104)698 699/*700 * Interrupt state machine and other bits.701 */702#define PCIE_MISCCFG_RC (0x1206c)703 704 705#define ISR_INT_TARGET_STATUS \706 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))707#define ISR_INT_TARGET_STATUS_F1 \708 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))709#define ISR_INT_TARGET_STATUS_F2 \710 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))711#define ISR_INT_TARGET_STATUS_F3 \712 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))713#define ISR_INT_TARGET_STATUS_F4 \714 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))715#define ISR_INT_TARGET_STATUS_F5 \716 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))717#define ISR_INT_TARGET_STATUS_F6 \718 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))719#define ISR_INT_TARGET_STATUS_F7 \720 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))721 722#define ISR_INT_TARGET_MASK \723 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))724#define ISR_INT_TARGET_MASK_F1 \725 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))726#define ISR_INT_TARGET_MASK_F2 \727 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))728#define ISR_INT_TARGET_MASK_F3 \729 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))730#define ISR_INT_TARGET_MASK_F4 \731 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))732#define ISR_INT_TARGET_MASK_F5 \733 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))734#define ISR_INT_TARGET_MASK_F6 \735 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))736#define ISR_INT_TARGET_MASK_F7 \737 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))738 739#define ISR_INT_VECTOR (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))740#define ISR_INT_MASK (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))741#define ISR_INT_STATE_REG (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))742 743#define ISR_MSI_INT_TRIGGER(FUNC) (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))744 745 746#define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)747#define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)748 749/*750 * PCI Interrupt Vector Values.751 */752#define PCIX_INT_VECTOR_BIT_F0 0x0080753#define PCIX_INT_VECTOR_BIT_F1 0x0100754#define PCIX_INT_VECTOR_BIT_F2 0x0200755#define PCIX_INT_VECTOR_BIT_F3 0x0400756#define PCIX_INT_VECTOR_BIT_F4 0x0800757#define PCIX_INT_VECTOR_BIT_F5 0x1000758#define PCIX_INT_VECTOR_BIT_F6 0x2000759#define PCIX_INT_VECTOR_BIT_F7 0x4000760 761/* struct qla4_8xxx_legacy_intr_set defined in ql4_def.h */762 763#define QLA82XX_LEGACY_INTR_CONFIG \764{ \765 { \766 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \767 .tgt_status_reg = ISR_INT_TARGET_STATUS, \768 .tgt_mask_reg = ISR_INT_TARGET_MASK, \769 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \770 \771 { \772 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \773 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \774 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \775 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \776 \777 { \778 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \779 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \780 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \781 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \782 \783 { \784 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \785 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \786 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \787 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \788 \789 { \790 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \791 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \792 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \793 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \794 \795 { \796 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \797 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \798 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \799 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \800 \801 { \802 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \803 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \804 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \805 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \806 \807 { \808 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \809 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \810 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \811 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \812}813 814/* Magic number to let user know flash is programmed */815#define QLA82XX_BDINFO_MAGIC 0x12345678816#define FW_SIZE_OFFSET (0x3e840c)817 818/* QLA82XX additions */819#define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)820#define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)821 822/* Minidump related */823 824/* Entry Type Defines */825#define QLA8XXX_RDNOP 0826#define QLA8XXX_RDCRB 1827#define QLA8XXX_RDMUX 2828#define QLA8XXX_QUEUE 3829#define QLA8XXX_BOARD 4830#define QLA8XXX_RDOCM 6831#define QLA8XXX_PREGS 7832#define QLA8XXX_L1DTG 8833#define QLA8XXX_L1ITG 9834#define QLA8XXX_L1DAT 11835#define QLA8XXX_L1INS 12836#define QLA8XXX_L2DTG 21837#define QLA8XXX_L2ITG 22838#define QLA8XXX_L2DAT 23839#define QLA8XXX_L2INS 24840#define QLA83XX_POLLRD 35841#define QLA83XX_RDMUX2 36842#define QLA83XX_POLLRDMWR 37843#define QLA8044_RDDFE 38844#define QLA8044_RDMDIO 39845#define QLA8044_POLLWR 40846#define QLA8XXX_RDROM 71847#define QLA8XXX_RDMEM 72848#define QLA8XXX_CNTRL 98849#define QLA83XX_TLHDR 99850#define QLA8XXX_RDEND 255851 852/* Opcodes for Control Entries.853 * These Flags are bit fields.854 */855#define QLA8XXX_DBG_OPCODE_WR 0x01856#define QLA8XXX_DBG_OPCODE_RW 0x02857#define QLA8XXX_DBG_OPCODE_AND 0x04858#define QLA8XXX_DBG_OPCODE_OR 0x08859#define QLA8XXX_DBG_OPCODE_POLL 0x10860#define QLA8XXX_DBG_OPCODE_RDSTATE 0x20861#define QLA8XXX_DBG_OPCODE_WRSTATE 0x40862#define QLA8XXX_DBG_OPCODE_MDSTATE 0x80863 864/* Driver Flags */865#define QLA8XXX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */866#define QLA8XXX_DBG_SIZE_ERR_FLAG 0x40 /* Entry vs Capture size867 * mismatch */868 869/* Driver_code is for driver to write some info about the entry870 * currently not used.871 */872struct qla8xxx_minidump_entry_hdr {873 uint32_t entry_type;874 uint32_t entry_size;875 uint32_t entry_capture_size;876 struct {877 uint8_t entry_capture_mask;878 uint8_t entry_code;879 uint8_t driver_code;880 uint8_t driver_flags;881 } d_ctrl;882};883 884/* Read CRB entry header */885struct qla8xxx_minidump_entry_crb {886 struct qla8xxx_minidump_entry_hdr h;887 uint32_t addr;888 struct {889 uint8_t addr_stride;890 uint8_t state_index_a;891 uint16_t poll_timeout;892 } crb_strd;893 uint32_t data_size;894 uint32_t op_count;895 896 struct {897 uint8_t opcode;898 uint8_t state_index_v;899 uint8_t shl;900 uint8_t shr;901 } crb_ctrl;902 903 uint32_t value_1;904 uint32_t value_2;905 uint32_t value_3;906};907 908struct qla8xxx_minidump_entry_cache {909 struct qla8xxx_minidump_entry_hdr h;910 uint32_t tag_reg_addr;911 struct {912 uint16_t tag_value_stride;913 uint16_t init_tag_value;914 } addr_ctrl;915 uint32_t data_size;916 uint32_t op_count;917 uint32_t control_addr;918 struct {919 uint16_t write_value;920 uint8_t poll_mask;921 uint8_t poll_wait;922 } cache_ctrl;923 uint32_t read_addr;924 struct {925 uint8_t read_addr_stride;926 uint8_t read_addr_cnt;927 uint16_t rsvd_1;928 } read_ctrl;929};930 931/* Read OCM */932struct qla8xxx_minidump_entry_rdocm {933 struct qla8xxx_minidump_entry_hdr h;934 uint32_t rsvd_0;935 uint32_t rsvd_1;936 uint32_t data_size;937 uint32_t op_count;938 uint32_t rsvd_2;939 uint32_t rsvd_3;940 uint32_t read_addr;941 uint32_t read_addr_stride;942};943 944/* Read Memory */945struct qla8xxx_minidump_entry_rdmem {946 struct qla8xxx_minidump_entry_hdr h;947 uint32_t rsvd[6];948 uint32_t read_addr;949 uint32_t read_data_size;950};951 952/* Read ROM */953struct qla8xxx_minidump_entry_rdrom {954 struct qla8xxx_minidump_entry_hdr h;955 uint32_t rsvd[6];956 uint32_t read_addr;957 uint32_t read_data_size;958};959 960/* Mux entry */961struct qla8xxx_minidump_entry_mux {962 struct qla8xxx_minidump_entry_hdr h;963 uint32_t select_addr;964 uint32_t rsvd_0;965 uint32_t data_size;966 uint32_t op_count;967 uint32_t select_value;968 uint32_t select_value_stride;969 uint32_t read_addr;970 uint32_t rsvd_1;971};972 973/* Queue entry */974struct qla8xxx_minidump_entry_queue {975 struct qla8xxx_minidump_entry_hdr h;976 uint32_t select_addr;977 struct {978 uint16_t queue_id_stride;979 uint16_t rsvd_0;980 } q_strd;981 uint32_t data_size;982 uint32_t op_count;983 uint32_t rsvd_1;984 uint32_t rsvd_2;985 uint32_t read_addr;986 struct {987 uint8_t read_addr_stride;988 uint8_t read_addr_cnt;989 uint16_t rsvd_3;990 } rd_strd;991};992 993#define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129994#define RQST_TMPLT_SIZE 0x0995#define RQST_TMPLT 0x1996#define MD_DIRECT_ROM_WINDOW 0x42110030997#define MD_DIRECT_ROM_READ_BASE 0x42150000998#define MD_MIU_TEST_AGT_CTRL 0x41000090999#define MD_MIU_TEST_AGT_ADDR_LO 0x410000941000#define MD_MIU_TEST_AGT_ADDR_HI 0x410000981001 1002#define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A01003#define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A41004#define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B01005#define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B41006 1007#endif1008