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1# SPDX-License-Identifier: GPL-2.0-only2 3if ARCH_ASPEED || COMPILE_TEST4 5menu "ASPEED SoC drivers"6 7config ASPEED_LPC_CTRL8 tristate "ASPEED LPC firmware cycle control"9 select REGMAP10 select MFD_SYSCON11 default ARCH_ASPEED12 help13 Control LPC firmware cycle mappings through ioctl()s. The driver14 also provides a read/write interface to a BMC ram region where the15 host LPC read/write region can be buffered.16 17config ASPEED_LPC_SNOOP18 tristate "ASPEED LPC snoop support"19 select REGMAP20 select MFD_SYSCON21 default ARCH_ASPEED22 help23 Provides a driver to control the LPC snoop interface which24 allows the BMC to listen on and save the data written by25 the host to an arbitrary LPC I/O port.26 27config ASPEED_UART_ROUTING28 tristate "ASPEED uart routing control"29 select REGMAP30 select MFD_SYSCON31 default ARCH_ASPEED32 help33 Provides a driver to control the UART routing paths, allowing34 users to perform runtime configuration of the RX muxes among35 the UART controllers and I/O pins.36 37config ASPEED_P2A_CTRL38 tristate "ASPEED P2A (VGA MMIO to BMC) bridge control"39 select REGMAP40 select MFD_SYSCON41 default ARCH_ASPEED42 help43 Control ASPEED P2A VGA MMIO to BMC mappings through ioctl()s. The44 driver also provides an interface for userspace mappings to a45 pre-defined region.46 47config ASPEED_SOCINFO48 bool "ASPEED SoC Information driver"49 default ARCH_ASPEED50 select SOC_BUS51 default ARCH_ASPEED52 help53 Say yes to support decoding of ASPEED BMC information.54 55endmenu56 57endif58