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1/* SPDX-License-Identifier: GPL-2.0-only */2 3#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H4#define __SOC_MEDIATEK_MT8186_MMSYS_H5 6/* Values for DPI configuration in MMSYS address space */7#define MT8186_MMSYS_DPI_OUTPUT_FORMAT 0x4008#define MT8186_DPI_FORMAT_MASK GENMASK(1, 0)9#define MT8186_DPI_RGB888_SDR_CON 010#define MT8186_DPI_RGB888_DDR_CON 111#define MT8186_DPI_RGB565_SDR_CON 212#define MT8186_DPI_RGB565_DDR_CON 313 14#define MT8186_MMSYS_OVL_CON 0xF0415#define MT8186_MMSYS_OVL0_CON_MASK 0x316#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC17#define MT8186_OVL0_GO_BLEND BIT(0)18#define MT8186_OVL0_GO_BG BIT(1)19#define MT8186_OVL0_2L_GO_BLEND BIT(2)20#define MT8186_OVL0_2L_GO_BG BIT(3)21#define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C22#define MT8186_RDMA0_SOUT_SEL_MASK 0xF23#define MT8186_RDMA0_SOUT_TO_DSI0 (0)24#define MT8186_RDMA0_SOUT_TO_COLOR0 (1)25#define MT8186_RDMA0_SOUT_TO_DPI0 (2)26#define MT8186_DISP_OVL0_2L_MOUT_EN 0xF1427#define MT8186_OVL0_2L_MOUT_EN_MASK 0xF28#define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0)29#define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3)30#define MT8186_DISP_OVL0_MOUT_EN 0xF1831#define MT8186_OVL0_MOUT_EN_MASK 0xF32#define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0)33#define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3)34#define MT8186_DISP_DITHER0_MOUT_EN 0xF2035#define MT8186_DITHER0_MOUT_EN_MASK 0xF36#define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0)37#define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2)38#define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3)39#define MT8186_DISP_RDMA0_SEL_IN 0xF2840#define MT8186_RDMA0_SEL_IN_MASK 0xF41#define MT8186_RDMA0_FROM_OVL0 042#define MT8186_RDMA0_FROM_OVL0_2L 243#define MT8186_DISP_DSI0_SEL_IN 0xF3044#define MT8186_DSI0_SEL_IN_MASK 0xF45#define MT8186_DSI0_FROM_RDMA0 046#define MT8186_DSI0_FROM_DITHER0 147#define MT8186_DSI0_FROM_RDMA1 248#define MT8186_DISP_RDMA1_MOUT_EN 0xF3C49#define MT8186_RDMA1_MOUT_EN_MASK 0xF50#define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0)51#define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2)52#define MT8186_DISP_RDMA1_SEL_IN 0xF4053#define MT8186_RDMA1_SEL_IN_MASK 0xF54#define MT8186_RDMA1_FROM_OVL0 055#define MT8186_RDMA1_FROM_OVL0_2L 256#define MT8186_RDMA1_FROM_DITHER0 357#define MT8186_DISP_DPI0_SEL_IN 0xF4458#define MT8186_DPI0_SEL_IN_MASK 0xF59#define MT8186_DPI0_FROM_RDMA1 060#define MT8186_DPI0_FROM_DITHER0 161#define MT8186_DPI0_FROM_RDMA0 262 63#define MT8186_MMSYS_SW0_RST_B 0x16064 65static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {66 {67 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,68 MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,69 MT8186_OVL0_MOUT_TO_RDMA070 },71 {72 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,73 MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,74 MT8186_RDMA0_FROM_OVL075 },76 {77 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,78 MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,79 MT8186_OVL0_GO_BLEND80 },81 {82 DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,83 MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,84 MT8186_RDMA0_SOUT_TO_COLOR085 },86 {87 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,88 MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,89 MT8186_DITHER0_MOUT_TO_DSI0,90 },91 {92 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,93 MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,94 MT8186_DSI0_FROM_DITHER095 },96 {97 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,98 MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,99 MT8186_OVL0_2L_MOUT_TO_RDMA1100 },101 {102 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,103 MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,104 MT8186_RDMA1_FROM_OVL0_2L105 },106 {107 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,108 MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,109 MT8186_OVL0_2L_GO_BLEND110 },111 {112 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,113 MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,114 MT8186_RDMA1_MOUT_TO_DPI0_SEL115 },116 {117 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,118 MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,119 MT8186_DPI0_FROM_RDMA1120 },121};122 123#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */124