2618 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2014 MediaTek Inc.4 * Author: Flora Fu, MediaTek5 */6#include <linux/clk.h>7#include <linux/interrupt.h>8#include <linux/io.h>9#include <linux/kernel.h>10#include <linux/module.h>11#include <linux/of.h>12#include <linux/of_platform.h>13#include <linux/platform_device.h>14#include <linux/regmap.h>15#include <linux/reset.h>16 17#define PWRAP_POLL_DELAY_US 1018#define PWRAP_POLL_TIMEOUT_US 1000019 20#define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x421#define PWRAP_MT8135_BRIDGE_WACS3_EN 0x1022#define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x1423#define PWRAP_MT8135_BRIDGE_WACS4_EN 0x2424#define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x2825#define PWRAP_MT8135_BRIDGE_INT_EN 0x3826#define PWRAP_MT8135_BRIDGE_TIMER_EN 0x4827#define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x5028#define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x5429 30/* macro for wrapper status */31#define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)32#define PWRAP_GET_WACS_ARB_FSM(x) (((x) >> 1) & 0x00000007)33#define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)34#define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)35#define PWRAP_STATE_SYNC_IDLE0 BIT(20)36#define PWRAP_STATE_INIT_DONE0 BIT(21)37#define PWRAP_STATE_INIT_DONE0_MT8186 BIT(22)38#define PWRAP_STATE_INIT_DONE1 BIT(15)39 40/* macro for WACS FSM */41#define PWRAP_WACS_FSM_IDLE 0x0042#define PWRAP_WACS_FSM_REQ 0x0243#define PWRAP_WACS_FSM_WFDLE 0x0444#define PWRAP_WACS_FSM_WFVLDCLR 0x0645#define PWRAP_WACS_INIT_DONE 0x0146#define PWRAP_WACS_WACS_SYNC_IDLE 0x0147#define PWRAP_WACS_SYNC_BUSY 0x0048 49/* macro for device wrapper default value */50#define PWRAP_DEW_READ_TEST_VAL 0x5aa551#define PWRAP_DEW_COMP_READ_TEST_VAL 0xa55a52#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a53 54/* macro for manual command */55#define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)56#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)57#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)58#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)59#define PWRAP_MAN_CMD_OP_CK (0x2 << 8)60#define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)61#define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)62#define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)63 64/* macro for Watch Dog Timer Source */65#define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)66#define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)67#define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)68#define PWRAP_WDT_SRC_MASK_ALL 0xffffffff69#define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \70 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \71 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)72 73/* Group of bits used for shown slave capability */74#define PWRAP_SLV_CAP_SPI BIT(0)75#define PWRAP_SLV_CAP_DUALIO BIT(1)76#define PWRAP_SLV_CAP_SECURITY BIT(2)77#define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))78 79/* Group of bits used for shown pwrap capability */80#define PWRAP_CAP_BRIDGE BIT(0)81#define PWRAP_CAP_RESET BIT(1)82#define PWRAP_CAP_DCM BIT(2)83#define PWRAP_CAP_INT1_EN BIT(3)84#define PWRAP_CAP_WDT_SRC1 BIT(4)85#define PWRAP_CAP_ARB BIT(5)86#define PWRAP_CAP_ARB_MT8186 BIT(8)87 88/* defines for slave device wrapper registers */89enum dew_regs {90 PWRAP_DEW_BASE,91 PWRAP_DEW_DIO_EN,92 PWRAP_DEW_READ_TEST,93 PWRAP_DEW_WRITE_TEST,94 PWRAP_DEW_CRC_EN,95 PWRAP_DEW_CRC_VAL,96 PWRAP_DEW_MON_GRP_SEL,97 PWRAP_DEW_CIPHER_KEY_SEL,98 PWRAP_DEW_CIPHER_IV_SEL,99 PWRAP_DEW_CIPHER_RDY,100 PWRAP_DEW_CIPHER_MODE,101 PWRAP_DEW_CIPHER_SWRST,102 103 /* MT6323 only regs */104 PWRAP_DEW_CIPHER_EN,105 PWRAP_DEW_RDDMY_NO,106 107 /* MT6358 only regs */108 PWRAP_SMT_CON1,109 PWRAP_DRV_CON1,110 PWRAP_FILTER_CON0,111 PWRAP_GPIO_PULLEN0_CLR,112 PWRAP_RG_SPI_CON0,113 PWRAP_RG_SPI_RECORD0,114 PWRAP_RG_SPI_CON2,115 PWRAP_RG_SPI_CON3,116 PWRAP_RG_SPI_CON4,117 PWRAP_RG_SPI_CON5,118 PWRAP_RG_SPI_CON6,119 PWRAP_RG_SPI_CON7,120 PWRAP_RG_SPI_CON8,121 PWRAP_RG_SPI_CON13,122 PWRAP_SPISLV_KEY,123 124 /* MT6359 only regs */125 PWRAP_DEW_CRC_SWRST,126 PWRAP_DEW_RG_EN_RECORD,127 PWRAP_DEW_RECORD_CMD0,128 PWRAP_DEW_RECORD_CMD1,129 PWRAP_DEW_RECORD_CMD2,130 PWRAP_DEW_RECORD_CMD3,131 PWRAP_DEW_RECORD_CMD4,132 PWRAP_DEW_RECORD_CMD5,133 PWRAP_DEW_RECORD_WDATA0,134 PWRAP_DEW_RECORD_WDATA1,135 PWRAP_DEW_RECORD_WDATA2,136 PWRAP_DEW_RECORD_WDATA3,137 PWRAP_DEW_RECORD_WDATA4,138 PWRAP_DEW_RECORD_WDATA5,139 PWRAP_DEW_RG_ADDR_TARGET,140 PWRAP_DEW_RG_ADDR_MASK,141 PWRAP_DEW_RG_WDATA_TARGET,142 PWRAP_DEW_RG_WDATA_MASK,143 PWRAP_DEW_RG_SPI_RECORD_CLR,144 PWRAP_DEW_RG_CMD_ALERT_CLR,145 146 /* MT6397 only regs */147 PWRAP_DEW_EVENT_OUT_EN,148 PWRAP_DEW_EVENT_SRC_EN,149 PWRAP_DEW_EVENT_SRC,150 PWRAP_DEW_EVENT_FLAG,151 PWRAP_DEW_MON_FLAG_SEL,152 PWRAP_DEW_EVENT_TEST,153 PWRAP_DEW_CIPHER_LOAD,154 PWRAP_DEW_CIPHER_START,155};156 157static const u32 mt6323_regs[] = {158 [PWRAP_DEW_BASE] = 0x0000,159 [PWRAP_DEW_DIO_EN] = 0x018a,160 [PWRAP_DEW_READ_TEST] = 0x018c,161 [PWRAP_DEW_WRITE_TEST] = 0x018e,162 [PWRAP_DEW_CRC_EN] = 0x0192,163 [PWRAP_DEW_CRC_VAL] = 0x0194,164 [PWRAP_DEW_MON_GRP_SEL] = 0x0196,165 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,166 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,167 [PWRAP_DEW_CIPHER_EN] = 0x019c,168 [PWRAP_DEW_CIPHER_RDY] = 0x019e,169 [PWRAP_DEW_CIPHER_MODE] = 0x01a0,170 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2,171 [PWRAP_DEW_RDDMY_NO] = 0x01a4,172};173 174static const u32 mt6331_regs[] = {175 [PWRAP_DEW_DIO_EN] = 0x018c,176 [PWRAP_DEW_READ_TEST] = 0x018e,177 [PWRAP_DEW_WRITE_TEST] = 0x0190,178 [PWRAP_DEW_CRC_SWRST] = 0x0192,179 [PWRAP_DEW_CRC_EN] = 0x0194,180 [PWRAP_DEW_CRC_VAL] = 0x0196,181 [PWRAP_DEW_MON_GRP_SEL] = 0x0198,182 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x019a,183 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019c,184 [PWRAP_DEW_CIPHER_EN] = 0x019e,185 [PWRAP_DEW_CIPHER_RDY] = 0x01a0,186 [PWRAP_DEW_CIPHER_MODE] = 0x01a2,187 [PWRAP_DEW_CIPHER_SWRST] = 0x01a4,188 [PWRAP_DEW_RDDMY_NO] = 0x01a6,189};190 191static const u32 mt6332_regs[] = {192 [PWRAP_DEW_DIO_EN] = 0x80f6,193 [PWRAP_DEW_READ_TEST] = 0x80f8,194 [PWRAP_DEW_WRITE_TEST] = 0x80fa,195 [PWRAP_DEW_CRC_SWRST] = 0x80fc,196 [PWRAP_DEW_CRC_EN] = 0x80fe,197 [PWRAP_DEW_CRC_VAL] = 0x8100,198 [PWRAP_DEW_MON_GRP_SEL] = 0x8102,199 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x8104,200 [PWRAP_DEW_CIPHER_IV_SEL] = 0x8106,201 [PWRAP_DEW_CIPHER_EN] = 0x8108,202 [PWRAP_DEW_CIPHER_RDY] = 0x810a,203 [PWRAP_DEW_CIPHER_MODE] = 0x810c,204 [PWRAP_DEW_CIPHER_SWRST] = 0x810e,205 [PWRAP_DEW_RDDMY_NO] = 0x8110,206};207 208static const u32 mt6351_regs[] = {209 [PWRAP_DEW_DIO_EN] = 0x02F2,210 [PWRAP_DEW_READ_TEST] = 0x02F4,211 [PWRAP_DEW_WRITE_TEST] = 0x02F6,212 [PWRAP_DEW_CRC_EN] = 0x02FA,213 [PWRAP_DEW_CRC_VAL] = 0x02FC,214 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300,215 [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302,216 [PWRAP_DEW_CIPHER_EN] = 0x0304,217 [PWRAP_DEW_CIPHER_RDY] = 0x0306,218 [PWRAP_DEW_CIPHER_MODE] = 0x0308,219 [PWRAP_DEW_CIPHER_SWRST] = 0x030A,220 [PWRAP_DEW_RDDMY_NO] = 0x030C,221};222 223static const u32 mt6357_regs[] = {224 [PWRAP_DEW_DIO_EN] = 0x040A,225 [PWRAP_DEW_READ_TEST] = 0x040C,226 [PWRAP_DEW_WRITE_TEST] = 0x040E,227 [PWRAP_DEW_CRC_EN] = 0x0412,228 [PWRAP_DEW_CRC_VAL] = 0x0414,229 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,230 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A,231 [PWRAP_DEW_CIPHER_EN] = 0x041C,232 [PWRAP_DEW_CIPHER_RDY] = 0x041E,233 [PWRAP_DEW_CIPHER_MODE] = 0x0420,234 [PWRAP_DEW_CIPHER_SWRST] = 0x0422,235 [PWRAP_DEW_RDDMY_NO] = 0x0424,236};237 238static const u32 mt6358_regs[] = {239 [PWRAP_SMT_CON1] = 0x0030,240 [PWRAP_DRV_CON1] = 0x0038,241 [PWRAP_FILTER_CON0] = 0x0040,242 [PWRAP_GPIO_PULLEN0_CLR] = 0x0098,243 [PWRAP_RG_SPI_CON0] = 0x0408,244 [PWRAP_RG_SPI_RECORD0] = 0x040a,245 [PWRAP_DEW_DIO_EN] = 0x040c,246 [PWRAP_DEW_READ_TEST] = 0x040e,247 [PWRAP_DEW_WRITE_TEST] = 0x0410,248 [PWRAP_DEW_CRC_EN] = 0x0414,249 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a,250 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c,251 [PWRAP_DEW_CIPHER_EN] = 0x041e,252 [PWRAP_DEW_CIPHER_RDY] = 0x0420,253 [PWRAP_DEW_CIPHER_MODE] = 0x0422,254 [PWRAP_DEW_CIPHER_SWRST] = 0x0424,255 [PWRAP_RG_SPI_CON2] = 0x0432,256 [PWRAP_RG_SPI_CON3] = 0x0434,257 [PWRAP_RG_SPI_CON4] = 0x0436,258 [PWRAP_RG_SPI_CON5] = 0x0438,259 [PWRAP_RG_SPI_CON6] = 0x043a,260 [PWRAP_RG_SPI_CON7] = 0x043c,261 [PWRAP_RG_SPI_CON8] = 0x043e,262 [PWRAP_RG_SPI_CON13] = 0x0448,263 [PWRAP_SPISLV_KEY] = 0x044a,264};265 266static const u32 mt6359_regs[] = {267 [PWRAP_DEW_RG_EN_RECORD] = 0x040a,268 [PWRAP_DEW_DIO_EN] = 0x040c,269 [PWRAP_DEW_READ_TEST] = 0x040e,270 [PWRAP_DEW_WRITE_TEST] = 0x0410,271 [PWRAP_DEW_CRC_SWRST] = 0x0412,272 [PWRAP_DEW_CRC_EN] = 0x0414,273 [PWRAP_DEW_CRC_VAL] = 0x0416,274 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,275 [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a,276 [PWRAP_DEW_CIPHER_EN] = 0x041c,277 [PWRAP_DEW_CIPHER_RDY] = 0x041e,278 [PWRAP_DEW_CIPHER_MODE] = 0x0420,279 [PWRAP_DEW_CIPHER_SWRST] = 0x0422,280 [PWRAP_DEW_RDDMY_NO] = 0x0424,281 [PWRAP_DEW_RECORD_CMD0] = 0x0428,282 [PWRAP_DEW_RECORD_CMD1] = 0x042a,283 [PWRAP_DEW_RECORD_CMD2] = 0x042c,284 [PWRAP_DEW_RECORD_CMD3] = 0x042e,285 [PWRAP_DEW_RECORD_CMD4] = 0x0430,286 [PWRAP_DEW_RECORD_CMD5] = 0x0432,287 [PWRAP_DEW_RECORD_WDATA0] = 0x0434,288 [PWRAP_DEW_RECORD_WDATA1] = 0x0436,289 [PWRAP_DEW_RECORD_WDATA2] = 0x0438,290 [PWRAP_DEW_RECORD_WDATA3] = 0x043a,291 [PWRAP_DEW_RECORD_WDATA4] = 0x043c,292 [PWRAP_DEW_RECORD_WDATA5] = 0x043e,293 [PWRAP_DEW_RG_ADDR_TARGET] = 0x0440,294 [PWRAP_DEW_RG_ADDR_MASK] = 0x0442,295 [PWRAP_DEW_RG_WDATA_TARGET] = 0x0444,296 [PWRAP_DEW_RG_WDATA_MASK] = 0x0446,297 [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,298 [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448,299 [PWRAP_SPISLV_KEY] = 0x044a,300};301 302static const u32 mt6397_regs[] = {303 [PWRAP_DEW_BASE] = 0xbc00,304 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,305 [PWRAP_DEW_DIO_EN] = 0xbc02,306 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,307 [PWRAP_DEW_EVENT_SRC] = 0xbc06,308 [PWRAP_DEW_EVENT_FLAG] = 0xbc08,309 [PWRAP_DEW_READ_TEST] = 0xbc0a,310 [PWRAP_DEW_WRITE_TEST] = 0xbc0c,311 [PWRAP_DEW_CRC_EN] = 0xbc0e,312 [PWRAP_DEW_CRC_VAL] = 0xbc10,313 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,314 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,315 [PWRAP_DEW_EVENT_TEST] = 0xbc16,316 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,317 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,318 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,319 [PWRAP_DEW_CIPHER_START] = 0xbc1e,320 [PWRAP_DEW_CIPHER_RDY] = 0xbc20,321 [PWRAP_DEW_CIPHER_MODE] = 0xbc22,322 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,323};324 325enum pwrap_regs {326 PWRAP_MUX_SEL,327 PWRAP_WRAP_EN,328 PWRAP_DIO_EN,329 PWRAP_SIDLY,330 PWRAP_CSHEXT_WRITE,331 PWRAP_CSHEXT_READ,332 PWRAP_CSLEXT_START,333 PWRAP_CSLEXT_END,334 PWRAP_STAUPD_PRD,335 PWRAP_STAUPD_GRPEN,336 PWRAP_STAUPD_MAN_TRIG,337 PWRAP_STAUPD_STA,338 PWRAP_WRAP_STA,339 PWRAP_HARB_INIT,340 PWRAP_HARB_HPRIO,341 PWRAP_HIPRIO_ARB_EN,342 PWRAP_HARB_STA0,343 PWRAP_HARB_STA1,344 PWRAP_MAN_EN,345 PWRAP_MAN_CMD,346 PWRAP_MAN_RDATA,347 PWRAP_MAN_VLDCLR,348 PWRAP_WACS0_EN,349 PWRAP_INIT_DONE0,350 PWRAP_WACS0_CMD,351 PWRAP_WACS0_RDATA,352 PWRAP_WACS0_VLDCLR,353 PWRAP_WACS1_EN,354 PWRAP_INIT_DONE1,355 PWRAP_WACS1_CMD,356 PWRAP_WACS1_RDATA,357 PWRAP_WACS1_VLDCLR,358 PWRAP_WACS2_EN,359 PWRAP_INIT_DONE2,360 PWRAP_WACS2_CMD,361 PWRAP_WACS2_RDATA,362 PWRAP_WACS2_VLDCLR,363 PWRAP_INT_EN,364 PWRAP_INT_FLG_RAW,365 PWRAP_INT_FLG,366 PWRAP_INT_CLR,367 PWRAP_SIG_ADR,368 PWRAP_SIG_MODE,369 PWRAP_SIG_VALUE,370 PWRAP_SIG_ERRVAL,371 PWRAP_CRC_EN,372 PWRAP_TIMER_EN,373 PWRAP_TIMER_STA,374 PWRAP_WDT_UNIT,375 PWRAP_WDT_SRC_EN,376 PWRAP_WDT_FLG,377 PWRAP_DEBUG_INT_SEL,378 PWRAP_CIPHER_KEY_SEL,379 PWRAP_CIPHER_IV_SEL,380 PWRAP_CIPHER_RDY,381 PWRAP_CIPHER_MODE,382 PWRAP_CIPHER_SWRST,383 PWRAP_DCM_EN,384 PWRAP_DCM_DBC_PRD,385 PWRAP_EINT_STA0_ADR,386 PWRAP_EINT_STA1_ADR,387 PWRAP_SWINF_2_WDATA_31_0,388 PWRAP_SWINF_2_RDATA_31_0,389 390 /* MT2701 only regs */391 PWRAP_ADC_CMD_ADDR,392 PWRAP_PWRAP_ADC_CMD,393 PWRAP_ADC_RDY_ADDR,394 PWRAP_ADC_RDATA_ADDR1,395 PWRAP_ADC_RDATA_ADDR2,396 397 /* MT7622 only regs */398 PWRAP_STA,399 PWRAP_CLR,400 PWRAP_DVFS_ADR8,401 PWRAP_DVFS_WDATA8,402 PWRAP_DVFS_ADR9,403 PWRAP_DVFS_WDATA9,404 PWRAP_DVFS_ADR10,405 PWRAP_DVFS_WDATA10,406 PWRAP_DVFS_ADR11,407 PWRAP_DVFS_WDATA11,408 PWRAP_DVFS_ADR12,409 PWRAP_DVFS_WDATA12,410 PWRAP_DVFS_ADR13,411 PWRAP_DVFS_WDATA13,412 PWRAP_DVFS_ADR14,413 PWRAP_DVFS_WDATA14,414 PWRAP_DVFS_ADR15,415 PWRAP_DVFS_WDATA15,416 PWRAP_EXT_CK,417 PWRAP_ADC_RDATA_ADDR,418 PWRAP_GPS_STA,419 PWRAP_SW_RST,420 PWRAP_DVFS_STEP_CTRL0,421 PWRAP_DVFS_STEP_CTRL1,422 PWRAP_DVFS_STEP_CTRL2,423 PWRAP_SPI2_CTRL,424 425 /* MT8135 only regs */426 PWRAP_CSHEXT,427 PWRAP_EVENT_IN_EN,428 PWRAP_EVENT_DST_EN,429 PWRAP_RRARB_INIT,430 PWRAP_RRARB_EN,431 PWRAP_RRARB_STA0,432 PWRAP_RRARB_STA1,433 PWRAP_EVENT_STA,434 PWRAP_EVENT_STACLR,435 PWRAP_CIPHER_LOAD,436 PWRAP_CIPHER_START,437 438 /* MT8173 only regs */439 PWRAP_RDDMY,440 PWRAP_SI_CK_CON,441 PWRAP_DVFS_ADR0,442 PWRAP_DVFS_WDATA0,443 PWRAP_DVFS_ADR1,444 PWRAP_DVFS_WDATA1,445 PWRAP_DVFS_ADR2,446 PWRAP_DVFS_WDATA2,447 PWRAP_DVFS_ADR3,448 PWRAP_DVFS_WDATA3,449 PWRAP_DVFS_ADR4,450 PWRAP_DVFS_WDATA4,451 PWRAP_DVFS_ADR5,452 PWRAP_DVFS_WDATA5,453 PWRAP_DVFS_ADR6,454 PWRAP_DVFS_WDATA6,455 PWRAP_DVFS_ADR7,456 PWRAP_DVFS_WDATA7,457 PWRAP_SPMINF_STA,458 PWRAP_CIPHER_EN,459 460 /* MT8183 only regs */461 PWRAP_SI_SAMPLE_CTRL,462 PWRAP_CSLEXT_WRITE,463 PWRAP_CSLEXT_READ,464 PWRAP_EXT_CK_WRITE,465 PWRAP_STAUPD_CTRL,466 PWRAP_WACS_P2P_EN,467 PWRAP_INIT_DONE_P2P,468 PWRAP_WACS_MD32_EN,469 PWRAP_INIT_DONE_MD32,470 PWRAP_INT1_EN,471 PWRAP_INT1_FLG,472 PWRAP_INT1_CLR,473 PWRAP_WDT_SRC_EN_1,474 PWRAP_INT_GPS_AUXADC_CMD_ADDR,475 PWRAP_INT_GPS_AUXADC_CMD,476 PWRAP_INT_GPS_AUXADC_RDATA_ADDR,477 PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,478 PWRAP_GPSINF_0_STA,479 PWRAP_GPSINF_1_STA,480 481 /* MT8516 only regs */482 PWRAP_OP_TYPE,483 PWRAP_MSB_FIRST,484};485 486static const int mt2701_regs[] = {487 [PWRAP_MUX_SEL] = 0x0,488 [PWRAP_WRAP_EN] = 0x4,489 [PWRAP_DIO_EN] = 0x8,490 [PWRAP_SIDLY] = 0xc,491 [PWRAP_RDDMY] = 0x18,492 [PWRAP_SI_CK_CON] = 0x1c,493 [PWRAP_CSHEXT_WRITE] = 0x20,494 [PWRAP_CSHEXT_READ] = 0x24,495 [PWRAP_CSLEXT_START] = 0x28,496 [PWRAP_CSLEXT_END] = 0x2c,497 [PWRAP_STAUPD_PRD] = 0x30,498 [PWRAP_STAUPD_GRPEN] = 0x34,499 [PWRAP_STAUPD_MAN_TRIG] = 0x38,500 [PWRAP_STAUPD_STA] = 0x3c,501 [PWRAP_WRAP_STA] = 0x44,502 [PWRAP_HARB_INIT] = 0x48,503 [PWRAP_HARB_HPRIO] = 0x4c,504 [PWRAP_HIPRIO_ARB_EN] = 0x50,505 [PWRAP_HARB_STA0] = 0x54,506 [PWRAP_HARB_STA1] = 0x58,507 [PWRAP_MAN_EN] = 0x5c,508 [PWRAP_MAN_CMD] = 0x60,509 [PWRAP_MAN_RDATA] = 0x64,510 [PWRAP_MAN_VLDCLR] = 0x68,511 [PWRAP_WACS0_EN] = 0x6c,512 [PWRAP_INIT_DONE0] = 0x70,513 [PWRAP_WACS0_CMD] = 0x74,514 [PWRAP_WACS0_RDATA] = 0x78,515 [PWRAP_WACS0_VLDCLR] = 0x7c,516 [PWRAP_WACS1_EN] = 0x80,517 [PWRAP_INIT_DONE1] = 0x84,518 [PWRAP_WACS1_CMD] = 0x88,519 [PWRAP_WACS1_RDATA] = 0x8c,520 [PWRAP_WACS1_VLDCLR] = 0x90,521 [PWRAP_WACS2_EN] = 0x94,522 [PWRAP_INIT_DONE2] = 0x98,523 [PWRAP_WACS2_CMD] = 0x9c,524 [PWRAP_WACS2_RDATA] = 0xa0,525 [PWRAP_WACS2_VLDCLR] = 0xa4,526 [PWRAP_INT_EN] = 0xa8,527 [PWRAP_INT_FLG_RAW] = 0xac,528 [PWRAP_INT_FLG] = 0xb0,529 [PWRAP_INT_CLR] = 0xb4,530 [PWRAP_SIG_ADR] = 0xb8,531 [PWRAP_SIG_MODE] = 0xbc,532 [PWRAP_SIG_VALUE] = 0xc0,533 [PWRAP_SIG_ERRVAL] = 0xc4,534 [PWRAP_CRC_EN] = 0xc8,535 [PWRAP_TIMER_EN] = 0xcc,536 [PWRAP_TIMER_STA] = 0xd0,537 [PWRAP_WDT_UNIT] = 0xd4,538 [PWRAP_WDT_SRC_EN] = 0xd8,539 [PWRAP_WDT_FLG] = 0xdc,540 [PWRAP_DEBUG_INT_SEL] = 0xe0,541 [PWRAP_DVFS_ADR0] = 0xe4,542 [PWRAP_DVFS_WDATA0] = 0xe8,543 [PWRAP_DVFS_ADR1] = 0xec,544 [PWRAP_DVFS_WDATA1] = 0xf0,545 [PWRAP_DVFS_ADR2] = 0xf4,546 [PWRAP_DVFS_WDATA2] = 0xf8,547 [PWRAP_DVFS_ADR3] = 0xfc,548 [PWRAP_DVFS_WDATA3] = 0x100,549 [PWRAP_DVFS_ADR4] = 0x104,550 [PWRAP_DVFS_WDATA4] = 0x108,551 [PWRAP_DVFS_ADR5] = 0x10c,552 [PWRAP_DVFS_WDATA5] = 0x110,553 [PWRAP_DVFS_ADR6] = 0x114,554 [PWRAP_DVFS_WDATA6] = 0x118,555 [PWRAP_DVFS_ADR7] = 0x11c,556 [PWRAP_DVFS_WDATA7] = 0x120,557 [PWRAP_CIPHER_KEY_SEL] = 0x124,558 [PWRAP_CIPHER_IV_SEL] = 0x128,559 [PWRAP_CIPHER_EN] = 0x12c,560 [PWRAP_CIPHER_RDY] = 0x130,561 [PWRAP_CIPHER_MODE] = 0x134,562 [PWRAP_CIPHER_SWRST] = 0x138,563 [PWRAP_DCM_EN] = 0x13c,564 [PWRAP_DCM_DBC_PRD] = 0x140,565 [PWRAP_ADC_CMD_ADDR] = 0x144,566 [PWRAP_PWRAP_ADC_CMD] = 0x148,567 [PWRAP_ADC_RDY_ADDR] = 0x14c,568 [PWRAP_ADC_RDATA_ADDR1] = 0x150,569 [PWRAP_ADC_RDATA_ADDR2] = 0x154,570};571 572static const int mt6765_regs[] = {573 [PWRAP_MUX_SEL] = 0x0,574 [PWRAP_WRAP_EN] = 0x4,575 [PWRAP_DIO_EN] = 0x8,576 [PWRAP_RDDMY] = 0x20,577 [PWRAP_CSHEXT_WRITE] = 0x24,578 [PWRAP_CSHEXT_READ] = 0x28,579 [PWRAP_CSLEXT_START] = 0x2C,580 [PWRAP_CSLEXT_END] = 0x30,581 [PWRAP_STAUPD_PRD] = 0x3C,582 [PWRAP_HARB_HPRIO] = 0x68,583 [PWRAP_HIPRIO_ARB_EN] = 0x6C,584 [PWRAP_MAN_EN] = 0x7C,585 [PWRAP_MAN_CMD] = 0x80,586 [PWRAP_WACS0_EN] = 0x8C,587 [PWRAP_WACS1_EN] = 0x94,588 [PWRAP_WACS2_EN] = 0x9C,589 [PWRAP_INIT_DONE2] = 0xA0,590 [PWRAP_WACS2_CMD] = 0xC20,591 [PWRAP_WACS2_RDATA] = 0xC24,592 [PWRAP_WACS2_VLDCLR] = 0xC28,593 [PWRAP_INT_EN] = 0xB4,594 [PWRAP_INT_FLG_RAW] = 0xB8,595 [PWRAP_INT_FLG] = 0xBC,596 [PWRAP_INT_CLR] = 0xC0,597 [PWRAP_TIMER_EN] = 0xE8,598 [PWRAP_WDT_UNIT] = 0xF0,599 [PWRAP_WDT_SRC_EN] = 0xF4,600 [PWRAP_DCM_EN] = 0x1DC,601 [PWRAP_DCM_DBC_PRD] = 0x1E0,602};603 604static const int mt6779_regs[] = {605 [PWRAP_MUX_SEL] = 0x0,606 [PWRAP_WRAP_EN] = 0x4,607 [PWRAP_DIO_EN] = 0x8,608 [PWRAP_RDDMY] = 0x20,609 [PWRAP_CSHEXT_WRITE] = 0x24,610 [PWRAP_CSHEXT_READ] = 0x28,611 [PWRAP_CSLEXT_WRITE] = 0x2C,612 [PWRAP_CSLEXT_READ] = 0x30,613 [PWRAP_EXT_CK_WRITE] = 0x34,614 [PWRAP_STAUPD_CTRL] = 0x3C,615 [PWRAP_STAUPD_GRPEN] = 0x40,616 [PWRAP_EINT_STA0_ADR] = 0x44,617 [PWRAP_HARB_HPRIO] = 0x68,618 [PWRAP_HIPRIO_ARB_EN] = 0x6C,619 [PWRAP_MAN_EN] = 0x7C,620 [PWRAP_MAN_CMD] = 0x80,621 [PWRAP_WACS0_EN] = 0x8C,622 [PWRAP_INIT_DONE0] = 0x90,623 [PWRAP_WACS1_EN] = 0x94,624 [PWRAP_WACS2_EN] = 0x9C,625 [PWRAP_INIT_DONE1] = 0x98,626 [PWRAP_INIT_DONE2] = 0xA0,627 [PWRAP_INT_EN] = 0xBC,628 [PWRAP_INT_FLG_RAW] = 0xC0,629 [PWRAP_INT_FLG] = 0xC4,630 [PWRAP_INT_CLR] = 0xC8,631 [PWRAP_INT1_EN] = 0xCC,632 [PWRAP_INT1_FLG] = 0xD4,633 [PWRAP_INT1_CLR] = 0xD8,634 [PWRAP_TIMER_EN] = 0xF0,635 [PWRAP_WDT_UNIT] = 0xF8,636 [PWRAP_WDT_SRC_EN] = 0xFC,637 [PWRAP_WDT_SRC_EN_1] = 0x100,638 [PWRAP_WACS2_CMD] = 0xC20,639 [PWRAP_WACS2_RDATA] = 0xC24,640 [PWRAP_WACS2_VLDCLR] = 0xC28,641};642 643static const int mt6795_regs[] = {644 [PWRAP_MUX_SEL] = 0x0,645 [PWRAP_WRAP_EN] = 0x4,646 [PWRAP_DIO_EN] = 0x8,647 [PWRAP_SIDLY] = 0xc,648 [PWRAP_RDDMY] = 0x10,649 [PWRAP_SI_CK_CON] = 0x14,650 [PWRAP_CSHEXT_WRITE] = 0x18,651 [PWRAP_CSHEXT_READ] = 0x1c,652 [PWRAP_CSLEXT_START] = 0x20,653 [PWRAP_CSLEXT_END] = 0x24,654 [PWRAP_STAUPD_PRD] = 0x28,655 [PWRAP_STAUPD_GRPEN] = 0x2c,656 [PWRAP_EINT_STA0_ADR] = 0x30,657 [PWRAP_EINT_STA1_ADR] = 0x34,658 [PWRAP_STAUPD_MAN_TRIG] = 0x40,659 [PWRAP_STAUPD_STA] = 0x44,660 [PWRAP_WRAP_STA] = 0x48,661 [PWRAP_HARB_INIT] = 0x4c,662 [PWRAP_HARB_HPRIO] = 0x50,663 [PWRAP_HIPRIO_ARB_EN] = 0x54,664 [PWRAP_HARB_STA0] = 0x58,665 [PWRAP_HARB_STA1] = 0x5c,666 [PWRAP_MAN_EN] = 0x60,667 [PWRAP_MAN_CMD] = 0x64,668 [PWRAP_MAN_RDATA] = 0x68,669 [PWRAP_MAN_VLDCLR] = 0x6c,670 [PWRAP_WACS0_EN] = 0x70,671 [PWRAP_INIT_DONE0] = 0x74,672 [PWRAP_WACS0_CMD] = 0x78,673 [PWRAP_WACS0_RDATA] = 0x7c,674 [PWRAP_WACS0_VLDCLR] = 0x80,675 [PWRAP_WACS1_EN] = 0x84,676 [PWRAP_INIT_DONE1] = 0x88,677 [PWRAP_WACS1_CMD] = 0x8c,678 [PWRAP_WACS1_RDATA] = 0x90,679 [PWRAP_WACS1_VLDCLR] = 0x94,680 [PWRAP_WACS2_EN] = 0x98,681 [PWRAP_INIT_DONE2] = 0x9c,682 [PWRAP_WACS2_CMD] = 0xa0,683 [PWRAP_WACS2_RDATA] = 0xa4,684 [PWRAP_WACS2_VLDCLR] = 0xa8,685 [PWRAP_INT_EN] = 0xac,686 [PWRAP_INT_FLG_RAW] = 0xb0,687 [PWRAP_INT_FLG] = 0xb4,688 [PWRAP_INT_CLR] = 0xb8,689 [PWRAP_SIG_ADR] = 0xbc,690 [PWRAP_SIG_MODE] = 0xc0,691 [PWRAP_SIG_VALUE] = 0xc4,692 [PWRAP_SIG_ERRVAL] = 0xc8,693 [PWRAP_CRC_EN] = 0xcc,694 [PWRAP_TIMER_EN] = 0xd0,695 [PWRAP_TIMER_STA] = 0xd4,696 [PWRAP_WDT_UNIT] = 0xd8,697 [PWRAP_WDT_SRC_EN] = 0xdc,698 [PWRAP_WDT_FLG] = 0xe0,699 [PWRAP_DEBUG_INT_SEL] = 0xe4,700 [PWRAP_DVFS_ADR0] = 0xe8,701 [PWRAP_DVFS_WDATA0] = 0xec,702 [PWRAP_DVFS_ADR1] = 0xf0,703 [PWRAP_DVFS_WDATA1] = 0xf4,704 [PWRAP_DVFS_ADR2] = 0xf8,705 [PWRAP_DVFS_WDATA2] = 0xfc,706 [PWRAP_DVFS_ADR3] = 0x100,707 [PWRAP_DVFS_WDATA3] = 0x104,708 [PWRAP_DVFS_ADR4] = 0x108,709 [PWRAP_DVFS_WDATA4] = 0x10c,710 [PWRAP_DVFS_ADR5] = 0x110,711 [PWRAP_DVFS_WDATA5] = 0x114,712 [PWRAP_DVFS_ADR6] = 0x118,713 [PWRAP_DVFS_WDATA6] = 0x11c,714 [PWRAP_DVFS_ADR7] = 0x120,715 [PWRAP_DVFS_WDATA7] = 0x124,716 [PWRAP_SPMINF_STA] = 0x128,717 [PWRAP_CIPHER_KEY_SEL] = 0x12c,718 [PWRAP_CIPHER_IV_SEL] = 0x130,719 [PWRAP_CIPHER_EN] = 0x134,720 [PWRAP_CIPHER_RDY] = 0x138,721 [PWRAP_CIPHER_MODE] = 0x13c,722 [PWRAP_CIPHER_SWRST] = 0x140,723 [PWRAP_DCM_EN] = 0x144,724 [PWRAP_DCM_DBC_PRD] = 0x148,725 [PWRAP_EXT_CK] = 0x14c,726};727 728static const int mt6797_regs[] = {729 [PWRAP_MUX_SEL] = 0x0,730 [PWRAP_WRAP_EN] = 0x4,731 [PWRAP_DIO_EN] = 0x8,732 [PWRAP_SIDLY] = 0xC,733 [PWRAP_RDDMY] = 0x10,734 [PWRAP_CSHEXT_WRITE] = 0x18,735 [PWRAP_CSHEXT_READ] = 0x1C,736 [PWRAP_CSLEXT_START] = 0x20,737 [PWRAP_CSLEXT_END] = 0x24,738 [PWRAP_STAUPD_PRD] = 0x28,739 [PWRAP_HARB_HPRIO] = 0x50,740 [PWRAP_HIPRIO_ARB_EN] = 0x54,741 [PWRAP_MAN_EN] = 0x60,742 [PWRAP_MAN_CMD] = 0x64,743 [PWRAP_WACS0_EN] = 0x70,744 [PWRAP_WACS1_EN] = 0x84,745 [PWRAP_WACS2_EN] = 0x98,746 [PWRAP_INIT_DONE2] = 0x9C,747 [PWRAP_WACS2_CMD] = 0xA0,748 [PWRAP_WACS2_RDATA] = 0xA4,749 [PWRAP_WACS2_VLDCLR] = 0xA8,750 [PWRAP_INT_EN] = 0xC0,751 [PWRAP_INT_FLG_RAW] = 0xC4,752 [PWRAP_INT_FLG] = 0xC8,753 [PWRAP_INT_CLR] = 0xCC,754 [PWRAP_TIMER_EN] = 0xF4,755 [PWRAP_WDT_UNIT] = 0xFC,756 [PWRAP_WDT_SRC_EN] = 0x100,757 [PWRAP_DCM_EN] = 0x1CC,758 [PWRAP_DCM_DBC_PRD] = 0x1D4,759};760 761static const int mt6873_regs[] = {762 [PWRAP_INIT_DONE2] = 0x0,763 [PWRAP_TIMER_EN] = 0x3E0,764 [PWRAP_INT_EN] = 0x448,765 [PWRAP_WACS2_CMD] = 0xC80,766 [PWRAP_SWINF_2_WDATA_31_0] = 0xC84,767 [PWRAP_SWINF_2_RDATA_31_0] = 0xC94,768 [PWRAP_WACS2_VLDCLR] = 0xCA4,769 [PWRAP_WACS2_RDATA] = 0xCA8,770};771 772static const int mt7622_regs[] = {773 [PWRAP_MUX_SEL] = 0x0,774 [PWRAP_WRAP_EN] = 0x4,775 [PWRAP_DIO_EN] = 0x8,776 [PWRAP_SIDLY] = 0xC,777 [PWRAP_RDDMY] = 0x10,778 [PWRAP_SI_CK_CON] = 0x14,779 [PWRAP_CSHEXT_WRITE] = 0x18,780 [PWRAP_CSHEXT_READ] = 0x1C,781 [PWRAP_CSLEXT_START] = 0x20,782 [PWRAP_CSLEXT_END] = 0x24,783 [PWRAP_STAUPD_PRD] = 0x28,784 [PWRAP_STAUPD_GRPEN] = 0x2C,785 [PWRAP_EINT_STA0_ADR] = 0x30,786 [PWRAP_EINT_STA1_ADR] = 0x34,787 [PWRAP_STA] = 0x38,788 [PWRAP_CLR] = 0x3C,789 [PWRAP_STAUPD_MAN_TRIG] = 0x40,790 [PWRAP_STAUPD_STA] = 0x44,791 [PWRAP_WRAP_STA] = 0x48,792 [PWRAP_HARB_INIT] = 0x4C,793 [PWRAP_HARB_HPRIO] = 0x50,794 [PWRAP_HIPRIO_ARB_EN] = 0x54,795 [PWRAP_HARB_STA0] = 0x58,796 [PWRAP_HARB_STA1] = 0x5C,797 [PWRAP_MAN_EN] = 0x60,798 [PWRAP_MAN_CMD] = 0x64,799 [PWRAP_MAN_RDATA] = 0x68,800 [PWRAP_MAN_VLDCLR] = 0x6C,801 [PWRAP_WACS0_EN] = 0x70,802 [PWRAP_INIT_DONE0] = 0x74,803 [PWRAP_WACS0_CMD] = 0x78,804 [PWRAP_WACS0_RDATA] = 0x7C,805 [PWRAP_WACS0_VLDCLR] = 0x80,806 [PWRAP_WACS1_EN] = 0x84,807 [PWRAP_INIT_DONE1] = 0x88,808 [PWRAP_WACS1_CMD] = 0x8C,809 [PWRAP_WACS1_RDATA] = 0x90,810 [PWRAP_WACS1_VLDCLR] = 0x94,811 [PWRAP_WACS2_EN] = 0x98,812 [PWRAP_INIT_DONE2] = 0x9C,813 [PWRAP_WACS2_CMD] = 0xA0,814 [PWRAP_WACS2_RDATA] = 0xA4,815 [PWRAP_WACS2_VLDCLR] = 0xA8,816 [PWRAP_INT_EN] = 0xAC,817 [PWRAP_INT_FLG_RAW] = 0xB0,818 [PWRAP_INT_FLG] = 0xB4,819 [PWRAP_INT_CLR] = 0xB8,820 [PWRAP_SIG_ADR] = 0xBC,821 [PWRAP_SIG_MODE] = 0xC0,822 [PWRAP_SIG_VALUE] = 0xC4,823 [PWRAP_SIG_ERRVAL] = 0xC8,824 [PWRAP_CRC_EN] = 0xCC,825 [PWRAP_TIMER_EN] = 0xD0,826 [PWRAP_TIMER_STA] = 0xD4,827 [PWRAP_WDT_UNIT] = 0xD8,828 [PWRAP_WDT_SRC_EN] = 0xDC,829 [PWRAP_WDT_FLG] = 0xE0,830 [PWRAP_DEBUG_INT_SEL] = 0xE4,831 [PWRAP_DVFS_ADR0] = 0xE8,832 [PWRAP_DVFS_WDATA0] = 0xEC,833 [PWRAP_DVFS_ADR1] = 0xF0,834 [PWRAP_DVFS_WDATA1] = 0xF4,835 [PWRAP_DVFS_ADR2] = 0xF8,836 [PWRAP_DVFS_WDATA2] = 0xFC,837 [PWRAP_DVFS_ADR3] = 0x100,838 [PWRAP_DVFS_WDATA3] = 0x104,839 [PWRAP_DVFS_ADR4] = 0x108,840 [PWRAP_DVFS_WDATA4] = 0x10C,841 [PWRAP_DVFS_ADR5] = 0x110,842 [PWRAP_DVFS_WDATA5] = 0x114,843 [PWRAP_DVFS_ADR6] = 0x118,844 [PWRAP_DVFS_WDATA6] = 0x11C,845 [PWRAP_DVFS_ADR7] = 0x120,846 [PWRAP_DVFS_WDATA7] = 0x124,847 [PWRAP_DVFS_ADR8] = 0x128,848 [PWRAP_DVFS_WDATA8] = 0x12C,849 [PWRAP_DVFS_ADR9] = 0x130,850 [PWRAP_DVFS_WDATA9] = 0x134,851 [PWRAP_DVFS_ADR10] = 0x138,852 [PWRAP_DVFS_WDATA10] = 0x13C,853 [PWRAP_DVFS_ADR11] = 0x140,854 [PWRAP_DVFS_WDATA11] = 0x144,855 [PWRAP_DVFS_ADR12] = 0x148,856 [PWRAP_DVFS_WDATA12] = 0x14C,857 [PWRAP_DVFS_ADR13] = 0x150,858 [PWRAP_DVFS_WDATA13] = 0x154,859 [PWRAP_DVFS_ADR14] = 0x158,860 [PWRAP_DVFS_WDATA14] = 0x15C,861 [PWRAP_DVFS_ADR15] = 0x160,862 [PWRAP_DVFS_WDATA15] = 0x164,863 [PWRAP_SPMINF_STA] = 0x168,864 [PWRAP_CIPHER_KEY_SEL] = 0x16C,865 [PWRAP_CIPHER_IV_SEL] = 0x170,866 [PWRAP_CIPHER_EN] = 0x174,867 [PWRAP_CIPHER_RDY] = 0x178,868 [PWRAP_CIPHER_MODE] = 0x17C,869 [PWRAP_CIPHER_SWRST] = 0x180,870 [PWRAP_DCM_EN] = 0x184,871 [PWRAP_DCM_DBC_PRD] = 0x188,872 [PWRAP_EXT_CK] = 0x18C,873 [PWRAP_ADC_CMD_ADDR] = 0x190,874 [PWRAP_PWRAP_ADC_CMD] = 0x194,875 [PWRAP_ADC_RDATA_ADDR] = 0x198,876 [PWRAP_GPS_STA] = 0x19C,877 [PWRAP_SW_RST] = 0x1A0,878 [PWRAP_DVFS_STEP_CTRL0] = 0x238,879 [PWRAP_DVFS_STEP_CTRL1] = 0x23C,880 [PWRAP_DVFS_STEP_CTRL2] = 0x240,881 [PWRAP_SPI2_CTRL] = 0x244,882};883 884static const int mt8135_regs[] = {885 [PWRAP_MUX_SEL] = 0x0,886 [PWRAP_WRAP_EN] = 0x4,887 [PWRAP_DIO_EN] = 0x8,888 [PWRAP_SIDLY] = 0xc,889 [PWRAP_CSHEXT] = 0x10,890 [PWRAP_CSHEXT_WRITE] = 0x14,891 [PWRAP_CSHEXT_READ] = 0x18,892 [PWRAP_CSLEXT_START] = 0x1c,893 [PWRAP_CSLEXT_END] = 0x20,894 [PWRAP_STAUPD_PRD] = 0x24,895 [PWRAP_STAUPD_GRPEN] = 0x28,896 [PWRAP_STAUPD_MAN_TRIG] = 0x2c,897 [PWRAP_STAUPD_STA] = 0x30,898 [PWRAP_EVENT_IN_EN] = 0x34,899 [PWRAP_EVENT_DST_EN] = 0x38,900 [PWRAP_WRAP_STA] = 0x3c,901 [PWRAP_RRARB_INIT] = 0x40,902 [PWRAP_RRARB_EN] = 0x44,903 [PWRAP_RRARB_STA0] = 0x48,904 [PWRAP_RRARB_STA1] = 0x4c,905 [PWRAP_HARB_INIT] = 0x50,906 [PWRAP_HARB_HPRIO] = 0x54,907 [PWRAP_HIPRIO_ARB_EN] = 0x58,908 [PWRAP_HARB_STA0] = 0x5c,909 [PWRAP_HARB_STA1] = 0x60,910 [PWRAP_MAN_EN] = 0x64,911 [PWRAP_MAN_CMD] = 0x68,912 [PWRAP_MAN_RDATA] = 0x6c,913 [PWRAP_MAN_VLDCLR] = 0x70,914 [PWRAP_WACS0_EN] = 0x74,915 [PWRAP_INIT_DONE0] = 0x78,916 [PWRAP_WACS0_CMD] = 0x7c,917 [PWRAP_WACS0_RDATA] = 0x80,918 [PWRAP_WACS0_VLDCLR] = 0x84,919 [PWRAP_WACS1_EN] = 0x88,920 [PWRAP_INIT_DONE1] = 0x8c,921 [PWRAP_WACS1_CMD] = 0x90,922 [PWRAP_WACS1_RDATA] = 0x94,923 [PWRAP_WACS1_VLDCLR] = 0x98,924 [PWRAP_WACS2_EN] = 0x9c,925 [PWRAP_INIT_DONE2] = 0xa0,926 [PWRAP_WACS2_CMD] = 0xa4,927 [PWRAP_WACS2_RDATA] = 0xa8,928 [PWRAP_WACS2_VLDCLR] = 0xac,929 [PWRAP_INT_EN] = 0xb0,930 [PWRAP_INT_FLG_RAW] = 0xb4,931 [PWRAP_INT_FLG] = 0xb8,932 [PWRAP_INT_CLR] = 0xbc,933 [PWRAP_SIG_ADR] = 0xc0,934 [PWRAP_SIG_MODE] = 0xc4,935 [PWRAP_SIG_VALUE] = 0xc8,936 [PWRAP_SIG_ERRVAL] = 0xcc,937 [PWRAP_CRC_EN] = 0xd0,938 [PWRAP_EVENT_STA] = 0xd4,939 [PWRAP_EVENT_STACLR] = 0xd8,940 [PWRAP_TIMER_EN] = 0xdc,941 [PWRAP_TIMER_STA] = 0xe0,942 [PWRAP_WDT_UNIT] = 0xe4,943 [PWRAP_WDT_SRC_EN] = 0xe8,944 [PWRAP_WDT_FLG] = 0xec,945 [PWRAP_DEBUG_INT_SEL] = 0xf0,946 [PWRAP_CIPHER_KEY_SEL] = 0x134,947 [PWRAP_CIPHER_IV_SEL] = 0x138,948 [PWRAP_CIPHER_LOAD] = 0x13c,949 [PWRAP_CIPHER_START] = 0x140,950 [PWRAP_CIPHER_RDY] = 0x144,951 [PWRAP_CIPHER_MODE] = 0x148,952 [PWRAP_CIPHER_SWRST] = 0x14c,953 [PWRAP_DCM_EN] = 0x15c,954 [PWRAP_DCM_DBC_PRD] = 0x160,955};956 957static const int mt8173_regs[] = {958 [PWRAP_MUX_SEL] = 0x0,959 [PWRAP_WRAP_EN] = 0x4,960 [PWRAP_DIO_EN] = 0x8,961 [PWRAP_SIDLY] = 0xc,962 [PWRAP_RDDMY] = 0x10,963 [PWRAP_SI_CK_CON] = 0x14,964 [PWRAP_CSHEXT_WRITE] = 0x18,965 [PWRAP_CSHEXT_READ] = 0x1c,966 [PWRAP_CSLEXT_START] = 0x20,967 [PWRAP_CSLEXT_END] = 0x24,968 [PWRAP_STAUPD_PRD] = 0x28,969 [PWRAP_STAUPD_GRPEN] = 0x2c,970 [PWRAP_STAUPD_MAN_TRIG] = 0x40,971 [PWRAP_STAUPD_STA] = 0x44,972 [PWRAP_WRAP_STA] = 0x48,973 [PWRAP_HARB_INIT] = 0x4c,974 [PWRAP_HARB_HPRIO] = 0x50,975 [PWRAP_HIPRIO_ARB_EN] = 0x54,976 [PWRAP_HARB_STA0] = 0x58,977 [PWRAP_HARB_STA1] = 0x5c,978 [PWRAP_MAN_EN] = 0x60,979 [PWRAP_MAN_CMD] = 0x64,980 [PWRAP_MAN_RDATA] = 0x68,981 [PWRAP_MAN_VLDCLR] = 0x6c,982 [PWRAP_WACS0_EN] = 0x70,983 [PWRAP_INIT_DONE0] = 0x74,984 [PWRAP_WACS0_CMD] = 0x78,985 [PWRAP_WACS0_RDATA] = 0x7c,986 [PWRAP_WACS0_VLDCLR] = 0x80,987 [PWRAP_WACS1_EN] = 0x84,988 [PWRAP_INIT_DONE1] = 0x88,989 [PWRAP_WACS1_CMD] = 0x8c,990 [PWRAP_WACS1_RDATA] = 0x90,991 [PWRAP_WACS1_VLDCLR] = 0x94,992 [PWRAP_WACS2_EN] = 0x98,993 [PWRAP_INIT_DONE2] = 0x9c,994 [PWRAP_WACS2_CMD] = 0xa0,995 [PWRAP_WACS2_RDATA] = 0xa4,996 [PWRAP_WACS2_VLDCLR] = 0xa8,997 [PWRAP_INT_EN] = 0xac,998 [PWRAP_INT_FLG_RAW] = 0xb0,999 [PWRAP_INT_FLG] = 0xb4,1000 [PWRAP_INT_CLR] = 0xb8,1001 [PWRAP_SIG_ADR] = 0xbc,1002 [PWRAP_SIG_MODE] = 0xc0,1003 [PWRAP_SIG_VALUE] = 0xc4,1004 [PWRAP_SIG_ERRVAL] = 0xc8,1005 [PWRAP_CRC_EN] = 0xcc,1006 [PWRAP_TIMER_EN] = 0xd0,1007 [PWRAP_TIMER_STA] = 0xd4,1008 [PWRAP_WDT_UNIT] = 0xd8,1009 [PWRAP_WDT_SRC_EN] = 0xdc,1010 [PWRAP_WDT_FLG] = 0xe0,1011 [PWRAP_DEBUG_INT_SEL] = 0xe4,1012 [PWRAP_DVFS_ADR0] = 0xe8,1013 [PWRAP_DVFS_WDATA0] = 0xec,1014 [PWRAP_DVFS_ADR1] = 0xf0,1015 [PWRAP_DVFS_WDATA1] = 0xf4,1016 [PWRAP_DVFS_ADR2] = 0xf8,1017 [PWRAP_DVFS_WDATA2] = 0xfc,1018 [PWRAP_DVFS_ADR3] = 0x100,1019 [PWRAP_DVFS_WDATA3] = 0x104,1020 [PWRAP_DVFS_ADR4] = 0x108,1021 [PWRAP_DVFS_WDATA4] = 0x10c,1022 [PWRAP_DVFS_ADR5] = 0x110,1023 [PWRAP_DVFS_WDATA5] = 0x114,1024 [PWRAP_DVFS_ADR6] = 0x118,1025 [PWRAP_DVFS_WDATA6] = 0x11c,1026 [PWRAP_DVFS_ADR7] = 0x120,1027 [PWRAP_DVFS_WDATA7] = 0x124,1028 [PWRAP_SPMINF_STA] = 0x128,1029 [PWRAP_CIPHER_KEY_SEL] = 0x12c,1030 [PWRAP_CIPHER_IV_SEL] = 0x130,1031 [PWRAP_CIPHER_EN] = 0x134,1032 [PWRAP_CIPHER_RDY] = 0x138,1033 [PWRAP_CIPHER_MODE] = 0x13c,1034 [PWRAP_CIPHER_SWRST] = 0x140,1035 [PWRAP_DCM_EN] = 0x144,1036 [PWRAP_DCM_DBC_PRD] = 0x148,1037};1038 1039static const int mt8183_regs[] = {1040 [PWRAP_MUX_SEL] = 0x0,1041 [PWRAP_WRAP_EN] = 0x4,1042 [PWRAP_DIO_EN] = 0x8,1043 [PWRAP_SI_SAMPLE_CTRL] = 0xC,1044 [PWRAP_RDDMY] = 0x14,1045 [PWRAP_CSHEXT_WRITE] = 0x18,1046 [PWRAP_CSHEXT_READ] = 0x1C,1047 [PWRAP_CSLEXT_WRITE] = 0x20,1048 [PWRAP_CSLEXT_READ] = 0x24,1049 [PWRAP_EXT_CK_WRITE] = 0x28,1050 [PWRAP_STAUPD_CTRL] = 0x30,1051 [PWRAP_STAUPD_GRPEN] = 0x34,1052 [PWRAP_EINT_STA0_ADR] = 0x38,1053 [PWRAP_HARB_HPRIO] = 0x5C,1054 [PWRAP_HIPRIO_ARB_EN] = 0x60,1055 [PWRAP_MAN_EN] = 0x70,1056 [PWRAP_MAN_CMD] = 0x74,1057 [PWRAP_WACS0_EN] = 0x80,1058 [PWRAP_INIT_DONE0] = 0x84,1059 [PWRAP_WACS1_EN] = 0x88,1060 [PWRAP_INIT_DONE1] = 0x8C,1061 [PWRAP_WACS2_EN] = 0x90,1062 [PWRAP_INIT_DONE2] = 0x94,1063 [PWRAP_WACS_P2P_EN] = 0xA0,1064 [PWRAP_INIT_DONE_P2P] = 0xA4,1065 [PWRAP_WACS_MD32_EN] = 0xA8,1066 [PWRAP_INIT_DONE_MD32] = 0xAC,1067 [PWRAP_INT_EN] = 0xB0,1068 [PWRAP_INT_FLG] = 0xB8,1069 [PWRAP_INT_CLR] = 0xBC,1070 [PWRAP_INT1_EN] = 0xC0,1071 [PWRAP_INT1_FLG] = 0xC8,1072 [PWRAP_INT1_CLR] = 0xCC,1073 [PWRAP_SIG_ADR] = 0xD0,1074 [PWRAP_CRC_EN] = 0xE0,1075 [PWRAP_TIMER_EN] = 0xE4,1076 [PWRAP_WDT_UNIT] = 0xEC,1077 [PWRAP_WDT_SRC_EN] = 0xF0,1078 [PWRAP_WDT_SRC_EN_1] = 0xF4,1079 [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC,1080 [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0,1081 [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4,1082 [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8,1083 [PWRAP_GPSINF_0_STA] = 0x1EC,1084 [PWRAP_GPSINF_1_STA] = 0x1F0,1085 [PWRAP_WACS2_CMD] = 0xC20,1086 [PWRAP_WACS2_RDATA] = 0xC24,1087 [PWRAP_WACS2_VLDCLR] = 0xC28,1088};1089 1090static const int mt8195_regs[] = {1091 [PWRAP_INIT_DONE2] = 0x0,1092 [PWRAP_STAUPD_CTRL] = 0x4C,1093 [PWRAP_TIMER_EN] = 0x3E4,1094 [PWRAP_INT_EN] = 0x420,1095 [PWRAP_INT_FLG] = 0x428,1096 [PWRAP_INT_CLR] = 0x42C,1097 [PWRAP_INT1_EN] = 0x450,1098 [PWRAP_INT1_FLG] = 0x458,1099 [PWRAP_INT1_CLR] = 0x45C,1100 [PWRAP_WACS2_CMD] = 0x880,1101 [PWRAP_SWINF_2_WDATA_31_0] = 0x884,1102 [PWRAP_SWINF_2_RDATA_31_0] = 0x894,1103 [PWRAP_WACS2_VLDCLR] = 0x8A4,1104 [PWRAP_WACS2_RDATA] = 0x8A8,1105};1106 1107static const int mt8365_regs[] = {1108 [PWRAP_MUX_SEL] = 0x0,1109 [PWRAP_WRAP_EN] = 0x4,1110 [PWRAP_DIO_EN] = 0x8,1111 [PWRAP_CSHEXT_WRITE] = 0x24,1112 [PWRAP_CSHEXT_READ] = 0x28,1113 [PWRAP_STAUPD_PRD] = 0x3c,1114 [PWRAP_STAUPD_GRPEN] = 0x40,1115 [PWRAP_STAUPD_MAN_TRIG] = 0x58,1116 [PWRAP_STAUPD_STA] = 0x5c,1117 [PWRAP_WRAP_STA] = 0x60,1118 [PWRAP_HARB_INIT] = 0x64,1119 [PWRAP_HARB_HPRIO] = 0x68,1120 [PWRAP_HIPRIO_ARB_EN] = 0x6c,1121 [PWRAP_HARB_STA0] = 0x70,1122 [PWRAP_HARB_STA1] = 0x74,1123 [PWRAP_MAN_EN] = 0x7c,1124 [PWRAP_MAN_CMD] = 0x80,1125 [PWRAP_MAN_RDATA] = 0x84,1126 [PWRAP_MAN_VLDCLR] = 0x88,1127 [PWRAP_WACS0_EN] = 0x8c,1128 [PWRAP_INIT_DONE0] = 0x90,1129 [PWRAP_WACS0_CMD] = 0xc00,1130 [PWRAP_WACS0_RDATA] = 0xc04,1131 [PWRAP_WACS0_VLDCLR] = 0xc08,1132 [PWRAP_WACS1_EN] = 0x94,1133 [PWRAP_INIT_DONE1] = 0x98,1134 [PWRAP_WACS2_EN] = 0x9c,1135 [PWRAP_INIT_DONE2] = 0xa0,1136 [PWRAP_WACS2_CMD] = 0xc20,1137 [PWRAP_WACS2_RDATA] = 0xc24,1138 [PWRAP_WACS2_VLDCLR] = 0xc28,1139 [PWRAP_INT_EN] = 0xb4,1140 [PWRAP_INT_FLG_RAW] = 0xb8,1141 [PWRAP_INT_FLG] = 0xbc,1142 [PWRAP_INT_CLR] = 0xc0,1143 [PWRAP_SIG_ADR] = 0xd4,1144 [PWRAP_SIG_MODE] = 0xd8,1145 [PWRAP_SIG_VALUE] = 0xdc,1146 [PWRAP_SIG_ERRVAL] = 0xe0,1147 [PWRAP_CRC_EN] = 0xe4,1148 [PWRAP_TIMER_EN] = 0xe8,1149 [PWRAP_TIMER_STA] = 0xec,1150 [PWRAP_WDT_UNIT] = 0xf0,1151 [PWRAP_WDT_SRC_EN] = 0xf4,1152 [PWRAP_WDT_FLG] = 0xfc,1153 [PWRAP_DEBUG_INT_SEL] = 0x104,1154 [PWRAP_CIPHER_KEY_SEL] = 0x1c4,1155 [PWRAP_CIPHER_IV_SEL] = 0x1c8,1156 [PWRAP_CIPHER_RDY] = 0x1d0,1157 [PWRAP_CIPHER_MODE] = 0x1d4,1158 [PWRAP_CIPHER_SWRST] = 0x1d8,1159 [PWRAP_DCM_EN] = 0x1dc,1160 [PWRAP_DCM_DBC_PRD] = 0x1e0,1161 [PWRAP_EINT_STA0_ADR] = 0x44,1162 [PWRAP_EINT_STA1_ADR] = 0x48,1163 [PWRAP_INT1_EN] = 0xc4,1164 [PWRAP_INT1_FLG] = 0xcc,1165 [PWRAP_INT1_CLR] = 0xd0,1166 [PWRAP_WDT_SRC_EN_1] = 0xf8,1167};1168 1169static const int mt8516_regs[] = {1170 [PWRAP_MUX_SEL] = 0x0,1171 [PWRAP_WRAP_EN] = 0x4,1172 [PWRAP_DIO_EN] = 0x8,1173 [PWRAP_SIDLY] = 0xc,1174 [PWRAP_RDDMY] = 0x10,1175 [PWRAP_SI_CK_CON] = 0x14,1176 [PWRAP_CSHEXT_WRITE] = 0x18,1177 [PWRAP_CSHEXT_READ] = 0x1c,1178 [PWRAP_CSLEXT_START] = 0x20,1179 [PWRAP_CSLEXT_END] = 0x24,1180 [PWRAP_STAUPD_PRD] = 0x28,1181 [PWRAP_STAUPD_GRPEN] = 0x2c,1182 [PWRAP_STAUPD_MAN_TRIG] = 0x40,1183 [PWRAP_STAUPD_STA] = 0x44,1184 [PWRAP_WRAP_STA] = 0x48,1185 [PWRAP_HARB_INIT] = 0x4c,1186 [PWRAP_HARB_HPRIO] = 0x50,1187 [PWRAP_HIPRIO_ARB_EN] = 0x54,1188 [PWRAP_HARB_STA0] = 0x58,1189 [PWRAP_HARB_STA1] = 0x5c,1190 [PWRAP_MAN_EN] = 0x60,1191 [PWRAP_MAN_CMD] = 0x64,1192 [PWRAP_MAN_RDATA] = 0x68,1193 [PWRAP_MAN_VLDCLR] = 0x6c,1194 [PWRAP_WACS0_EN] = 0x70,1195 [PWRAP_INIT_DONE0] = 0x74,1196 [PWRAP_WACS0_CMD] = 0x78,1197 [PWRAP_WACS0_RDATA] = 0x7c,1198 [PWRAP_WACS0_VLDCLR] = 0x80,1199 [PWRAP_WACS1_EN] = 0x84,1200 [PWRAP_INIT_DONE1] = 0x88,1201 [PWRAP_WACS1_CMD] = 0x8c,1202 [PWRAP_WACS1_RDATA] = 0x90,1203 [PWRAP_WACS1_VLDCLR] = 0x94,1204 [PWRAP_WACS2_EN] = 0x98,1205 [PWRAP_INIT_DONE2] = 0x9c,1206 [PWRAP_WACS2_CMD] = 0xa0,1207 [PWRAP_WACS2_RDATA] = 0xa4,1208 [PWRAP_WACS2_VLDCLR] = 0xa8,1209 [PWRAP_INT_EN] = 0xac,1210 [PWRAP_INT_FLG_RAW] = 0xb0,1211 [PWRAP_INT_FLG] = 0xb4,1212 [PWRAP_INT_CLR] = 0xb8,1213 [PWRAP_SIG_ADR] = 0xbc,1214 [PWRAP_SIG_MODE] = 0xc0,1215 [PWRAP_SIG_VALUE] = 0xc4,1216 [PWRAP_SIG_ERRVAL] = 0xc8,1217 [PWRAP_CRC_EN] = 0xcc,1218 [PWRAP_TIMER_EN] = 0xd0,1219 [PWRAP_TIMER_STA] = 0xd4,1220 [PWRAP_WDT_UNIT] = 0xd8,1221 [PWRAP_WDT_SRC_EN] = 0xdc,1222 [PWRAP_WDT_FLG] = 0xe0,1223 [PWRAP_DEBUG_INT_SEL] = 0xe4,1224 [PWRAP_DVFS_ADR0] = 0xe8,1225 [PWRAP_DVFS_WDATA0] = 0xec,1226 [PWRAP_DVFS_ADR1] = 0xf0,1227 [PWRAP_DVFS_WDATA1] = 0xf4,1228 [PWRAP_DVFS_ADR2] = 0xf8,1229 [PWRAP_DVFS_WDATA2] = 0xfc,1230 [PWRAP_DVFS_ADR3] = 0x100,1231 [PWRAP_DVFS_WDATA3] = 0x104,1232 [PWRAP_DVFS_ADR4] = 0x108,1233 [PWRAP_DVFS_WDATA4] = 0x10c,1234 [PWRAP_DVFS_ADR5] = 0x110,1235 [PWRAP_DVFS_WDATA5] = 0x114,1236 [PWRAP_DVFS_ADR6] = 0x118,1237 [PWRAP_DVFS_WDATA6] = 0x11c,1238 [PWRAP_DVFS_ADR7] = 0x120,1239 [PWRAP_DVFS_WDATA7] = 0x124,1240 [PWRAP_SPMINF_STA] = 0x128,1241 [PWRAP_CIPHER_KEY_SEL] = 0x12c,1242 [PWRAP_CIPHER_IV_SEL] = 0x130,1243 [PWRAP_CIPHER_EN] = 0x134,1244 [PWRAP_CIPHER_RDY] = 0x138,1245 [PWRAP_CIPHER_MODE] = 0x13c,1246 [PWRAP_CIPHER_SWRST] = 0x140,1247 [PWRAP_DCM_EN] = 0x144,1248 [PWRAP_DCM_DBC_PRD] = 0x148,1249 [PWRAP_SW_RST] = 0x168,1250 [PWRAP_OP_TYPE] = 0x16c,1251 [PWRAP_MSB_FIRST] = 0x170,1252};1253 1254static const int mt8186_regs[] = {1255 [PWRAP_MUX_SEL] = 0x0,1256 [PWRAP_WRAP_EN] = 0x4,1257 [PWRAP_DIO_EN] = 0x8,1258 [PWRAP_RDDMY] = 0x20,1259 [PWRAP_CSHEXT_WRITE] = 0x24,1260 [PWRAP_CSHEXT_READ] = 0x28,1261 [PWRAP_CSLEXT_WRITE] = 0x2C,1262 [PWRAP_CSLEXT_READ] = 0x30,1263 [PWRAP_EXT_CK_WRITE] = 0x34,1264 [PWRAP_STAUPD_CTRL] = 0x3C,1265 [PWRAP_STAUPD_GRPEN] = 0x40,1266 [PWRAP_EINT_STA0_ADR] = 0x44,1267 [PWRAP_EINT_STA1_ADR] = 0x48,1268 [PWRAP_INT_CLR] = 0xC8,1269 [PWRAP_INT_FLG] = 0xC4,1270 [PWRAP_MAN_EN] = 0x7C,1271 [PWRAP_MAN_CMD] = 0x80,1272 [PWRAP_WACS0_EN] = 0x8C,1273 [PWRAP_WACS1_EN] = 0x94,1274 [PWRAP_WACS2_EN] = 0x9C,1275 [PWRAP_INIT_DONE0] = 0x90,1276 [PWRAP_INIT_DONE1] = 0x98,1277 [PWRAP_INIT_DONE2] = 0xA0,1278 [PWRAP_INT_EN] = 0xBC,1279 [PWRAP_INT1_EN] = 0xCC,1280 [PWRAP_INT1_FLG] = 0xD4,1281 [PWRAP_INT1_CLR] = 0xD8,1282 [PWRAP_TIMER_EN] = 0xF0,1283 [PWRAP_WDT_UNIT] = 0xF8,1284 [PWRAP_WDT_SRC_EN] = 0xFC,1285 [PWRAP_WDT_SRC_EN_1] = 0x100,1286 [PWRAP_WDT_FLG] = 0x104,1287 [PWRAP_SPMINF_STA] = 0x1B4,1288 [PWRAP_DCM_EN] = 0x1EC,1289 [PWRAP_DCM_DBC_PRD] = 0x1F0,1290 [PWRAP_GPSINF_0_STA] = 0x204,1291 [PWRAP_GPSINF_1_STA] = 0x208,1292 [PWRAP_WACS0_CMD] = 0xC00,1293 [PWRAP_WACS0_RDATA] = 0xC04,1294 [PWRAP_WACS0_VLDCLR] = 0xC08,1295 [PWRAP_WACS1_CMD] = 0xC10,1296 [PWRAP_WACS1_RDATA] = 0xC14,1297 [PWRAP_WACS1_VLDCLR] = 0xC18,1298 [PWRAP_WACS2_CMD] = 0xC20,1299 [PWRAP_WACS2_RDATA] = 0xC24,1300 [PWRAP_WACS2_VLDCLR] = 0xC28,1301};1302 1303enum pmic_type {1304 PMIC_MT6323,1305 PMIC_MT6331,1306 PMIC_MT6332,1307 PMIC_MT6351,1308 PMIC_MT6357,1309 PMIC_MT6358,1310 PMIC_MT6359,1311 PMIC_MT6380,1312 PMIC_MT6397,1313};1314 1315enum pwrap_type {1316 PWRAP_MT2701,1317 PWRAP_MT6765,1318 PWRAP_MT6779,1319 PWRAP_MT6795,1320 PWRAP_MT6797,1321 PWRAP_MT6873,1322 PWRAP_MT7622,1323 PWRAP_MT8135,1324 PWRAP_MT8173,1325 PWRAP_MT8183,1326 PWRAP_MT8186,1327 PWRAP_MT8195,1328 PWRAP_MT8365,1329 PWRAP_MT8516,1330};1331 1332struct pmic_wrapper;1333 1334struct pwrap_slv_regops {1335 const struct regmap_config *regmap;1336 /*1337 * pwrap operations are highly associated with the PMIC types,1338 * so the pointers added increases flexibility allowing determination1339 * which type is used by the detection through device tree.1340 */1341 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);1342 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);1343};1344 1345/**1346 * struct pwrap_slv_type - PMIC device wrapper definitions1347 * @dew_regs: Device Wrapper (DeW) register offsets1348 * @type: PMIC Type (model)1349 * @comp_dew_regs: Device Wrapper (DeW) register offsets for companion device1350 * @comp_type: Companion PMIC Type (model)1351 * @regops: Register R/W ops1352 * @caps: Capability flags for the target device1353 */1354struct pwrap_slv_type {1355 const u32 *dew_regs;1356 enum pmic_type type;1357 const u32 *comp_dew_regs;1358 enum pmic_type comp_type;1359 const struct pwrap_slv_regops *regops;1360 u32 caps;1361};1362 1363struct pmic_wrapper {1364 struct device *dev;1365 void __iomem *base;1366 struct regmap *regmap;1367 const struct pmic_wrapper_type *master;1368 const struct pwrap_slv_type *slave;1369 struct reset_control *rstc;1370 1371 struct reset_control *rstc_bridge;1372 void __iomem *bridge_base;1373};1374 1375struct pmic_wrapper_type {1376 const int *regs;1377 enum pwrap_type type;1378 u32 arb_en_all;1379 u32 int_en_all;1380 u32 int1_en_all;1381 u32 spi_w;1382 u32 wdt_src;1383 /* Flags indicating the capability for the target pwrap */1384 u32 caps;1385 int (*init_reg_clock)(struct pmic_wrapper *wrp);1386 int (*init_soc_specific)(struct pmic_wrapper *wrp);1387};1388 1389static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)1390{1391 return readl(wrp->base + wrp->master->regs[reg]);1392}1393 1394static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)1395{1396 writel(val, wrp->base + wrp->master->regs[reg]);1397}1398 1399static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp)1400{1401 u32 val;1402 1403 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);1404 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))1405 return PWRAP_GET_WACS_ARB_FSM(val);1406 else1407 return PWRAP_GET_WACS_FSM(val);1408}1409 1410static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)1411{1412 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE;1413}1414 1415static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)1416{1417 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR;1418}1419 1420/*1421 * Timeout issue sometimes caused by the last read command1422 * failed because pmic wrap could not got the FSM_VLDCLR1423 * in time after finishing WACS2_CMD. It made state machine1424 * still on FSM_VLDCLR and timeout next time.1425 * Check the status of FSM and clear the vldclr to recovery the1426 * error.1427 */1428static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)1429{1430 if (pwrap_is_fsm_vldclr(wrp))1431 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);1432}1433 1434static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)1435{1436 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;1437}1438 1439static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)1440{1441 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);1442 1443 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&1444 (val & PWRAP_STATE_SYNC_IDLE0);1445}1446 1447static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)1448{1449 bool tmp;1450 int ret;1451 u32 val;1452 1453 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,1454 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);1455 if (ret) {1456 pwrap_leave_fsm_vldclr(wrp);1457 return ret;1458 }1459 1460 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))1461 val = adr;1462 else1463 val = (adr >> 1) << 16;1464 pwrap_writel(wrp, val, PWRAP_WACS2_CMD);1465 1466 ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp,1467 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);1468 if (ret)1469 return ret;1470 1471 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))1472 val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0);1473 else1474 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);1475 *rdata = PWRAP_GET_WACS_RDATA(val);1476 1477 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);1478 1479 return 0;1480}1481 1482static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)1483{1484 bool tmp;1485 int ret, msb;1486 1487 *rdata = 0;1488 for (msb = 0; msb < 2; msb++) {1489 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,1490 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);1491 1492 if (ret) {1493 pwrap_leave_fsm_vldclr(wrp);1494 return ret;1495 }1496 1497 pwrap_writel(wrp, ((msb << 30) | (adr << 16)),1498 PWRAP_WACS2_CMD);1499 1500 ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp,1501 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);1502 if (ret)1503 return ret;1504 1505 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,1506 PWRAP_WACS2_RDATA)) << (16 * msb));1507 1508 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);1509 }1510 1511 return 0;1512}1513 1514static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)1515{1516 return wrp->slave->regops->pwrap_read(wrp, adr, rdata);1517}1518 1519static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)1520{1521 bool tmp;1522 int ret;1523 1524 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,1525 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);1526 if (ret) {1527 pwrap_leave_fsm_vldclr(wrp);1528 return ret;1529 }1530 1531 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) {1532 pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0);1533 pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD);1534 } else {1535 pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata,1536 PWRAP_WACS2_CMD);1537 }1538 1539 return 0;1540}1541 1542static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)1543{1544 bool tmp;1545 int ret, msb, rdata;1546 1547 for (msb = 0; msb < 2; msb++) {1548 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,1549 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);1550 if (ret) {1551 pwrap_leave_fsm_vldclr(wrp);1552 return ret;1553 }1554 1555 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |1556 ((wdata >> (msb * 16)) & 0xffff),1557 PWRAP_WACS2_CMD);1558 1559 /*1560 * The pwrap_read operation is the requirement of hardware used1561 * for the synchronization between two successive 16-bit1562 * pwrap_writel operations composing one 32-bit bus writing.1563 * Otherwise, we'll find the result fails on the lower 16-bit1564 * pwrap writing.1565 */1566 if (!msb)1567 pwrap_read(wrp, adr, &rdata);1568 }1569 1570 return 0;1571}1572 1573static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)1574{1575 return wrp->slave->regops->pwrap_write(wrp, adr, wdata);1576}1577 1578static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)1579{1580 return pwrap_read(context, adr, rdata);1581}1582 1583static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)1584{1585 return pwrap_write(context, adr, wdata);1586}1587 1588static bool pwrap_pmic_read_test(struct pmic_wrapper *wrp, const u32 *dew_regs,1589 u16 read_test_val)1590{1591 bool is_success;1592 u32 rdata;1593 1594 pwrap_read(wrp, dew_regs[PWRAP_DEW_READ_TEST], &rdata);1595 is_success = ((rdata & U16_MAX) == read_test_val);1596 1597 return is_success;1598}1599 1600static int pwrap_reset_spislave(struct pmic_wrapper *wrp)1601{1602 bool tmp;1603 int ret, i;1604 1605 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);1606 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);1607 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);1608 pwrap_writel(wrp, 1, PWRAP_MAN_EN);1609 pwrap_writel(wrp, 0, PWRAP_DIO_EN);1610 1611 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,1612 PWRAP_MAN_CMD);1613 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,1614 PWRAP_MAN_CMD);1615 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,1616 PWRAP_MAN_CMD);1617 1618 for (i = 0; i < 4; i++)1619 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,1620 PWRAP_MAN_CMD);1621 1622 ret = readx_poll_timeout(pwrap_is_sync_idle, wrp, tmp, tmp,1623 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);1624 if (ret) {1625 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);1626 return ret;1627 }1628 1629 pwrap_writel(wrp, 0, PWRAP_MAN_EN);1630 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);1631 1632 return 0;1633}1634 1635/*1636 * pwrap_init_sidly - configure serial input delay1637 *1638 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns1639 * delay. Do a read test with all possible values and chose the best delay.1640 */1641static int pwrap_init_sidly(struct pmic_wrapper *wrp)1642{1643 u32 i;1644 u32 pass = 0;1645 bool read_ok;1646 signed char dly[16] = {1647 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 11648 };1649 1650 for (i = 0; i < 4; i++) {1651 pwrap_writel(wrp, i, PWRAP_SIDLY);1652 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs,1653 PWRAP_DEW_READ_TEST_VAL);1654 if (read_ok) {1655 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);1656 pass |= 1 << i;1657 }1658 }1659 1660 if (dly[pass] < 0) {1661 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",1662 pass);1663 return -EIO;1664 }1665 1666 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);1667 1668 return 0;1669}1670 1671static int pwrap_init_dual_io(struct pmic_wrapper *wrp)1672{1673 int ret;1674 bool read_ok, tmp;1675 bool comp_read_ok = true;1676 1677 /* Enable dual IO mode */1678 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);1679 if (wrp->slave->comp_dew_regs)1680 pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_DIO_EN], 1);1681 1682 /* Check IDLE & INIT_DONE in advance */1683 ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp,1684 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);1685 if (ret) {1686 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);1687 return ret;1688 }1689 1690 pwrap_writel(wrp, 1, PWRAP_DIO_EN);1691 1692 /* Read Test */1693 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_READ_TEST_VAL);1694 if (wrp->slave->comp_dew_regs)1695 comp_read_ok = pwrap_pmic_read_test(wrp, wrp->slave->comp_dew_regs,1696 PWRAP_DEW_COMP_READ_TEST_VAL);1697 if (!read_ok || !comp_read_ok) {1698 dev_err(wrp->dev, "Read failed on DIO mode. Main PMIC %s%s\n",1699 !read_ok ? "fail" : "success",1700 wrp->slave->comp_dew_regs && !comp_read_ok ?1701 ", Companion PMIC fail" : "");1702 return -EFAULT;1703 }1704 1705 return 0;1706}1707 1708/*1709 * pwrap_init_chip_select_ext is used to configure CS extension time for each1710 * phase during data transactions on the pwrap bus.1711 */1712static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,1713 u8 hext_read, u8 lext_start,1714 u8 lext_end)1715{1716 /*1717 * After finishing a write and read transaction, extends CS high time1718 * to be at least xT of BUS CLK as hext_write and hext_read specifies1719 * respectively.1720 */1721 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);1722 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);1723 1724 /*1725 * Extends CS low time after CSL and before CSH command to be at1726 * least xT of BUS CLK as lext_start and lext_end specifies1727 * respectively.1728 */1729 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);1730 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);1731}1732 1733static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)1734{1735 switch (wrp->master->type) {1736 case PWRAP_MT6795:1737 if (wrp->slave->type == PMIC_MT6331) {1738 const u32 *dew_regs = wrp->slave->dew_regs;1739 1740 pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);1741 1742 if (wrp->slave->comp_type == PMIC_MT6332) {1743 dew_regs = wrp->slave->comp_dew_regs;1744 pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);1745 }1746 }1747 pwrap_writel(wrp, 0x88, PWRAP_RDDMY);1748 pwrap_init_chip_select_ext(wrp, 15, 15, 15, 15);1749 break;1750 case PWRAP_MT8173:1751 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);1752 break;1753 case PWRAP_MT8135:1754 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);1755 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);1756 break;1757 default:1758 break;1759 }1760 1761 return 0;1762}1763 1764static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)1765{1766 switch (wrp->slave->type) {1767 case PMIC_MT6397:1768 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);1769 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);1770 break;1771 1772 case PMIC_MT6323:1773 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);1774 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],1775 0x8);1776 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);1777 break;1778 default:1779 break;1780 }1781 1782 return 0;1783}1784 1785static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)1786{1787 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;1788}1789 1790static bool __pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp, const u32 *dew_regs)1791{1792 u32 rdata;1793 int ret;1794 1795 ret = pwrap_read(wrp, dew_regs[PWRAP_DEW_CIPHER_RDY], &rdata);1796 if (ret)1797 return false;1798 1799 return rdata == 1;1800}1801 1802 1803static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)1804{1805 bool ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->dew_regs);1806 1807 if (!ret)1808 return ret;1809 1810 /* If there's any companion, wait for it to be ready too */1811 if (wrp->slave->comp_dew_regs)1812 ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->comp_dew_regs);1813 1814 return ret;1815}1816 1817static void pwrap_config_cipher(struct pmic_wrapper *wrp, const u32 *dew_regs)1818{1819 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);1820 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);1821 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);1822 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);1823}1824 1825static int pwrap_init_cipher(struct pmic_wrapper *wrp)1826{1827 int ret;1828 bool tmp;1829 u32 rdata = 0;1830 1831 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);1832 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);1833 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);1834 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);1835 1836 switch (wrp->master->type) {1837 case PWRAP_MT8135:1838 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);1839 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);1840 break;1841 case PWRAP_MT2701:1842 case PWRAP_MT6765:1843 case PWRAP_MT6779:1844 case PWRAP_MT6795:1845 case PWRAP_MT6797:1846 case PWRAP_MT8173:1847 case PWRAP_MT8186:1848 case PWRAP_MT8365:1849 case PWRAP_MT8516:1850 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);1851 break;1852 case PWRAP_MT7622:1853 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);1854 break;1855 case PWRAP_MT6873:1856 case PWRAP_MT8183:1857 case PWRAP_MT8195:1858 break;1859 }1860 1861 /* Config cipher mode @PMIC */1862 pwrap_config_cipher(wrp, wrp->slave->dew_regs);1863 1864 /* If there is any companion PMIC, configure cipher mode there too */1865 if (wrp->slave->comp_type > 0)1866 pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs);1867 1868 switch (wrp->slave->type) {1869 case PMIC_MT6397:1870 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],1871 0x1);1872 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],1873 0x1);1874 break;1875 case PMIC_MT6323:1876 case PMIC_MT6351:1877 case PMIC_MT6357:1878 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],1879 0x1);1880 break;1881 default:1882 break;1883 }1884 1885 /* wait for cipher data ready@AP */1886 ret = readx_poll_timeout(pwrap_is_cipher_ready, wrp, tmp, tmp,1887 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);1888 if (ret) {1889 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);1890 return ret;1891 }1892 1893 /* wait for cipher data ready@PMIC */1894 ret = readx_poll_timeout(pwrap_is_pmic_cipher_ready, wrp, tmp, tmp,1895 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);1896 if (ret) {1897 dev_err(wrp->dev,1898 "timeout waiting for cipher data ready@PMIC\n");1899 return ret;1900 }1901 1902 /* wait for cipher mode idle */1903 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);1904 ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp,1905 PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);1906 if (ret) {1907 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);1908 return ret;1909 }1910 1911 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);1912 1913 /* Write Test */1914 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],1915 PWRAP_DEW_WRITE_TEST_VAL) ||1916 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],1917 &rdata) ||1918 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {1919 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);1920 return -EFAULT;1921 }1922 1923 return 0;1924}1925 1926static int pwrap_init_security(struct pmic_wrapper *wrp)1927{1928 u32 crc_val;1929 int ret;1930 1931 /* Enable encryption */1932 ret = pwrap_init_cipher(wrp);1933 if (ret)1934 return ret;1935 1936 /* Signature checking - using CRC */1937 ret = pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);1938 if (ret == 0 && wrp->slave->comp_dew_regs)1939 ret = pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_EN], 0x1);1940 1941 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);1942 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);1943 1944 /* CRC value */1945 crc_val = wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL];1946 if (wrp->slave->comp_dew_regs)1947 crc_val |= wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_VAL] << 16;1948 1949 pwrap_writel(wrp, crc_val, PWRAP_SIG_ADR);1950 1951 /* PMIC Wrapper Arbiter priority */1952 pwrap_writel(wrp,1953 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);1954 1955 return 0;1956}1957 1958static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)1959{1960 /* enable pwrap events and pwrap bridge in AP side */1961 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);1962 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);1963 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);1964 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);1965 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);1966 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);1967 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);1968 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);1969 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);1970 1971 /* enable PMIC event out and sources */1972 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],1973 0x1) ||1974 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],1975 0xffff)) {1976 dev_err(wrp->dev, "enable dewrap fail\n");1977 return -EFAULT;1978 }1979 1980 return 0;1981}1982 1983static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)1984{1985 /* PMIC_DEWRAP enables */1986 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],1987 0x1) ||1988 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],1989 0xffff)) {1990 dev_err(wrp->dev, "enable dewrap fail\n");1991 return -EFAULT;1992 }1993 1994 return 0;1995}1996 1997static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)1998{1999 /* GPS_INTF initialization */2000 switch (wrp->slave->type) {2001 case PMIC_MT6323:2002 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);2003 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);2004 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);2005 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);2006 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);2007 break;2008 default:2009 break;2010 }2011 2012 return 0;2013}2014 2015static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp)2016{2017 pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN);2018 2019 if (wrp->slave->type == PMIC_MT6331)2020 pwrap_writel(wrp, 0x1b4, PWRAP_EINT_STA0_ADR);2021 2022 if (wrp->slave->comp_type == PMIC_MT6332)2023 pwrap_writel(wrp, 0x8112, PWRAP_EINT_STA1_ADR);2024 2025 return 0;2026}2027 2028static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)2029{2030 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);2031 /* enable 2wire SPI master */2032 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);2033 2034 return 0;2035}2036 2037static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)2038{2039 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);2040 2041 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);2042 pwrap_writel(wrp, 1, PWRAP_CRC_EN);2043 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);2044 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);2045 2046 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);2047 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);2048 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);2049 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);2050 2051 return 0;2052}2053 2054static int pwrap_init(struct pmic_wrapper *wrp)2055{2056 int ret;2057 2058 if (wrp->rstc)2059 reset_control_reset(wrp->rstc);2060 if (wrp->rstc_bridge)2061 reset_control_reset(wrp->rstc_bridge);2062 2063 switch (wrp->master->type) {2064 case PWRAP_MT6795:2065 fallthrough;2066 case PWRAP_MT8173:2067 /* Enable DCM */2068 pwrap_writel(wrp, 3, PWRAP_DCM_EN);2069 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);2070 break;2071 default:2072 break;2073 }2074 2075 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {2076 /* Reset SPI slave */2077 ret = pwrap_reset_spislave(wrp);2078 if (ret)2079 return ret;2080 }2081 2082 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);2083 2084 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);2085 2086 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);2087 2088 ret = wrp->master->init_reg_clock(wrp);2089 if (ret)2090 return ret;2091 2092 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {2093 /* Setup serial input delay */2094 ret = pwrap_init_sidly(wrp);2095 if (ret)2096 return ret;2097 }2098 2099 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {2100 /* Enable dual I/O mode */2101 ret = pwrap_init_dual_io(wrp);2102 if (ret)2103 return ret;2104 }2105 2106 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {2107 /* Enable security on bus */2108 ret = pwrap_init_security(wrp);2109 if (ret)2110 return ret;2111 }2112 2113 if (wrp->master->type == PWRAP_MT8135)2114 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);2115 2116 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);2117 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);2118 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);2119 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);2120 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);2121 2122 if (wrp->master->init_soc_specific) {2123 ret = wrp->master->init_soc_specific(wrp);2124 if (ret)2125 return ret;2126 }2127 2128 /* Setup the init done registers */2129 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);2130 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);2131 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);2132 2133 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {2134 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);2135 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);2136 }2137 2138 return 0;2139}2140 2141static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)2142{2143 u32 rdata;2144 struct pmic_wrapper *wrp = dev_id;2145 2146 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);2147 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);2148 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);2149 2150 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {2151 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);2152 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);2153 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);2154 }2155 2156 return IRQ_HANDLED;2157}2158 2159static const struct regmap_config pwrap_regmap_config16 = {2160 .reg_bits = 16,2161 .val_bits = 16,2162 .reg_stride = 2,2163 .reg_read = pwrap_regmap_read,2164 .reg_write = pwrap_regmap_write,2165 .max_register = 0xffff,2166};2167 2168static const struct regmap_config pwrap_regmap_config32 = {2169 .reg_bits = 32,2170 .val_bits = 32,2171 .reg_stride = 4,2172 .reg_read = pwrap_regmap_read,2173 .reg_write = pwrap_regmap_write,2174 .max_register = 0xffff,2175};2176 2177static const struct pwrap_slv_regops pwrap_regops16 = {2178 .pwrap_read = pwrap_read16,2179 .pwrap_write = pwrap_write16,2180 .regmap = &pwrap_regmap_config16,2181};2182 2183static const struct pwrap_slv_regops pwrap_regops32 = {2184 .pwrap_read = pwrap_read32,2185 .pwrap_write = pwrap_write32,2186 .regmap = &pwrap_regmap_config32,2187};2188 2189static const struct pwrap_slv_type pmic_mt6323 = {2190 .dew_regs = mt6323_regs,2191 .type = PMIC_MT6323,2192 .regops = &pwrap_regops16,2193 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |2194 PWRAP_SLV_CAP_SECURITY,2195};2196 2197static const struct pwrap_slv_type pmic_mt6331 = {2198 .dew_regs = mt6331_regs,2199 .type = PMIC_MT6331,2200 .comp_dew_regs = mt6332_regs,2201 .comp_type = PMIC_MT6332,2202 .regops = &pwrap_regops16,2203 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |2204 PWRAP_SLV_CAP_SECURITY,2205};2206 2207static const struct pwrap_slv_type pmic_mt6351 = {2208 .dew_regs = mt6351_regs,2209 .type = PMIC_MT6351,2210 .regops = &pwrap_regops16,2211 .caps = 0,2212};2213 2214static const struct pwrap_slv_type pmic_mt6357 = {2215 .dew_regs = mt6357_regs,2216 .type = PMIC_MT6357,2217 .regops = &pwrap_regops16,2218 .caps = 0,2219};2220 2221static const struct pwrap_slv_type pmic_mt6358 = {2222 .dew_regs = mt6358_regs,2223 .type = PMIC_MT6358,2224 .regops = &pwrap_regops16,2225 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,2226};2227 2228static const struct pwrap_slv_type pmic_mt6359 = {2229 .dew_regs = mt6359_regs,2230 .type = PMIC_MT6359,2231 .regops = &pwrap_regops16,2232 .caps = PWRAP_SLV_CAP_DUALIO,2233};2234 2235static const struct pwrap_slv_type pmic_mt6380 = {2236 .dew_regs = NULL,2237 .type = PMIC_MT6380,2238 .regops = &pwrap_regops32,2239 .caps = 0,2240};2241 2242static const struct pwrap_slv_type pmic_mt6397 = {2243 .dew_regs = mt6397_regs,2244 .type = PMIC_MT6397,2245 .regops = &pwrap_regops16,2246 .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |2247 PWRAP_SLV_CAP_SECURITY,2248};2249 2250static const struct of_device_id of_slave_match_tbl[] = {2251 { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 },2252 { .compatible = "mediatek,mt6331", .data = &pmic_mt6331 },2253 { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 },2254 { .compatible = "mediatek,mt6357", .data = &pmic_mt6357 },2255 { .compatible = "mediatek,mt6358", .data = &pmic_mt6358 },2256 { .compatible = "mediatek,mt6359", .data = &pmic_mt6359 },2257 2258 /* The MT6380 PMIC only implements a regulator, so we bind it2259 * directly instead of using a MFD.2260 */2261 { .compatible = "mediatek,mt6380-regulator", .data = &pmic_mt6380 },2262 { .compatible = "mediatek,mt6397", .data = &pmic_mt6397 },2263 { /* sentinel */ }2264};2265MODULE_DEVICE_TABLE(of, of_slave_match_tbl);2266 2267static const struct pmic_wrapper_type pwrap_mt2701 = {2268 .regs = mt2701_regs,2269 .type = PWRAP_MT2701,2270 .arb_en_all = 0x3f,2271 .int_en_all = ~(u32)(BIT(31) | BIT(2)),2272 .int1_en_all = 0,2273 .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,2274 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2275 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,2276 .init_reg_clock = pwrap_mt2701_init_reg_clock,2277 .init_soc_specific = pwrap_mt2701_init_soc_specific,2278};2279 2280static const struct pmic_wrapper_type pwrap_mt6765 = {2281 .regs = mt6765_regs,2282 .type = PWRAP_MT6765,2283 .arb_en_all = 0x3fd35,2284 .int_en_all = 0xffffffff,2285 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2286 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2287 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,2288 .init_reg_clock = pwrap_common_init_reg_clock,2289 .init_soc_specific = NULL,2290};2291 2292static const struct pmic_wrapper_type pwrap_mt6779 = {2293 .regs = mt6779_regs,2294 .type = PWRAP_MT6779,2295 .arb_en_all = 0xfbb7f,2296 .int_en_all = 0xfffffffe,2297 .int1_en_all = 0,2298 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2299 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2300 .caps = 0,2301 .init_reg_clock = pwrap_common_init_reg_clock,2302 .init_soc_specific = NULL,2303};2304 2305static const struct pmic_wrapper_type pwrap_mt6795 = {2306 .regs = mt6795_regs,2307 .type = PWRAP_MT6795,2308 .arb_en_all = 0x3f,2309 .int_en_all = ~(u32)(BIT(31) | BIT(2) | BIT(1)),2310 .int1_en_all = 0,2311 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2312 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,2313 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,2314 .init_reg_clock = pwrap_common_init_reg_clock,2315 .init_soc_specific = pwrap_mt6795_init_soc_specific,2316};2317 2318static const struct pmic_wrapper_type pwrap_mt6797 = {2319 .regs = mt6797_regs,2320 .type = PWRAP_MT6797,2321 .arb_en_all = 0x01fff,2322 .int_en_all = 0xffffffc6,2323 .int1_en_all = 0,2324 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2325 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2326 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,2327 .init_reg_clock = pwrap_common_init_reg_clock,2328 .init_soc_specific = NULL,2329};2330 2331static const struct pmic_wrapper_type pwrap_mt6873 = {2332 .regs = mt6873_regs,2333 .type = PWRAP_MT6873,2334 .arb_en_all = 0x777f,2335 .int_en_all = BIT(4) | BIT(5),2336 .int1_en_all = 0,2337 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2338 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2339 .caps = PWRAP_CAP_ARB,2340 .init_reg_clock = pwrap_common_init_reg_clock,2341 .init_soc_specific = NULL,2342};2343 2344static const struct pmic_wrapper_type pwrap_mt7622 = {2345 .regs = mt7622_regs,2346 .type = PWRAP_MT7622,2347 .arb_en_all = 0xff,2348 .int_en_all = ~(u32)BIT(31),2349 .int1_en_all = 0,2350 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2351 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2352 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,2353 .init_reg_clock = pwrap_common_init_reg_clock,2354 .init_soc_specific = pwrap_mt7622_init_soc_specific,2355};2356 2357static const struct pmic_wrapper_type pwrap_mt8135 = {2358 .regs = mt8135_regs,2359 .type = PWRAP_MT8135,2360 .arb_en_all = 0x1ff,2361 .int_en_all = ~(u32)(BIT(31) | BIT(1)),2362 .int1_en_all = 0,2363 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2364 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2365 .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,2366 .init_reg_clock = pwrap_common_init_reg_clock,2367 .init_soc_specific = pwrap_mt8135_init_soc_specific,2368};2369 2370static const struct pmic_wrapper_type pwrap_mt8173 = {2371 .regs = mt8173_regs,2372 .type = PWRAP_MT8173,2373 .arb_en_all = 0x3f,2374 .int_en_all = ~(u32)(BIT(31) | BIT(1)),2375 .int1_en_all = 0,2376 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2377 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,2378 .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,2379 .init_reg_clock = pwrap_common_init_reg_clock,2380 .init_soc_specific = pwrap_mt8173_init_soc_specific,2381};2382 2383static const struct pmic_wrapper_type pwrap_mt8183 = {2384 .regs = mt8183_regs,2385 .type = PWRAP_MT8183,2386 .arb_en_all = 0x3fa75,2387 .int_en_all = 0xffffffff,2388 .int1_en_all = 0xeef7ffff,2389 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2390 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2391 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,2392 .init_reg_clock = pwrap_common_init_reg_clock,2393 .init_soc_specific = pwrap_mt8183_init_soc_specific,2394};2395 2396static const struct pmic_wrapper_type pwrap_mt8195 = {2397 .regs = mt8195_regs,2398 .type = PWRAP_MT8195,2399 .arb_en_all = 0x777f, /* NEED CONFIRM */2400 .int_en_all = 0x180000, /* NEED CONFIRM */2401 .int1_en_all = 0,2402 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2403 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2404 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB,2405 .init_reg_clock = pwrap_common_init_reg_clock,2406 .init_soc_specific = NULL,2407};2408 2409static const struct pmic_wrapper_type pwrap_mt8365 = {2410 .regs = mt8365_regs,2411 .type = PWRAP_MT8365,2412 .arb_en_all = 0x3ffff,2413 .int_en_all = 0x7f1fffff,2414 .int1_en_all = 0x0,2415 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2416 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2417 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,2418 .init_reg_clock = pwrap_common_init_reg_clock,2419 .init_soc_specific = NULL,2420};2421 2422static const struct pmic_wrapper_type pwrap_mt8516 = {2423 .regs = mt8516_regs,2424 .type = PWRAP_MT8516,2425 .arb_en_all = 0xff,2426 .int_en_all = ~(u32)(BIT(31) | BIT(2)),2427 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2428 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2429 .caps = PWRAP_CAP_DCM,2430 .init_reg_clock = pwrap_mt2701_init_reg_clock,2431 .init_soc_specific = NULL,2432};2433 2434static const struct pmic_wrapper_type pwrap_mt8186 = {2435 .regs = mt8186_regs,2436 .type = PWRAP_MT8186,2437 .arb_en_all = 0xfb27f,2438 .int_en_all = 0xfffffffe, /* disable WatchDog Timeout for bit 1 */2439 .int1_en_all = 0x000017ff, /* disable Matching interrupt for bit 13 */2440 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,2441 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,2442 .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB_MT8186,2443 .init_reg_clock = pwrap_common_init_reg_clock,2444 .init_soc_specific = NULL,2445};2446 2447static const struct of_device_id of_pwrap_match_tbl[] = {2448 { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 },2449 { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 },2450 { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 },2451 { .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 },2452 { .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 },2453 { .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 },2454 { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 },2455 { .compatible = "mediatek,mt8135-pwrap", .data = &pwrap_mt8135 },2456 { .compatible = "mediatek,mt8173-pwrap", .data = &pwrap_mt8173 },2457 { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183 },2458 { .compatible = "mediatek,mt8186-pwrap", .data = &pwrap_mt8186 },2459 { .compatible = "mediatek,mt8195-pwrap", .data = &pwrap_mt8195 },2460 { .compatible = "mediatek,mt8365-pwrap", .data = &pwrap_mt8365 },2461 { .compatible = "mediatek,mt8516-pwrap", .data = &pwrap_mt8516 },2462 { /* sentinel */ }2463};2464MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);2465 2466static int pwrap_probe(struct platform_device *pdev)2467{2468 int ret, irq;2469 u32 mask_done;2470 struct pmic_wrapper *wrp;2471 struct clk_bulk_data *clk;2472 struct device_node *np = pdev->dev.of_node;2473 const struct of_device_id *of_slave_id = NULL;2474 2475 if (np->child)2476 of_slave_id = of_match_node(of_slave_match_tbl, np->child);2477 2478 if (!of_slave_id) {2479 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");2480 return -EINVAL;2481 }2482 2483 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);2484 if (!wrp)2485 return -ENOMEM;2486 2487 platform_set_drvdata(pdev, wrp);2488 2489 wrp->master = of_device_get_match_data(&pdev->dev);2490 wrp->slave = of_slave_id->data;2491 wrp->dev = &pdev->dev;2492 2493 wrp->base = devm_platform_ioremap_resource_byname(pdev, "pwrap");2494 if (IS_ERR(wrp->base))2495 return PTR_ERR(wrp->base);2496 2497 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {2498 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");2499 if (IS_ERR(wrp->rstc)) {2500 ret = PTR_ERR(wrp->rstc);2501 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);2502 return ret;2503 }2504 }2505 2506 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {2507 wrp->bridge_base = devm_platform_ioremap_resource_byname(pdev, "pwrap-bridge");2508 if (IS_ERR(wrp->bridge_base))2509 return PTR_ERR(wrp->bridge_base);2510 2511 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,2512 "pwrap-bridge");2513 if (IS_ERR(wrp->rstc_bridge)) {2514 ret = PTR_ERR(wrp->rstc_bridge);2515 dev_dbg(wrp->dev,2516 "cannot get pwrap-bridge reset: %d\n", ret);2517 return ret;2518 }2519 }2520 2521 ret = devm_clk_bulk_get_all_enable(wrp->dev, &clk);2522 if (ret)2523 return dev_err_probe(wrp->dev, ret,2524 "failed to get clocks\n");2525 2526 /* Enable internal dynamic clock */2527 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {2528 pwrap_writel(wrp, 1, PWRAP_DCM_EN);2529 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);2530 }2531 2532 /*2533 * The PMIC could already be initialized by the bootloader.2534 * Skip initialization here in this case.2535 */2536 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {2537 ret = pwrap_init(wrp);2538 if (ret) {2539 dev_dbg(wrp->dev, "init failed with %d\n", ret);2540 return ret;2541 }2542 }2543 2544 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))2545 mask_done = PWRAP_STATE_INIT_DONE1;2546 else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186))2547 mask_done = PWRAP_STATE_INIT_DONE0_MT8186;2548 else2549 mask_done = PWRAP_STATE_INIT_DONE0;2550 2551 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) {2552 dev_dbg(wrp->dev, "initialization isn't finished\n");2553 return -ENODEV;2554 }2555 2556 /* Initialize watchdog, may not be done by the bootloader */2557 if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))2558 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);2559 2560 /*2561 * Since STAUPD was not used on mt8173 platform,2562 * so STAUPD of WDT_SRC which should be turned off2563 */2564 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);2565 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))2566 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);2567 2568 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))2569 pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN);2570 else2571 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);2572 2573 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);2574 /*2575 * We add INT1 interrupt to handle starvation and request exception2576 * If we support it, we should enable it here.2577 */2578 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))2579 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);2580 2581 irq = platform_get_irq(pdev, 0);2582 if (irq < 0)2583 return irq;2584 2585 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,2586 IRQF_TRIGGER_HIGH,2587 "mt-pmic-pwrap", wrp);2588 if (ret)2589 return ret;2590 2591 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regops->regmap);2592 if (IS_ERR(wrp->regmap))2593 return PTR_ERR(wrp->regmap);2594 2595 ret = of_platform_populate(np, NULL, NULL, wrp->dev);2596 if (ret) {2597 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",2598 np);2599 return ret;2600 }2601 2602 return 0;2603}2604 2605static struct platform_driver pwrap_drv = {2606 .driver = {2607 .name = "mt-pmic-pwrap",2608 .of_match_table = of_pwrap_match_tbl,2609 },2610 .probe = pwrap_probe,2611};2612 2613module_platform_driver(pwrap_drv);2614 2615MODULE_AUTHOR("Flora Fu, MediaTek");2616MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");2617MODULE_LICENSE("GPL v2");2618