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1// SPDX-License-Identifier: GPL-2.02// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.3 4/* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */5#define __DISABLE_TRACE_MMIO__6 7#include <linux/acpi.h>8#include <linux/clk.h>9#include <linux/slab.h>10#include <linux/dma-mapping.h>11#include <linux/io.h>12#include <linux/module.h>13#include <linux/of.h>14#include <linux/of_platform.h>15#include <linux/pinctrl/consumer.h>16#include <linux/platform_device.h>17#include <linux/soc/qcom/geni-se.h>18 19/**20 * DOC: Overview21 *22 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced23 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper24 * controller. QUP Wrapper is designed to support various serial bus protocols25 * like UART, SPI, I2C, I3C, etc.26 */27 28/**29 * DOC: Hardware description30 *31 * GENI based QUP is a highly-flexible and programmable module for supporting32 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single33 * QUP module can provide upto 8 serial interfaces, using its internal34 * serial engines. The actual configuration is determined by the target35 * platform configuration. The protocol supported by each interface is36 * determined by the firmware loaded to the serial engine. Each SE consists37 * of a DMA Engine and GENI sub modules which enable serial engines to38 * support FIFO and DMA modes of operation.39 *40 *41 * +-----------------------------------------+42 * |QUP Wrapper |43 * | +----------------------------+ |44 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>45 * | | ... | | Interface46 * <---Clock Perf.----+ +----+-----------------------+ | |47 * State Interface | | Serial Engine 1 | | |48 * | | | | |49 * | | | | |50 * <--------AHB-------> | | | |51 * | | +----+ |52 * | | | |53 * | | | |54 * <------SE IRQ------+ +----------------------------+ |55 * | |56 * +-----------------------------------------+57 *58 * Figure 1: GENI based QUP Wrapper59 *60 * The GENI submodules include primary and secondary sequencers which are61 * used to drive TX & RX operations. On serial interfaces that operate using62 * master-slave model, primary sequencer drives both TX & RX operations. On63 * serial interfaces that operate using peer-to-peer model, primary sequencer64 * drives TX operation and secondary sequencer drives RX operation.65 */66 67/**68 * DOC: Software description69 *70 * GENI SE Wrapper driver is structured into 2 parts:71 *72 * geni_wrapper represents QUP Wrapper controller. This part of the driver73 * manages QUP Wrapper information such as hardware version, clock74 * performance table that is common to all the internal serial engines.75 *76 * geni_se represents serial engine. This part of the driver manages serial77 * engine information such as clocks, containing QUP Wrapper, etc. This part78 * of driver also supports operations (eg. initialize the concerned serial79 * engine, select between FIFO and DMA mode of operation etc.) that are80 * common to all the serial engines and are independent of serial interfaces.81 */82 83#define MAX_CLK_PERF_LEVEL 3284#define MAX_CLKS 285 86/**87 * struct geni_wrapper - Data structure to represent the QUP Wrapper Core88 * @dev: Device pointer of the QUP wrapper core89 * @base: Base address of this instance of QUP wrapper core90 * @clks: Handle to the primary & optional secondary AHB clocks91 * @num_clks: Count of clocks92 */93struct geni_wrapper {94 struct device *dev;95 void __iomem *base;96 struct clk_bulk_data clks[MAX_CLKS];97 unsigned int num_clks;98};99 100/**101 * struct geni_se_desc - Data structure to represent the QUP Wrapper resources102 * @clks: Name of the primary & optional secondary AHB clocks103 * @num_clks: Count of clock names104 */105struct geni_se_desc {106 unsigned int num_clks;107 const char * const *clks;108};109 110static const char * const icc_path_names[] = {"qup-core", "qup-config",111 "qup-memory"};112 113#define QUP_HW_VER_REG 0x4114 115/* Common SE registers */116#define GENI_INIT_CFG_REVISION 0x0117#define GENI_S_INIT_CFG_REVISION 0x4118#define GENI_OUTPUT_CTRL 0x24119#define GENI_CGC_CTRL 0x28120#define GENI_CLK_CTRL_RO 0x60121#define GENI_FW_S_REVISION_RO 0x6c122#define SE_GENI_BYTE_GRAN 0x254123#define SE_GENI_TX_PACKING_CFG0 0x260124#define SE_GENI_TX_PACKING_CFG1 0x264125#define SE_GENI_RX_PACKING_CFG0 0x284126#define SE_GENI_RX_PACKING_CFG1 0x288127#define SE_GENI_M_GP_LENGTH 0x910128#define SE_GENI_S_GP_LENGTH 0x914129#define SE_DMA_TX_PTR_L 0xc30130#define SE_DMA_TX_PTR_H 0xc34131#define SE_DMA_TX_ATTR 0xc38132#define SE_DMA_TX_LEN 0xc3c133#define SE_DMA_TX_IRQ_EN 0xc48134#define SE_DMA_TX_IRQ_EN_SET 0xc4c135#define SE_DMA_TX_IRQ_EN_CLR 0xc50136#define SE_DMA_TX_LEN_IN 0xc54137#define SE_DMA_TX_MAX_BURST 0xc5c138#define SE_DMA_RX_PTR_L 0xd30139#define SE_DMA_RX_PTR_H 0xd34140#define SE_DMA_RX_ATTR 0xd38141#define SE_DMA_RX_LEN 0xd3c142#define SE_DMA_RX_IRQ_EN 0xd48143#define SE_DMA_RX_IRQ_EN_SET 0xd4c144#define SE_DMA_RX_IRQ_EN_CLR 0xd50145#define SE_DMA_RX_LEN_IN 0xd54146#define SE_DMA_RX_MAX_BURST 0xd5c147#define SE_DMA_RX_FLUSH 0xd60148#define SE_GSI_EVENT_EN 0xe18149#define SE_IRQ_EN 0xe1c150#define SE_DMA_GENERAL_CFG 0xe30151 152/* GENI_OUTPUT_CTRL fields */153#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)154 155/* GENI_CGC_CTRL fields */156#define CFG_AHB_CLK_CGC_ON BIT(0)157#define CFG_AHB_WR_ACLK_CGC_ON BIT(1)158#define DATA_AHB_CLK_CGC_ON BIT(2)159#define SCLK_CGC_ON BIT(3)160#define TX_CLK_CGC_ON BIT(4)161#define RX_CLK_CGC_ON BIT(5)162#define EXT_CLK_CGC_ON BIT(6)163#define PROG_RAM_HCLK_OFF BIT(8)164#define PROG_RAM_SCLK_OFF BIT(9)165#define DEFAULT_CGC_EN GENMASK(6, 0)166 167/* SE_GSI_EVENT_EN fields */168#define DMA_RX_EVENT_EN BIT(0)169#define DMA_TX_EVENT_EN BIT(1)170#define GENI_M_EVENT_EN BIT(2)171#define GENI_S_EVENT_EN BIT(3)172 173/* SE_IRQ_EN fields */174#define DMA_RX_IRQ_EN BIT(0)175#define DMA_TX_IRQ_EN BIT(1)176#define GENI_M_IRQ_EN BIT(2)177#define GENI_S_IRQ_EN BIT(3)178 179/* SE_DMA_GENERAL_CFG */180#define DMA_RX_CLK_CGC_ON BIT(0)181#define DMA_TX_CLK_CGC_ON BIT(1)182#define DMA_AHB_SLV_CFG_ON BIT(2)183#define AHB_SEC_SLV_CLK_CGC_ON BIT(3)184#define DUMMY_RX_NON_BUFFERABLE BIT(4)185#define RX_DMA_ZERO_PADDING_EN BIT(5)186#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)187#define RX_DMA_IRQ_DELAY_SHFT 6188 189/**190 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version191 * @se: Pointer to the corresponding serial engine.192 *193 * Return: Hardware Version of the wrapper.194 */195u32 geni_se_get_qup_hw_version(struct geni_se *se)196{197 struct geni_wrapper *wrapper = se->wrapper;198 199 return readl_relaxed(wrapper->base + QUP_HW_VER_REG);200}201EXPORT_SYMBOL_GPL(geni_se_get_qup_hw_version);202 203static void geni_se_io_set_mode(void __iomem *base)204{205 u32 val;206 207 val = readl_relaxed(base + SE_IRQ_EN);208 val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN;209 val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN;210 writel_relaxed(val, base + SE_IRQ_EN);211 212 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);213 val &= ~GENI_DMA_MODE_EN;214 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);215 216 writel_relaxed(0, base + SE_GSI_EVENT_EN);217}218 219static void geni_se_io_init(void __iomem *base)220{221 u32 val;222 223 val = readl_relaxed(base + GENI_CGC_CTRL);224 val |= DEFAULT_CGC_EN;225 writel_relaxed(val, base + GENI_CGC_CTRL);226 227 val = readl_relaxed(base + SE_DMA_GENERAL_CFG);228 val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON;229 val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;230 writel_relaxed(val, base + SE_DMA_GENERAL_CFG);231 232 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);233 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);234}235 236static void geni_se_irq_clear(struct geni_se *se)237{238 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);239 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);240 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);241 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);242 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);243 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);244}245 246/**247 * geni_se_init() - Initialize the GENI serial engine248 * @se: Pointer to the concerned serial engine.249 * @rx_wm: Receive watermark, in units of FIFO words.250 * @rx_rfr: Ready-for-receive watermark, in units of FIFO words.251 *252 * This function is used to initialize the GENI serial engine, configure253 * receive watermark and ready-for-receive watermarks.254 */255void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)256{257 u32 val;258 259 geni_se_irq_clear(se);260 geni_se_io_init(se->base);261 geni_se_io_set_mode(se->base);262 263 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);264 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);265 266 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);267 val |= M_COMMON_GENI_M_IRQ_EN;268 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);269 270 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);271 val |= S_COMMON_GENI_S_IRQ_EN;272 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);273}274EXPORT_SYMBOL_GPL(geni_se_init);275 276static void geni_se_select_fifo_mode(struct geni_se *se)277{278 u32 proto = geni_se_read_proto(se);279 u32 val, val_old;280 281 geni_se_irq_clear(se);282 283 /* UART driver manages enabling / disabling interrupts internally */284 if (proto != GENI_SE_UART) {285 /* Non-UART use only primary sequencer so dont bother about S_IRQ */286 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);287 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;288 val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;289 if (val != val_old)290 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);291 }292 293 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);294 val &= ~GENI_DMA_MODE_EN;295 if (val != val_old)296 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);297}298 299static void geni_se_select_dma_mode(struct geni_se *se)300{301 u32 proto = geni_se_read_proto(se);302 u32 val, val_old;303 304 geni_se_irq_clear(se);305 306 /* UART driver manages enabling / disabling interrupts internally */307 if (proto != GENI_SE_UART) {308 /* Non-UART use only primary sequencer so dont bother about S_IRQ */309 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);310 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);311 val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);312 if (val != val_old)313 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);314 }315 316 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);317 val |= GENI_DMA_MODE_EN;318 if (val != val_old)319 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);320}321 322static void geni_se_select_gpi_mode(struct geni_se *se)323{324 u32 val;325 326 geni_se_irq_clear(se);327 328 writel(0, se->base + SE_IRQ_EN);329 330 val = readl(se->base + SE_GENI_M_IRQ_EN);331 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN |332 M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);333 writel(val, se->base + SE_GENI_M_IRQ_EN);334 335 writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN);336 337 val = readl(se->base + SE_GSI_EVENT_EN);338 val |= (DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVENT_EN);339 writel(val, se->base + SE_GSI_EVENT_EN);340}341 342/**343 * geni_se_select_mode() - Select the serial engine transfer mode344 * @se: Pointer to the concerned serial engine.345 * @mode: Transfer mode to be selected.346 */347void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)348{349 WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA && mode != GENI_GPI_DMA);350 351 switch (mode) {352 case GENI_SE_FIFO:353 geni_se_select_fifo_mode(se);354 break;355 case GENI_SE_DMA:356 geni_se_select_dma_mode(se);357 break;358 case GENI_GPI_DMA:359 geni_se_select_gpi_mode(se);360 break;361 case GENI_SE_INVALID:362 default:363 break;364 }365}366EXPORT_SYMBOL_GPL(geni_se_select_mode);367 368/**369 * DOC: Overview370 *371 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist372 * of up to 4 operations, each operation represented by 4 configuration vectors373 * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for374 * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO.375 * Refer to below examples for detailed bit-field description.376 *377 * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1378 *379 * +-----------+-------+-------+-------+-------+380 * | | vec_0 | vec_1 | vec_2 | vec_3 |381 * +-----------+-------+-------+-------+-------+382 * | start | 0x6 | 0xe | 0x16 | 0x1e |383 * | direction | 1 | 1 | 1 | 1 |384 * | length | 6 | 6 | 6 | 6 |385 * | stop | 0 | 0 | 0 | 1 |386 * +-----------+-------+-------+-------+-------+387 *388 * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0389 *390 * +-----------+-------+-------+-------+-------+391 * | | vec_0 | vec_1 | vec_2 | vec_3 |392 * +-----------+-------+-------+-------+-------+393 * | start | 0x0 | 0x8 | 0x10 | 0x18 |394 * | direction | 0 | 0 | 0 | 0 |395 * | length | 7 | 6 | 7 | 6 |396 * | stop | 0 | 0 | 0 | 1 |397 * +-----------+-------+-------+-------+-------+398 *399 * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1400 *401 * +-----------+-------+-------+-------+-------+402 * | | vec_0 | vec_1 | vec_2 | vec_3 |403 * +-----------+-------+-------+-------+-------+404 * | start | 0x16 | 0xe | 0x6 | 0x0 |405 * | direction | 1 | 1 | 1 | 1 |406 * | length | 7 | 7 | 6 | 0 |407 * | stop | 0 | 0 | 1 | 0 |408 * +-----------+-------+-------+-------+-------+409 *410 */411 412#define NUM_PACKING_VECTORS 4413#define PACKING_START_SHIFT 5414#define PACKING_DIR_SHIFT 4415#define PACKING_LEN_SHIFT 1416#define PACKING_STOP_BIT BIT(0)417#define PACKING_VECTOR_SHIFT 10418/**419 * geni_se_config_packing() - Packing configuration of the serial engine420 * @se: Pointer to the concerned serial engine421 * @bpw: Bits of data per transfer word.422 * @pack_words: Number of words per fifo element.423 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.424 * @tx_cfg: Flag to configure the TX Packing.425 * @rx_cfg: Flag to configure the RX Packing.426 *427 * This function is used to configure the packing rules for the current428 * transfer.429 */430void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,431 bool msb_to_lsb, bool tx_cfg, bool rx_cfg)432{433 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0};434 int len;435 int temp_bpw = bpw;436 int idx_start = msb_to_lsb ? bpw - 1 : 0;437 int idx = idx_start;438 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE;439 int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE);440 int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE;441 int i;442 443 if (iter <= 0 || iter > NUM_PACKING_VECTORS)444 return;445 446 for (i = 0; i < iter; i++) {447 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1;448 cfg[i] = idx << PACKING_START_SHIFT;449 cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT;450 cfg[i] |= len << PACKING_LEN_SHIFT;451 452 if (temp_bpw <= BITS_PER_BYTE) {453 idx = ((i + 1) * BITS_PER_BYTE) + idx_start;454 temp_bpw = bpw;455 } else {456 idx = idx + idx_delta;457 temp_bpw = temp_bpw - BITS_PER_BYTE;458 }459 }460 cfg[iter - 1] |= PACKING_STOP_BIT;461 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT);462 cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT);463 464 if (tx_cfg) {465 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);466 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);467 }468 if (rx_cfg) {469 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);470 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);471 }472 473 /*474 * Number of protocol words in each FIFO entry475 * 0 - 4x8, four words in each entry, max word size of 8 bits476 * 1 - 2x16, two words in each entry, max word size of 16 bits477 * 2 - 1x32, one word in each entry, max word size of 32 bits478 * 3 - undefined479 */480 if (pack_words || bpw == 32)481 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);482}483EXPORT_SYMBOL_GPL(geni_se_config_packing);484 485static void geni_se_clks_off(struct geni_se *se)486{487 struct geni_wrapper *wrapper = se->wrapper;488 489 clk_disable_unprepare(se->clk);490 clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks);491}492 493/**494 * geni_se_resources_off() - Turn off resources associated with the serial495 * engine496 * @se: Pointer to the concerned serial engine.497 *498 * Return: 0 on success, standard Linux error codes on failure/error.499 */500int geni_se_resources_off(struct geni_se *se)501{502 int ret;503 504 if (has_acpi_companion(se->dev))505 return 0;506 507 ret = pinctrl_pm_select_sleep_state(se->dev);508 if (ret)509 return ret;510 511 geni_se_clks_off(se);512 return 0;513}514EXPORT_SYMBOL_GPL(geni_se_resources_off);515 516static int geni_se_clks_on(struct geni_se *se)517{518 int ret;519 struct geni_wrapper *wrapper = se->wrapper;520 521 ret = clk_bulk_prepare_enable(wrapper->num_clks, wrapper->clks);522 if (ret)523 return ret;524 525 ret = clk_prepare_enable(se->clk);526 if (ret)527 clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks);528 return ret;529}530 531/**532 * geni_se_resources_on() - Turn on resources associated with the serial533 * engine534 * @se: Pointer to the concerned serial engine.535 *536 * Return: 0 on success, standard Linux error codes on failure/error.537 */538int geni_se_resources_on(struct geni_se *se)539{540 int ret;541 542 if (has_acpi_companion(se->dev))543 return 0;544 545 ret = geni_se_clks_on(se);546 if (ret)547 return ret;548 549 ret = pinctrl_pm_select_default_state(se->dev);550 if (ret)551 geni_se_clks_off(se);552 553 return ret;554}555EXPORT_SYMBOL_GPL(geni_se_resources_on);556 557/**558 * geni_se_clk_tbl_get() - Get the clock table to program DFS559 * @se: Pointer to the concerned serial engine.560 * @tbl: Table in which the output is returned.561 *562 * This function is called by the protocol drivers to determine the different563 * clock frequencies supported by serial engine core clock. The protocol564 * drivers use the output to determine the clock frequency index to be565 * programmed into DFS.566 *567 * Return: number of valid performance levels in the table on success,568 * standard Linux error codes on failure.569 */570int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)571{572 long freq = 0;573 int i;574 575 if (se->clk_perf_tbl) {576 *tbl = se->clk_perf_tbl;577 return se->num_clk_levels;578 }579 580 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL,581 sizeof(*se->clk_perf_tbl),582 GFP_KERNEL);583 if (!se->clk_perf_tbl)584 return -ENOMEM;585 586 for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) {587 freq = clk_round_rate(se->clk, freq + 1);588 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1])589 break;590 se->clk_perf_tbl[i] = freq;591 }592 se->num_clk_levels = i;593 *tbl = se->clk_perf_tbl;594 return se->num_clk_levels;595}596EXPORT_SYMBOL_GPL(geni_se_clk_tbl_get);597 598/**599 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency600 * @se: Pointer to the concerned serial engine.601 * @req_freq: Requested clock frequency.602 * @index: Index of the resultant frequency in the table.603 * @res_freq: Resultant frequency of the source clock.604 * @exact: Flag to indicate exact multiple requirement of the requested605 * frequency.606 *607 * This function is called by the protocol drivers to determine the best match608 * of the requested frequency as provided by the serial engine clock in order609 * to meet the performance requirements.610 *611 * If we return success:612 * - if @exact is true then @res_freq / <an_integer> == @req_freq613 * - if @exact is false then @res_freq / <an_integer> <= @req_freq614 *615 * Return: 0 on success, standard Linux error codes on failure.616 */617int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,618 unsigned int *index, unsigned long *res_freq,619 bool exact)620{621 unsigned long *tbl;622 int num_clk_levels;623 int i;624 unsigned long best_delta;625 unsigned long new_delta;626 unsigned int divider;627 628 num_clk_levels = geni_se_clk_tbl_get(se, &tbl);629 if (num_clk_levels < 0)630 return num_clk_levels;631 632 if (num_clk_levels == 0)633 return -EINVAL;634 635 best_delta = ULONG_MAX;636 for (i = 0; i < num_clk_levels; i++) {637 divider = DIV_ROUND_UP(tbl[i], req_freq);638 new_delta = req_freq - tbl[i] / divider;639 if (new_delta < best_delta) {640 /* We have a new best! */641 *index = i;642 *res_freq = tbl[i];643 644 /* If the new best is exact then we're done */645 if (new_delta == 0)646 return 0;647 648 /* Record how close we got */649 best_delta = new_delta;650 }651 }652 653 if (exact)654 return -EINVAL;655 656 return 0;657}658EXPORT_SYMBOL_GPL(geni_se_clk_freq_match);659 660#define GENI_SE_DMA_DONE_EN BIT(0)661#define GENI_SE_DMA_EOT_EN BIT(1)662#define GENI_SE_DMA_AHB_ERR_EN BIT(2)663#define GENI_SE_DMA_EOT_BUF BIT(0)664 665/**666 * geni_se_tx_init_dma() - Initiate TX DMA transfer on the serial engine667 * @se: Pointer to the concerned serial engine.668 * @iova: Mapped DMA address.669 * @len: Length of the TX buffer.670 *671 * This function is used to initiate DMA TX transfer.672 */673void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len)674{675 u32 val;676 677 val = GENI_SE_DMA_DONE_EN;678 val |= GENI_SE_DMA_EOT_EN;679 val |= GENI_SE_DMA_AHB_ERR_EN;680 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);681 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_TX_PTR_L);682 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_TX_PTR_H);683 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);684 writel(len, se->base + SE_DMA_TX_LEN);685}686EXPORT_SYMBOL_GPL(geni_se_tx_init_dma);687 688/**689 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer690 * @se: Pointer to the concerned serial engine.691 * @buf: Pointer to the TX buffer.692 * @len: Length of the TX buffer.693 * @iova: Pointer to store the mapped DMA address.694 *695 * This function is used to prepare the buffers for DMA TX.696 *697 * Return: 0 on success, standard Linux error codes on failure.698 */699int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,700 dma_addr_t *iova)701{702 struct geni_wrapper *wrapper = se->wrapper;703 704 if (!wrapper)705 return -EINVAL;706 707 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE);708 if (dma_mapping_error(wrapper->dev, *iova))709 return -EIO;710 711 geni_se_tx_init_dma(se, *iova, len);712 return 0;713}714EXPORT_SYMBOL_GPL(geni_se_tx_dma_prep);715 716/**717 * geni_se_rx_init_dma() - Initiate RX DMA transfer on the serial engine718 * @se: Pointer to the concerned serial engine.719 * @iova: Mapped DMA address.720 * @len: Length of the RX buffer.721 *722 * This function is used to initiate DMA RX transfer.723 */724void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len)725{726 u32 val;727 728 val = GENI_SE_DMA_DONE_EN;729 val |= GENI_SE_DMA_EOT_EN;730 val |= GENI_SE_DMA_AHB_ERR_EN;731 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);732 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_RX_PTR_L);733 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_RX_PTR_H);734 /* RX does not have EOT buffer type bit. So just reset RX_ATTR */735 writel_relaxed(0, se->base + SE_DMA_RX_ATTR);736 writel(len, se->base + SE_DMA_RX_LEN);737}738EXPORT_SYMBOL_GPL(geni_se_rx_init_dma);739 740/**741 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer742 * @se: Pointer to the concerned serial engine.743 * @buf: Pointer to the RX buffer.744 * @len: Length of the RX buffer.745 * @iova: Pointer to store the mapped DMA address.746 *747 * This function is used to prepare the buffers for DMA RX.748 *749 * Return: 0 on success, standard Linux error codes on failure.750 */751int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,752 dma_addr_t *iova)753{754 struct geni_wrapper *wrapper = se->wrapper;755 756 if (!wrapper)757 return -EINVAL;758 759 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE);760 if (dma_mapping_error(wrapper->dev, *iova))761 return -EIO;762 763 geni_se_rx_init_dma(se, *iova, len);764 return 0;765}766EXPORT_SYMBOL_GPL(geni_se_rx_dma_prep);767 768/**769 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer770 * @se: Pointer to the concerned serial engine.771 * @iova: DMA address of the TX buffer.772 * @len: Length of the TX buffer.773 *774 * This function is used to unprepare the DMA buffers after DMA TX.775 */776void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)777{778 struct geni_wrapper *wrapper = se->wrapper;779 780 if (!dma_mapping_error(wrapper->dev, iova))781 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE);782}783EXPORT_SYMBOL_GPL(geni_se_tx_dma_unprep);784 785/**786 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer787 * @se: Pointer to the concerned serial engine.788 * @iova: DMA address of the RX buffer.789 * @len: Length of the RX buffer.790 *791 * This function is used to unprepare the DMA buffers after DMA RX.792 */793void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)794{795 struct geni_wrapper *wrapper = se->wrapper;796 797 if (!dma_mapping_error(wrapper->dev, iova))798 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE);799}800EXPORT_SYMBOL_GPL(geni_se_rx_dma_unprep);801 802int geni_icc_get(struct geni_se *se, const char *icc_ddr)803{804 int i, err;805 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr};806 807 if (has_acpi_companion(se->dev))808 return 0;809 810 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {811 if (!icc_names[i])812 continue;813 814 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]);815 if (IS_ERR(se->icc_paths[i].path))816 goto err;817 }818 819 return 0;820 821err:822 err = PTR_ERR(se->icc_paths[i].path);823 if (err != -EPROBE_DEFER)824 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n",825 icc_names[i], err);826 return err;827 828}829EXPORT_SYMBOL_GPL(geni_icc_get);830 831int geni_icc_set_bw(struct geni_se *se)832{833 int i, ret;834 835 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {836 ret = icc_set_bw(se->icc_paths[i].path,837 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw);838 if (ret) {839 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n",840 icc_path_names[i], ret);841 return ret;842 }843 }844 845 return 0;846}847EXPORT_SYMBOL_GPL(geni_icc_set_bw);848 849void geni_icc_set_tag(struct geni_se *se, u32 tag)850{851 int i;852 853 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++)854 icc_set_tag(se->icc_paths[i].path, tag);855}856EXPORT_SYMBOL_GPL(geni_icc_set_tag);857 858/* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */859int geni_icc_enable(struct geni_se *se)860{861 int i, ret;862 863 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {864 ret = icc_enable(se->icc_paths[i].path);865 if (ret) {866 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n",867 icc_path_names[i], ret);868 return ret;869 }870 }871 872 return 0;873}874EXPORT_SYMBOL_GPL(geni_icc_enable);875 876int geni_icc_disable(struct geni_se *se)877{878 int i, ret;879 880 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {881 ret = icc_disable(se->icc_paths[i].path);882 if (ret) {883 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n",884 icc_path_names[i], ret);885 return ret;886 }887 }888 889 return 0;890}891EXPORT_SYMBOL_GPL(geni_icc_disable);892 893static int geni_se_probe(struct platform_device *pdev)894{895 struct device *dev = &pdev->dev;896 struct geni_wrapper *wrapper;897 int ret;898 899 wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);900 if (!wrapper)901 return -ENOMEM;902 903 wrapper->dev = dev;904 wrapper->base = devm_platform_ioremap_resource(pdev, 0);905 if (IS_ERR(wrapper->base))906 return PTR_ERR(wrapper->base);907 908 if (!has_acpi_companion(&pdev->dev)) {909 const struct geni_se_desc *desc;910 int i;911 912 desc = device_get_match_data(&pdev->dev);913 if (!desc)914 return -EINVAL;915 916 wrapper->num_clks = min_t(unsigned int, desc->num_clks, MAX_CLKS);917 918 for (i = 0; i < wrapper->num_clks; ++i)919 wrapper->clks[i].id = desc->clks[i];920 921 ret = of_count_phandle_with_args(dev->of_node, "clocks", "#clock-cells");922 if (ret < 0) {923 dev_err(dev, "invalid clocks property at %pOF\n", dev->of_node);924 return ret;925 }926 927 if (ret < wrapper->num_clks) {928 dev_err(dev, "invalid clocks count at %pOF, expected %d entries\n",929 dev->of_node, wrapper->num_clks);930 return -EINVAL;931 }932 933 ret = devm_clk_bulk_get(dev, wrapper->num_clks, wrapper->clks);934 if (ret) {935 dev_err(dev, "Err getting clks %d\n", ret);936 return ret;937 }938 }939 940 dev_set_drvdata(dev, wrapper);941 dev_dbg(dev, "GENI SE Driver probed\n");942 return devm_of_platform_populate(dev);943}944 945static const char * const qup_clks[] = {946 "m-ahb",947 "s-ahb",948};949 950static const struct geni_se_desc qup_desc = {951 .clks = qup_clks,952 .num_clks = ARRAY_SIZE(qup_clks),953};954 955static const char * const i2c_master_hub_clks[] = {956 "s-ahb",957};958 959static const struct geni_se_desc i2c_master_hub_desc = {960 .clks = i2c_master_hub_clks,961 .num_clks = ARRAY_SIZE(i2c_master_hub_clks),962};963 964static const struct of_device_id geni_se_dt_match[] = {965 { .compatible = "qcom,geni-se-qup", .data = &qup_desc },966 { .compatible = "qcom,geni-se-i2c-master-hub", .data = &i2c_master_hub_desc },967 {}968};969MODULE_DEVICE_TABLE(of, geni_se_dt_match);970 971static struct platform_driver geni_se_driver = {972 .driver = {973 .name = "geni_se_qup",974 .of_match_table = geni_se_dt_match,975 },976 .probe = geni_se_probe,977};978module_platform_driver(geni_se_driver);979 980MODULE_DESCRIPTION("GENI Serial Engine Driver");981MODULE_LICENSE("GPL v2");982