178 lines · plain
1# SPDX-License-Identifier: GPL-2.0-only2if ARCH_TEGRA3 4# 32-bit ARM SoCs5if ARM6 7config ARCH_TEGRA_2x_SOC8 bool "Enable support for Tegra20 family"9 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP10 select ARM_ERRATA_72078911 select ARM_ERRATA_754327 if SMP12 select ARM_ERRATA_764369 if SMP13 select PINCTRL_TEGRA2014 select PL310_ERRATA_727915 if CACHE_L2X015 select PL310_ERRATA_769419 if CACHE_L2X016 select SOC_TEGRA_FLOWCTRL17 select SOC_TEGRA_PMC18 select SOC_TEGRA20_VOLTAGE_COUPLER if REGULATOR19 select TEGRA_TIMER20 help21 Support for NVIDIA Tegra AP20 and T20 processors, based on the22 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller23 24config ARCH_TEGRA_3x_SOC25 bool "Enable support for Tegra30 family"26 select ARM_ERRATA_75432227 select ARM_ERRATA_764369 if SMP28 select PINCTRL_TEGRA3029 select PL310_ERRATA_769419 if CACHE_L2X030 select SOC_TEGRA_FLOWCTRL31 select SOC_TEGRA_PMC32 select SOC_TEGRA30_VOLTAGE_COUPLER if REGULATOR33 select TEGRA_TIMER34 help35 Support for NVIDIA Tegra T30 processor family, based on the36 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller37 38config ARCH_TEGRA_114_SOC39 bool "Enable support for Tegra114 family"40 select ARM_ERRATA_798181 if SMP41 select HAVE_ARM_ARCH_TIMER42 select PINCTRL_TEGRA11443 select SOC_TEGRA_FLOWCTRL44 select SOC_TEGRA_PMC45 select TEGRA_TIMER46 help47 Support for NVIDIA Tegra T114 processor family, based on the48 ARM CortexA15MP CPU49 50config ARCH_TEGRA_124_SOC51 bool "Enable support for Tegra124 family"52 select HAVE_ARM_ARCH_TIMER53 select PINCTRL_TEGRA12454 select SOC_TEGRA_FLOWCTRL55 select SOC_TEGRA_PMC56 select TEGRA_TIMER57 help58 Support for NVIDIA Tegra T124 processor family, based on the59 ARM CortexA15MP CPU60 61endif62 63# 64-bit ARM SoCs64if ARM6465 66config ARCH_TEGRA_132_SOC67 bool "NVIDIA Tegra132 SoC"68 select PINCTRL_TEGRA12469 select SOC_TEGRA_FLOWCTRL70 select SOC_TEGRA_PMC71 help72 Enable support for NVIDIA Tegra132 SoC, based on the Denver73 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,74 but contains an NVIDIA Denver CPU complex in place of75 Tegra124's "4+1" Cortex-A15 CPU complex.76 77config ARCH_TEGRA_210_SOC78 bool "NVIDIA Tegra210 SoC"79 select PINCTRL_TEGRA21080 select SOC_TEGRA_FLOWCTRL81 select SOC_TEGRA_PMC82 select TEGRA_TIMER83 help84 Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A5386 cores in a switched configuration. It features a GPU of the Maxwell87 architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.188 and providing 256 CUDA cores. It supports hardware-accelerated en-89 and decoding of various video standards including H.265, H.264 and90 VP8 at 4K resolution and up to 60 fps.91 92 Besides the multimedia features it also comes with a variety of I/O93 controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to94 name only a few.95 96config ARCH_TEGRA_186_SOC97 bool "NVIDIA Tegra186 SoC"98 depends on !CPU_BIG_ENDIAN99 select MAILBOX100 select TEGRA_BPMP101 select TEGRA_HSP_MBOX102 select TEGRA_IVC103 select SOC_TEGRA_PMC104 help105 Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a106 combination of Denver and Cortex-A57 CPU cores and a GPU based on107 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU108 used for audio processing, hardware video encoders/decoders with109 multi-format support, ISP for image capture processing and BPMP for110 power management.111 112config ARCH_TEGRA_194_SOC113 bool "NVIDIA Tegra194 SoC"114 depends on !CPU_BIG_ENDIAN115 select MAILBOX116 select PINCTRL_TEGRA194117 select TEGRA_BPMP118 select TEGRA_HSP_MBOX119 select TEGRA_IVC120 select SOC_TEGRA_PMC121 help122 Enable support for the NVIDIA Tegra194 SoC.123 124config ARCH_TEGRA_234_SOC125 bool "NVIDIA Tegra234 SoC"126 depends on !CPU_BIG_ENDIAN127 select MAILBOX128 select PINCTRL_TEGRA234129 select TEGRA_BPMP130 select TEGRA_HSP_MBOX131 select TEGRA_IVC132 select SOC_TEGRA_PMC133 help134 Enable support for the NVIDIA Tegra234 SoC.135 136config ARCH_TEGRA_241_SOC137 bool "NVIDIA Tegra241 SoC"138 help139 Enable support for the NVIDIA Tegra241 SoC.140 141endif142endif143 144config SOC_TEGRA_FUSE145 def_bool y146 depends on ARCH_TEGRA147 select SOC_BUS148 149config SOC_TEGRA_FLOWCTRL150 bool151 152config SOC_TEGRA_PMC153 bool154 select GENERIC_PINCONF155 select IRQ_DOMAIN_HIERARCHY156 select PM_OPP157 select PM_GENERIC_DOMAINS158 select REGMAP159 160config SOC_TEGRA20_VOLTAGE_COUPLER161 bool "Voltage scaling support for Tegra20 SoCs"162 depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST163 depends on REGULATOR164 165config SOC_TEGRA30_VOLTAGE_COUPLER166 bool "Voltage scaling support for Tegra30 SoCs"167 depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST168 depends on REGULATOR169 170config SOC_TEGRA_CBB171 tristate "Tegra driver to handle error from CBB"172 depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC173 default y174 help175 Support for handling error from Tegra Control Backbone(CBB).176 This driver handles the errors from CBB and prints debug177 information about the failed transactions.178