602 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved.4 */5 6#include <linux/acpi.h>7#include <linux/clk.h>8#include <linux/device.h>9#include <linux/kobject.h>10#include <linux/init.h>11#include <linux/io.h>12#include <linux/mod_devicetable.h>13#include <linux/nvmem-consumer.h>14#include <linux/nvmem-provider.h>15#include <linux/of.h>16#include <linux/of_address.h>17#include <linux/platform_device.h>18#include <linux/pm_runtime.h>19#include <linux/reset.h>20#include <linux/slab.h>21#include <linux/sys_soc.h>22 23#include <soc/tegra/common.h>24#include <soc/tegra/fuse.h>25 26#include "fuse.h"27 28struct tegra_sku_info tegra_sku_info;29EXPORT_SYMBOL(tegra_sku_info);30 31static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {32 [TEGRA_REVISION_UNKNOWN] = "unknown",33 [TEGRA_REVISION_A01] = "A01",34 [TEGRA_REVISION_A02] = "A02",35 [TEGRA_REVISION_A03] = "A03",36 [TEGRA_REVISION_A03p] = "A03 prime",37 [TEGRA_REVISION_A04] = "A04",38};39 40static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {41 [TEGRA_PLATFORM_SILICON] = "Silicon",42 [TEGRA_PLATFORM_QT] = "QT",43 [TEGRA_PLATFORM_SYSTEM_FPGA] = "System FPGA",44 [TEGRA_PLATFORM_UNIT_FPGA] = "Unit FPGA",45 [TEGRA_PLATFORM_ASIM_QT] = "Asim QT",46 [TEGRA_PLATFORM_ASIM_LINSIM] = "Asim Linsim",47 [TEGRA_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim",48 [TEGRA_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation",49 [TEGRA_PLATFORM_VDK] = "VDK",50 [TEGRA_PLATFORM_VSP] = "VSP",51};52 53static const struct of_device_id car_match[] __initconst = {54 { .compatible = "nvidia,tegra20-car", },55 { .compatible = "nvidia,tegra30-car", },56 { .compatible = "nvidia,tegra114-car", },57 { .compatible = "nvidia,tegra124-car", },58 { .compatible = "nvidia,tegra132-car", },59 { .compatible = "nvidia,tegra210-car", },60 {},61};62 63static struct tegra_fuse *fuse = &(struct tegra_fuse) {64 .base = NULL,65 .soc = NULL,66};67 68static const struct of_device_id tegra_fuse_match[] = {69#ifdef CONFIG_ARCH_TEGRA_234_SOC70 { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },71#endif72#ifdef CONFIG_ARCH_TEGRA_194_SOC73 { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },74#endif75#ifdef CONFIG_ARCH_TEGRA_186_SOC76 { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },77#endif78#ifdef CONFIG_ARCH_TEGRA_210_SOC79 { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },80#endif81#ifdef CONFIG_ARCH_TEGRA_132_SOC82 { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },83#endif84#ifdef CONFIG_ARCH_TEGRA_124_SOC85 { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },86#endif87#ifdef CONFIG_ARCH_TEGRA_114_SOC88 { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },89#endif90#ifdef CONFIG_ARCH_TEGRA_3x_SOC91 { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },92#endif93#ifdef CONFIG_ARCH_TEGRA_2x_SOC94 { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },95#endif96 { /* sentinel */ }97};98 99static int tegra_fuse_read(void *priv, unsigned int offset, void *value,100 size_t bytes)101{102 unsigned int count = bytes / 4, i;103 struct tegra_fuse *fuse = priv;104 u32 *buffer = value;105 106 for (i = 0; i < count; i++)107 buffer[i] = fuse->read(fuse, offset + i * 4);108 109 return 0;110}111 112static void tegra_fuse_restore(void *base)113{114 fuse->base = (void __iomem *)base;115 fuse->clk = NULL;116}117 118static void tegra_fuse_print_sku_info(struct tegra_sku_info *tegra_sku_info)119{120 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",121 tegra_revision_name[tegra_sku_info->revision],122 tegra_sku_info->sku_id, tegra_sku_info->cpu_process_id,123 tegra_sku_info->soc_process_id);124 pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",125 tegra_sku_info->cpu_speedo_id, tegra_sku_info->soc_speedo_id);126}127 128static int tegra_fuse_add_lookups(struct tegra_fuse *fuse)129{130 fuse->lookups = kmemdup_array(fuse->soc->lookups, fuse->soc->num_lookups,131 sizeof(*fuse->lookups), GFP_KERNEL);132 if (!fuse->lookups)133 return -ENOMEM;134 135 nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups);136 137 return 0;138}139 140static int tegra_fuse_probe(struct platform_device *pdev)141{142 void __iomem *base = fuse->base;143 struct nvmem_config nvmem;144 struct resource *res;145 int err;146 147 err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base);148 if (err)149 return err;150 151 /* take over the memory region from the early initialization */152 fuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);153 if (IS_ERR(fuse->base))154 return PTR_ERR(fuse->base);155 fuse->phys = res->start;156 157 /* Initialize the soc data and lookups if using ACPI boot. */158 if (is_acpi_node(dev_fwnode(&pdev->dev)) && !fuse->soc) {159 u8 chip;160 161 tegra_acpi_init_apbmisc();162 163 chip = tegra_get_chip_id();164 switch (chip) {165#if defined(CONFIG_ARCH_TEGRA_194_SOC)166 case TEGRA194:167 fuse->soc = &tegra194_fuse_soc;168 break;169#endif170#if defined(CONFIG_ARCH_TEGRA_234_SOC)171 case TEGRA234:172 fuse->soc = &tegra234_fuse_soc;173 break;174#endif175#if defined(CONFIG_ARCH_TEGRA_241_SOC)176 case TEGRA241:177 fuse->soc = &tegra241_fuse_soc;178 break;179#endif180 default:181 return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported SoC: %02x\n", chip);182 }183 184 fuse->soc->init(fuse);185 tegra_fuse_print_sku_info(&tegra_sku_info);186 tegra_soc_device_register();187 188 err = tegra_fuse_add_lookups(fuse);189 if (err)190 return dev_err_probe(&pdev->dev, err, "failed to add FUSE lookups\n");191 }192 193 fuse->clk = devm_clk_get_optional(&pdev->dev, "fuse");194 if (IS_ERR(fuse->clk))195 return dev_err_probe(&pdev->dev, PTR_ERR(fuse->clk), "failed to get FUSE clock\n");196 197 platform_set_drvdata(pdev, fuse);198 fuse->dev = &pdev->dev;199 200 err = devm_pm_runtime_enable(&pdev->dev);201 if (err)202 return err;203 204 if (fuse->soc->probe) {205 err = fuse->soc->probe(fuse);206 if (err < 0)207 return err;208 }209 210 memset(&nvmem, 0, sizeof(nvmem));211 nvmem.dev = &pdev->dev;212 nvmem.name = "fuse";213 nvmem.id = -1;214 nvmem.owner = THIS_MODULE;215 nvmem.cells = fuse->soc->cells;216 nvmem.ncells = fuse->soc->num_cells;217 nvmem.keepout = fuse->soc->keepouts;218 nvmem.nkeepout = fuse->soc->num_keepouts;219 nvmem.type = NVMEM_TYPE_OTP;220 nvmem.read_only = true;221 nvmem.root_only = false;222 nvmem.reg_read = tegra_fuse_read;223 nvmem.size = fuse->soc->info->size;224 nvmem.word_size = 4;225 nvmem.stride = 4;226 nvmem.priv = fuse;227 228 fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);229 if (IS_ERR(fuse->nvmem)) {230 err = PTR_ERR(fuse->nvmem);231 dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",232 err);233 return err;234 }235 236 fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse");237 if (IS_ERR(fuse->rst))238 return dev_err_probe(&pdev->dev, PTR_ERR(fuse->rst), "failed to get FUSE reset\n");239 240 /*241 * FUSE clock is enabled at a boot time, hence this resume/suspend242 * disables the clock besides the h/w resetting.243 */244 err = pm_runtime_resume_and_get(&pdev->dev);245 if (err)246 return err;247 248 err = reset_control_reset(fuse->rst);249 pm_runtime_put(&pdev->dev);250 251 if (err < 0) {252 dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err);253 return err;254 }255 256 /* release the early I/O memory mapping */257 iounmap(base);258 259 return 0;260}261 262static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev)263{264 int err;265 266 err = clk_prepare_enable(fuse->clk);267 if (err < 0) {268 dev_err(dev, "failed to enable FUSE clock: %d\n", err);269 return err;270 }271 272 return 0;273}274 275static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev)276{277 clk_disable_unprepare(fuse->clk);278 279 return 0;280}281 282static int __maybe_unused tegra_fuse_suspend(struct device *dev)283{284 int ret;285 286 /*287 * Critical for RAM re-repair operation, which must occur on resume288 * from LP1 system suspend and as part of CCPLEX cluster switching.289 */290 if (fuse->soc->clk_suspend_on)291 ret = pm_runtime_resume_and_get(dev);292 else293 ret = pm_runtime_force_suspend(dev);294 295 return ret;296}297 298static int __maybe_unused tegra_fuse_resume(struct device *dev)299{300 int ret = 0;301 302 if (fuse->soc->clk_suspend_on)303 pm_runtime_put(dev);304 else305 ret = pm_runtime_force_resume(dev);306 307 return ret;308}309 310static const struct dev_pm_ops tegra_fuse_pm = {311 SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume,312 NULL)313 SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume)314};315 316static const struct acpi_device_id tegra_fuse_acpi_match[] = {317 { "NVDA200F" },318 { /* sentinel */ }319};320MODULE_DEVICE_TABLE(acpi, tegra_fuse_acpi_match);321 322static struct platform_driver tegra_fuse_driver = {323 .driver = {324 .name = "tegra-fuse",325 .of_match_table = tegra_fuse_match,326 .acpi_match_table = tegra_fuse_acpi_match,327 .pm = &tegra_fuse_pm,328 .suppress_bind_attrs = true,329 },330 .probe = tegra_fuse_probe,331};332builtin_platform_driver(tegra_fuse_driver);333 334u32 __init tegra_fuse_read_spare(unsigned int spare)335{336 unsigned int offset = fuse->soc->info->spare + spare * 4;337 338 return fuse->read_early(fuse, offset) & 1;339}340 341u32 __init tegra_fuse_read_early(unsigned int offset)342{343 return fuse->read_early(fuse, offset);344}345 346int tegra_fuse_readl(unsigned long offset, u32 *value)347{348 if (!fuse->dev)349 return -EPROBE_DEFER;350 351 /*352 * Wait for fuse->clk to be initialized if device-tree boot is used.353 */354 if (is_of_node(dev_fwnode(fuse->dev)) && !fuse->clk)355 return -EPROBE_DEFER;356 357 if (!fuse->read)358 return -EPROBE_DEFER;359 360 if (IS_ERR(fuse->clk))361 return PTR_ERR(fuse->clk);362 363 *value = fuse->read(fuse, offset);364 365 return 0;366}367EXPORT_SYMBOL(tegra_fuse_readl);368 369static void tegra_enable_fuse_clk(void __iomem *base)370{371 u32 reg;372 373 reg = readl_relaxed(base + 0x48);374 reg |= 1 << 28;375 writel(reg, base + 0x48);376 377 /*378 * Enable FUSE clock. This needs to be hardcoded because the clock379 * subsystem is not active during early boot.380 */381 reg = readl(base + 0x14);382 reg |= 1 << 7;383 writel(reg, base + 0x14);384}385 386static ssize_t major_show(struct device *dev, struct device_attribute *attr,387 char *buf)388{389 return sprintf(buf, "%d\n", tegra_get_major_rev());390}391 392static DEVICE_ATTR_RO(major);393 394static ssize_t minor_show(struct device *dev, struct device_attribute *attr,395 char *buf)396{397 return sprintf(buf, "%d\n", tegra_get_minor_rev());398}399 400static DEVICE_ATTR_RO(minor);401 402static struct attribute *tegra_soc_attr[] = {403 &dev_attr_major.attr,404 &dev_attr_minor.attr,405 NULL,406};407 408const struct attribute_group tegra_soc_attr_group = {409 .attrs = tegra_soc_attr,410};411 412#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \413 IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \414 IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC)415static ssize_t platform_show(struct device *dev, struct device_attribute *attr,416 char *buf)417{418 /*419 * Displays the value in the 'pre_si_platform' field of the HIDREV420 * register for Tegra194 devices. A value of 0 indicates that the421 * platform type is silicon and all other non-zero values indicate422 * the type of simulation platform is being used.423 */424 return sprintf(buf, "%d\n", tegra_get_platform());425}426 427static DEVICE_ATTR_RO(platform);428 429static struct attribute *tegra194_soc_attr[] = {430 &dev_attr_major.attr,431 &dev_attr_minor.attr,432 &dev_attr_platform.attr,433 NULL,434};435 436const struct attribute_group tegra194_soc_attr_group = {437 .attrs = tegra194_soc_attr,438};439#endif440 441struct device *tegra_soc_device_register(void)442{443 struct soc_device_attribute *attr;444 struct soc_device *dev;445 446 attr = kzalloc(sizeof(*attr), GFP_KERNEL);447 if (!attr)448 return NULL;449 450 attr->family = kasprintf(GFP_KERNEL, "Tegra");451 if (tegra_is_silicon())452 attr->revision = kasprintf(GFP_KERNEL, "%s %s",453 tegra_platform_name[tegra_sku_info.platform],454 tegra_revision_name[tegra_sku_info.revision]);455 else456 attr->revision = kasprintf(GFP_KERNEL, "%s",457 tegra_platform_name[tegra_sku_info.platform]);458 attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());459 attr->custom_attr_group = fuse->soc->soc_attr_group;460 461 dev = soc_device_register(attr);462 if (IS_ERR(dev)) {463 kfree(attr->soc_id);464 kfree(attr->revision);465 kfree(attr->family);466 kfree(attr);467 return ERR_CAST(dev);468 }469 470 return soc_device_to_device(dev);471}472 473static int __init tegra_init_fuse(void)474{475 const struct of_device_id *match;476 struct device_node *np;477 struct resource regs;478 int err;479 480 tegra_init_apbmisc();481 482 np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);483 if (!np) {484 /*485 * Fall back to legacy initialization for 32-bit ARM only. All486 * 64-bit ARM device tree files for Tegra are required to have487 * a FUSE node.488 *489 * This is for backwards-compatibility with old device trees490 * that didn't contain a FUSE node.491 */492 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {493 u8 chip = tegra_get_chip_id();494 495 regs.start = 0x7000f800;496 regs.end = 0x7000fbff;497 regs.flags = IORESOURCE_MEM;498 499 switch (chip) {500#ifdef CONFIG_ARCH_TEGRA_2x_SOC501 case TEGRA20:502 fuse->soc = &tegra20_fuse_soc;503 break;504#endif505 506#ifdef CONFIG_ARCH_TEGRA_3x_SOC507 case TEGRA30:508 fuse->soc = &tegra30_fuse_soc;509 break;510#endif511 512#ifdef CONFIG_ARCH_TEGRA_114_SOC513 case TEGRA114:514 fuse->soc = &tegra114_fuse_soc;515 break;516#endif517 518#ifdef CONFIG_ARCH_TEGRA_124_SOC519 case TEGRA124:520 fuse->soc = &tegra124_fuse_soc;521 break;522#endif523 524 default:525 pr_warn("Unsupported SoC: %02x\n", chip);526 break;527 }528 } else {529 /*530 * At this point we're not running on Tegra, so play531 * nice with multi-platform kernels.532 */533 return 0;534 }535 } else {536 /*537 * Extract information from the device tree if we've found a538 * matching node.539 */540 if (of_address_to_resource(np, 0, ®s) < 0) {541 pr_err("failed to get FUSE register\n");542 return -ENXIO;543 }544 545 fuse->soc = match->data;546 }547 548 np = of_find_matching_node(NULL, car_match);549 if (np) {550 void __iomem *base = of_iomap(np, 0);551 of_node_put(np);552 if (base) {553 tegra_enable_fuse_clk(base);554 iounmap(base);555 } else {556 pr_err("failed to map clock registers\n");557 return -ENXIO;558 }559 }560 561 fuse->base = ioremap(regs.start, resource_size(®s));562 if (!fuse->base) {563 pr_err("failed to map FUSE registers\n");564 return -ENXIO;565 }566 567 fuse->soc->init(fuse);568 569 tegra_fuse_print_sku_info(&tegra_sku_info);570 571 err = tegra_fuse_add_lookups(fuse);572 if (err)573 pr_err("failed to add FUSE lookups\n");574 575 return err;576}577early_initcall(tegra_init_fuse);578 579#ifdef CONFIG_ARM64580static int __init tegra_init_soc(void)581{582 struct device_node *np;583 struct device *soc;584 585 /* make sure we're running on Tegra */586 np = of_find_matching_node(NULL, tegra_fuse_match);587 if (!np)588 return 0;589 590 of_node_put(np);591 592 soc = tegra_soc_device_register();593 if (IS_ERR(soc)) {594 pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));595 return PTR_ERR(soc);596 }597 598 return 0;599}600device_initcall(tegra_init_soc);601#endif602