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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.4 */5 6#include <linux/acpi.h>7#include <linux/export.h>8#include <linux/io.h>9#include <linux/kernel.h>10#include <linux/mod_devicetable.h>11#include <linux/of.h>12#include <linux/of_address.h>13 14#include <soc/tegra/common.h>15#include <soc/tegra/fuse.h>16 17#include "fuse.h"18 19#define FUSE_SKU_INFO 0x1020 21#define ERD_ERR_CONFIG 0x120c22#define ERD_MASK_INBAND_ERR 0x123 24#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 425#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \26 (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)27#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \28 (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)29 30static void __iomem *apbmisc_base;31static bool long_ram_code;32static u32 strapping;33static u32 chipid;34 35u32 tegra_read_chipid(void)36{37 WARN(!chipid, "Tegra APB MISC not yet available\n");38 39 return chipid;40}41 42u8 tegra_get_chip_id(void)43{44 return (tegra_read_chipid() >> 8) & 0xff;45}46 47u8 tegra_get_major_rev(void)48{49 return (tegra_read_chipid() >> 4) & 0xf;50}51 52u8 tegra_get_minor_rev(void)53{54 return (tegra_read_chipid() >> 16) & 0xf;55}56 57u8 tegra_get_platform(void)58{59 return (tegra_read_chipid() >> 20) & 0xf;60}61 62bool tegra_is_silicon(void)63{64 switch (tegra_get_chip_id()) {65 case TEGRA194:66 case TEGRA234:67 case TEGRA241:68 case TEGRA264:69 if (tegra_get_platform() == 0)70 return true;71 72 return false;73 }74 75 /*76 * Chips prior to Tegra194 have a different way of determining whether77 * they are silicon or not. Since we never supported simulation on the78 * older Tegra chips, don't bother extracting the information and just79 * report that we're running on silicon.80 */81 return true;82}83 84u32 tegra_read_straps(void)85{86 WARN(!chipid, "Tegra ABP MISC not yet available\n");87 88 return strapping;89}90 91u32 tegra_read_ram_code(void)92{93 u32 straps = tegra_read_straps();94 95 if (long_ram_code)96 straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;97 else98 straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;99 100 return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;101}102EXPORT_SYMBOL_GPL(tegra_read_ram_code);103 104/*105 * The function sets ERD(Error Response Disable) bit.106 * This allows to mask inband errors and always send an107 * OKAY response from CBB to the master which caused error.108 */109int tegra194_miscreg_mask_serror(void)110{111 if (!apbmisc_base)112 return -EPROBE_DEFER;113 114 if (!of_machine_is_compatible("nvidia,tegra194")) {115 WARN(1, "Only supported for Tegra194 devices!\n");116 return -EOPNOTSUPP;117 }118 119 writel_relaxed(ERD_MASK_INBAND_ERR,120 apbmisc_base + ERD_ERR_CONFIG);121 122 return 0;123}124EXPORT_SYMBOL(tegra194_miscreg_mask_serror);125 126static const struct of_device_id apbmisc_match[] __initconst = {127 { .compatible = "nvidia,tegra20-apbmisc", },128 { .compatible = "nvidia,tegra186-misc", },129 { .compatible = "nvidia,tegra194-misc", },130 { .compatible = "nvidia,tegra234-misc", },131 {},132};133 134void __init tegra_init_revision(void)135{136 u8 chip_id, minor_rev;137 138 chip_id = tegra_get_chip_id();139 minor_rev = tegra_get_minor_rev();140 141 switch (minor_rev) {142 case 1:143 tegra_sku_info.revision = TEGRA_REVISION_A01;144 break;145 case 2:146 tegra_sku_info.revision = TEGRA_REVISION_A02;147 break;148 case 3:149 if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||150 tegra_fuse_read_spare(19)))151 tegra_sku_info.revision = TEGRA_REVISION_A03p;152 else153 tegra_sku_info.revision = TEGRA_REVISION_A03;154 break;155 case 4:156 tegra_sku_info.revision = TEGRA_REVISION_A04;157 break;158 default:159 tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN;160 }161 162 tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);163 tegra_sku_info.platform = tegra_get_platform();164}165 166static void tegra_init_apbmisc_resources(struct resource *apbmisc,167 struct resource *straps)168{169 void __iomem *strapping_base;170 171 apbmisc_base = ioremap(apbmisc->start, resource_size(apbmisc));172 if (apbmisc_base)173 chipid = readl_relaxed(apbmisc_base + 4);174 else175 pr_err("failed to map APBMISC registers\n");176 177 strapping_base = ioremap(straps->start, resource_size(straps));178 if (strapping_base) {179 strapping = readl_relaxed(strapping_base);180 iounmap(strapping_base);181 } else {182 pr_err("failed to map strapping options registers\n");183 }184}185 186/**187 * tegra_init_apbmisc - Initializes Tegra APBMISC and Strapping registers.188 *189 * This is called during early init as some of the old 32-bit ARM code needs190 * information from the APBMISC registers very early during boot.191 */192void __init tegra_init_apbmisc(void)193{194 struct resource apbmisc, straps;195 struct device_node *np;196 197 np = of_find_matching_node(NULL, apbmisc_match);198 if (!np) {199 /*200 * Fall back to legacy initialization for 32-bit ARM only. All201 * 64-bit ARM device tree files for Tegra are required to have202 * an APBMISC node.203 *204 * This is for backwards-compatibility with old device trees205 * that didn't contain an APBMISC node.206 */207 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {208 /* APBMISC registers (chip revision, ...) */209 apbmisc.start = 0x70000800;210 apbmisc.end = 0x70000863;211 apbmisc.flags = IORESOURCE_MEM;212 213 /* strapping options */214 if (of_machine_is_compatible("nvidia,tegra124")) {215 straps.start = 0x7000e864;216 straps.end = 0x7000e867;217 } else {218 straps.start = 0x70000008;219 straps.end = 0x7000000b;220 }221 222 straps.flags = IORESOURCE_MEM;223 224 pr_warn("Using APBMISC region %pR\n", &apbmisc);225 pr_warn("Using strapping options registers %pR\n",226 &straps);227 } else {228 /*229 * At this point we're not running on Tegra, so play230 * nice with multi-platform kernels.231 */232 return;233 }234 } else {235 /*236 * Extract information from the device tree if we've found a237 * matching node.238 */239 if (of_address_to_resource(np, 0, &apbmisc) < 0) {240 pr_err("failed to get APBMISC registers\n");241 goto put;242 }243 244 if (of_address_to_resource(np, 1, &straps) < 0) {245 pr_err("failed to get strapping options registers\n");246 goto put;247 }248 }249 250 tegra_init_apbmisc_resources(&apbmisc, &straps);251 long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");252 253put:254 of_node_put(np);255}256 257#ifdef CONFIG_ACPI258static const struct acpi_device_id apbmisc_acpi_match[] = {259 { "NVDA2010" },260 { /* sentinel */ }261};262 263void tegra_acpi_init_apbmisc(void)264{265 struct resource *resources[2] = { NULL };266 struct resource_entry *rentry;267 struct acpi_device *adev = NULL;268 struct list_head resource_list;269 int rcount = 0;270 int ret;271 272 adev = acpi_dev_get_first_match_dev(apbmisc_acpi_match[0].id, NULL, -1);273 if (!adev)274 return;275 276 INIT_LIST_HEAD(&resource_list);277 278 ret = acpi_dev_get_memory_resources(adev, &resource_list);279 if (ret < 0) {280 pr_err("failed to get APBMISC memory resources");281 goto out_put_acpi_dev;282 }283 284 /*285 * Get required memory resources.286 *287 * resources[0]: apbmisc.288 * resources[1]: straps.289 */290 resource_list_for_each_entry(rentry, &resource_list) {291 if (rcount >= ARRAY_SIZE(resources))292 break;293 294 resources[rcount++] = rentry->res;295 }296 297 if (!resources[0]) {298 pr_err("failed to get APBMISC registers\n");299 goto out_free_resource_list;300 }301 302 if (!resources[1]) {303 pr_err("failed to get strapping options registers\n");304 goto out_free_resource_list;305 }306 307 tegra_init_apbmisc_resources(resources[0], resources[1]);308 309out_free_resource_list:310 acpi_dev_free_resource_list(&resource_list);311 312out_put_acpi_dev:313 acpi_dev_put(adev);314}315#else316void tegra_acpi_init_apbmisc(void)317{318}319#endif320