brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.0-only2/*3 * drivers/soc/tegra/pmc.c4 *5 * Copyright (c) 2010 Google, Inc6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.7 *8 * Author:9 *	Colin Cross <ccross@google.com>10 */11 12#define pr_fmt(fmt) "tegra-pmc: " fmt13 14#include <linux/arm-smccc.h>15#include <linux/clk.h>16#include <linux/clk-provider.h>17#include <linux/clkdev.h>18#include <linux/clk/clk-conf.h>19#include <linux/clk/tegra.h>20#include <linux/debugfs.h>21#include <linux/delay.h>22#include <linux/device.h>23#include <linux/err.h>24#include <linux/export.h>25#include <linux/init.h>26#include <linux/interrupt.h>27#include <linux/io.h>28#include <linux/iopoll.h>29#include <linux/irqdomain.h>30#include <linux/irq.h>31#include <linux/kernel.h>32#include <linux/of_address.h>33#include <linux/of_clk.h>34#include <linux/of.h>35#include <linux/of_irq.h>36#include <linux/of_platform.h>37#include <linux/pinctrl/pinconf-generic.h>38#include <linux/pinctrl/pinconf.h>39#include <linux/pinctrl/pinctrl.h>40#include <linux/platform_device.h>41#include <linux/pm_domain.h>42#include <linux/pm_opp.h>43#include <linux/power_supply.h>44#include <linux/reboot.h>45#include <linux/regmap.h>46#include <linux/reset.h>47#include <linux/seq_file.h>48#include <linux/slab.h>49#include <linux/spinlock.h>50#include <linux/syscore_ops.h>51 52#include <soc/tegra/common.h>53#include <soc/tegra/fuse.h>54#include <soc/tegra/pmc.h>55 56#include <dt-bindings/interrupt-controller/arm-gic.h>57#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>58#include <dt-bindings/gpio/tegra186-gpio.h>59#include <dt-bindings/gpio/tegra194-gpio.h>60#include <dt-bindings/gpio/tegra234-gpio.h>61#include <dt-bindings/soc/tegra-pmc.h>62 63#define PMC_CNTRL			0x064#define  PMC_CNTRL_INTR_POLARITY	BIT(17) /* inverts INTR polarity */65#define  PMC_CNTRL_CPU_PWRREQ_OE	BIT(16) /* CPU pwr req enable */66#define  PMC_CNTRL_CPU_PWRREQ_POLARITY	BIT(15) /* CPU pwr req polarity */67#define  PMC_CNTRL_SIDE_EFFECT_LP0	BIT(14) /* LP0 when CPU pwr gated */68#define  PMC_CNTRL_SYSCLK_OE		BIT(11) /* system clock enable */69#define  PMC_CNTRL_SYSCLK_POLARITY	BIT(10) /* sys clk polarity */70#define  PMC_CNTRL_PWRREQ_POLARITY	BIT(8)71#define  PMC_CNTRL_BLINK_EN		772#define  PMC_CNTRL_MAIN_RST		BIT(4)73 74#define PMC_WAKE_MASK			0x0c75#define PMC_WAKE_LEVEL			0x1076#define PMC_WAKE_STATUS			0x1477#define PMC_SW_WAKE_STATUS		0x1878#define PMC_DPD_PADS_ORIDE		0x1c79#define  PMC_DPD_PADS_ORIDE_BLINK	2080 81#define DPD_SAMPLE			0x02082#define  DPD_SAMPLE_ENABLE		BIT(0)83#define  DPD_SAMPLE_DISABLE		(0 << 0)84 85#define PWRGATE_TOGGLE			0x3086#define  PWRGATE_TOGGLE_START		BIT(8)87 88#define REMOVE_CLAMPING			0x3489 90#define PWRGATE_STATUS			0x3891 92#define PMC_BLINK_TIMER			0x4093#define PMC_IMPL_E_33V_PWR		0x4094 95#define PMC_PWR_DET			0x4896 97#define PMC_SCRATCH0_MODE_RECOVERY	BIT(31)98#define PMC_SCRATCH0_MODE_BOOTLOADER	BIT(30)99#define PMC_SCRATCH0_MODE_RCM		BIT(1)100#define PMC_SCRATCH0_MODE_MASK		(PMC_SCRATCH0_MODE_RECOVERY | \101					 PMC_SCRATCH0_MODE_BOOTLOADER | \102					 PMC_SCRATCH0_MODE_RCM)103 104#define PMC_CPUPWRGOOD_TIMER		0xc8105#define PMC_CPUPWROFF_TIMER		0xcc106#define PMC_COREPWRGOOD_TIMER		0x3c107#define PMC_COREPWROFF_TIMER		0xe0108 109#define PMC_PWR_DET_VALUE		0xe4110 111#define PMC_USB_DEBOUNCE_DEL		0xec112#define PMC_USB_AO			0xf0113 114#define PMC_SCRATCH37			0x130115#define PMC_SCRATCH41			0x140116 117#define PMC_WAKE2_MASK			0x160118#define PMC_WAKE2_LEVEL			0x164119#define PMC_WAKE2_STATUS		0x168120#define PMC_SW_WAKE2_STATUS		0x16c121 122#define PMC_CLK_OUT_CNTRL		0x1a8123#define  PMC_CLK_OUT_MUX_MASK		GENMASK(1, 0)124#define PMC_SENSOR_CTRL			0x1b0125#define  PMC_SENSOR_CTRL_SCRATCH_WRITE	BIT(2)126#define  PMC_SENSOR_CTRL_ENABLE_RST	BIT(1)127 128#define  PMC_RST_STATUS_POR		0129#define  PMC_RST_STATUS_WATCHDOG	1130#define  PMC_RST_STATUS_SENSOR		2131#define  PMC_RST_STATUS_SW_MAIN		3132#define  PMC_RST_STATUS_LP0		4133#define  PMC_RST_STATUS_AOTAG		5134 135#define IO_DPD_REQ			0x1b8136#define  IO_DPD_REQ_CODE_IDLE		(0U << 30)137#define  IO_DPD_REQ_CODE_OFF		(1U << 30)138#define  IO_DPD_REQ_CODE_ON		(2U << 30)139#define  IO_DPD_REQ_CODE_MASK		(3U << 30)140 141#define IO_DPD_STATUS			0x1bc142#define IO_DPD2_REQ			0x1c0143#define IO_DPD2_STATUS			0x1c4144#define SEL_DPD_TIM			0x1c8145 146#define PMC_UTMIP_UHSIC_TRIGGERS	0x1ec147#define PMC_UTMIP_UHSIC_SAVED_STATE	0x1f0148 149#define PMC_UTMIP_TERM_PAD_CFG		0x1f8150#define PMC_UTMIP_UHSIC_SLEEP_CFG	0x1fc151#define PMC_UTMIP_UHSIC_FAKE		0x218152 153#define PMC_SCRATCH54			0x258154#define  PMC_SCRATCH54_DATA_SHIFT	8155#define  PMC_SCRATCH54_ADDR_SHIFT	0156 157#define PMC_SCRATCH55			0x25c158#define  PMC_SCRATCH55_RESET_TEGRA	BIT(31)159#define  PMC_SCRATCH55_CNTRL_ID_SHIFT	27160#define  PMC_SCRATCH55_PINMUX_SHIFT	24161#define  PMC_SCRATCH55_16BITOP		BIT(15)162#define  PMC_SCRATCH55_CHECKSUM_SHIFT	16163#define  PMC_SCRATCH55_I2CSLV1_SHIFT	0164 165#define  PMC_UTMIP_UHSIC_LINE_WAKEUP	0x26c166 167#define PMC_UTMIP_BIAS_MASTER_CNTRL	0x270168#define PMC_UTMIP_MASTER_CONFIG		0x274169#define PMC_UTMIP_UHSIC2_TRIGGERS	0x27c170#define PMC_UTMIP_MASTER2_CONFIG	0x29c171 172#define GPU_RG_CNTRL			0x2d4173 174#define PMC_UTMIP_PAD_CFG0		0x4c0175#define PMC_UTMIP_UHSIC_SLEEP_CFG1	0x4d0176#define PMC_UTMIP_SLEEPWALK_P3		0x4e0177/* Tegra186 and later */178#define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))179#define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)180#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1)181#define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))182#define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))183#define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))184#define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))185#define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))186#define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))187#define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))188#define WAKE_AOWAKE_SW_STATUS_W_0	0x49c189#define WAKE_AOWAKE_SW_STATUS(x)	(0x4a0 + ((x) << 2))190#define WAKE_LATCH_SW			0x498191 192#define WAKE_AOWAKE_CTRL 0x4f4193#define  WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)194 195#define SW_WAKE_ID		83 /* wake83 */196 197/* for secure PMC */198#define TEGRA_SMC_PMC		0xc2fffe00199#define  TEGRA_SMC_PMC_READ	0xaa200#define  TEGRA_SMC_PMC_WRITE	0xbb201 202struct pmc_clk {203	struct clk_hw	hw;204	unsigned long	offs;205	u32		mux_shift;206	u32		force_en_shift;207};208 209#define to_pmc_clk(_hw) container_of(_hw, struct pmc_clk, hw)210 211struct pmc_clk_gate {212	struct clk_hw	hw;213	unsigned long	offs;214	u32		shift;215};216 217#define to_pmc_clk_gate(_hw) container_of(_hw, struct pmc_clk_gate, hw)218 219struct pmc_clk_init_data {220	char *name;221	const char *const *parents;222	int num_parents;223	int clk_id;224	u8 mux_shift;225	u8 force_en_shift;226};227 228static const char * const clk_out1_parents[] = { "osc", "osc_div2",229	"osc_div4", "extern1",230};231 232static const char * const clk_out2_parents[] = { "osc", "osc_div2",233	"osc_div4", "extern2",234};235 236static const char * const clk_out3_parents[] = { "osc", "osc_div2",237	"osc_div4", "extern3",238};239 240static const struct pmc_clk_init_data tegra_pmc_clks_data[] = {241	{242		.name = "pmc_clk_out_1",243		.parents = clk_out1_parents,244		.num_parents = ARRAY_SIZE(clk_out1_parents),245		.clk_id = TEGRA_PMC_CLK_OUT_1,246		.mux_shift = 6,247		.force_en_shift = 2,248	},249	{250		.name = "pmc_clk_out_2",251		.parents = clk_out2_parents,252		.num_parents = ARRAY_SIZE(clk_out2_parents),253		.clk_id = TEGRA_PMC_CLK_OUT_2,254		.mux_shift = 14,255		.force_en_shift = 10,256	},257	{258		.name = "pmc_clk_out_3",259		.parents = clk_out3_parents,260		.num_parents = ARRAY_SIZE(clk_out3_parents),261		.clk_id = TEGRA_PMC_CLK_OUT_3,262		.mux_shift = 22,263		.force_en_shift = 18,264	},265};266 267struct tegra_powergate {268	struct generic_pm_domain genpd;269	struct tegra_pmc *pmc;270	unsigned int id;271	struct clk **clks;272	unsigned int num_clks;273	unsigned long *clk_rates;274	struct reset_control *reset;275};276 277struct tegra_io_pad_soc {278	enum tegra_io_pad id;279	unsigned int dpd;280	unsigned int request;281	unsigned int status;282	unsigned int voltage;283	const char *name;284};285 286struct tegra_pmc_regs {287	unsigned int scratch0;288	unsigned int rst_status;289	unsigned int rst_source_shift;290	unsigned int rst_source_mask;291	unsigned int rst_level_shift;292	unsigned int rst_level_mask;293};294 295struct tegra_wake_event {296	const char *name;297	unsigned int id;298	unsigned int irq;299	struct {300		unsigned int instance;301		unsigned int pin;302	} gpio;303};304 305#define TEGRA_WAKE_SIMPLE(_name, _id)			\306	{						\307		.name = _name,				\308		.id = _id,				\309		.irq = 0,				\310		.gpio = {				\311			.instance = UINT_MAX,		\312			.pin = UINT_MAX,		\313		},					\314	}315 316#define TEGRA_WAKE_IRQ(_name, _id, _irq)		\317	{						\318		.name = _name,				\319		.id = _id,				\320		.irq = _irq,				\321		.gpio = {				\322			.instance = UINT_MAX,		\323			.pin = UINT_MAX,		\324		},					\325	}326 327#define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin)	\328	{						\329		.name = _name,				\330		.id = _id,				\331		.irq = 0,				\332		.gpio = {				\333			.instance = _instance,		\334			.pin = _pin,			\335		},					\336	}337 338struct tegra_pmc_soc {339	unsigned int num_powergates;340	const char *const *powergates;341	unsigned int num_cpu_powergates;342	const u8 *cpu_powergates;343 344	bool has_tsense_reset;345	bool has_gpu_clamps;346	bool needs_mbist_war;347	bool has_impl_33v_pwr;348	bool maybe_tz_only;349 350	const struct tegra_io_pad_soc *io_pads;351	unsigned int num_io_pads;352 353	const struct pinctrl_pin_desc *pin_descs;354	unsigned int num_pin_descs;355 356	const struct tegra_pmc_regs *regs;357	void (*init)(struct tegra_pmc *pmc);358	void (*setup_irq_polarity)(struct tegra_pmc *pmc,359				   struct device_node *np,360				   bool invert);361	void (*set_wake_filters)(struct tegra_pmc *pmc);362	int (*irq_set_wake)(struct irq_data *data, unsigned int on);363	int (*irq_set_type)(struct irq_data *data, unsigned int type);364	int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,365			     bool new_state);366 367	const char * const *reset_sources;368	unsigned int num_reset_sources;369	const char * const *reset_levels;370	unsigned int num_reset_levels;371 372	/*373	 * These describe events that can wake the system from sleep (i.e.374	 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)375	 * are dealt with in the LIC.376	 */377	const struct tegra_wake_event *wake_events;378	unsigned int num_wake_events;379	unsigned int max_wake_events;380	unsigned int max_wake_vectors;381 382	const struct pmc_clk_init_data *pmc_clks_data;383	unsigned int num_pmc_clks;384	bool has_blink_output;385	bool has_usb_sleepwalk;386	bool supports_core_domain;387	bool has_single_mmio_aperture;388};389 390/**391 * struct tegra_pmc - NVIDIA Tegra PMC392 * @dev: pointer to PMC device structure393 * @base: pointer to I/O remapped register region394 * @wake: pointer to I/O remapped region for WAKE registers395 * @aotag: pointer to I/O remapped region for AOTAG registers396 * @scratch: pointer to I/O remapped region for scratch registers397 * @clk: pointer to pclk clock398 * @soc: pointer to SoC data structure399 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone400 * @rate: currently configured rate of pclk401 * @suspend_mode: lowest suspend mode available402 * @cpu_good_time: CPU power good time (in microseconds)403 * @cpu_off_time: CPU power off time (in microsecends)404 * @core_osc_time: core power good OSC time (in microseconds)405 * @core_pmu_time: core power good PMU time (in microseconds)406 * @core_off_time: core power off time (in microseconds)407 * @corereq_high: core power request is active-high408 * @sysclkreq_high: system clock request is active-high409 * @combined_req: combined power request for CPU & core410 * @cpu_pwr_good_en: CPU power good signal is enabled411 * @lp0_vec_phys: physical base address of the LP0 warm boot code412 * @lp0_vec_size: size of the LP0 warm boot code413 * @powergates_available: Bitmap of available power gates414 * @powergates_lock: mutex for power gate register access415 * @pctl_dev: pin controller exposed by the PMC416 * @domain: IRQ domain provided by the PMC417 * @irq: chip implementation for the IRQ domain418 * @clk_nb: pclk clock changes handler419 * @core_domain_state_synced: flag marking the core domain's state as synced420 * @core_domain_registered: flag marking the core domain as registered421 * @wake_type_level_map: Bitmap indicating level type for non-dual edge wakes422 * @wake_type_dual_edge_map: Bitmap indicating if a wake is dual-edge or not423 * @wake_sw_status_map: Bitmap to hold raw status of wakes without mask424 * @wake_cntrl_level_map: Bitmap to hold wake levels to be programmed in425 *     cntrl register associated with each wake during system suspend.426 */427struct tegra_pmc {428	struct device *dev;429	void __iomem *base;430	void __iomem *wake;431	void __iomem *aotag;432	void __iomem *scratch;433	struct clk *clk;434 435	const struct tegra_pmc_soc *soc;436	bool tz_only;437 438	unsigned long rate;439 440	enum tegra_suspend_mode suspend_mode;441	u32 cpu_good_time;442	u32 cpu_off_time;443	u32 core_osc_time;444	u32 core_pmu_time;445	u32 core_off_time;446	bool corereq_high;447	bool sysclkreq_high;448	bool combined_req;449	bool cpu_pwr_good_en;450	u32 lp0_vec_phys;451	u32 lp0_vec_size;452	DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);453 454	struct mutex powergates_lock;455 456	struct pinctrl_dev *pctl_dev;457 458	struct irq_domain *domain;459	struct irq_chip irq;460 461	struct notifier_block clk_nb;462 463	bool core_domain_state_synced;464	bool core_domain_registered;465 466	unsigned long *wake_type_level_map;467	unsigned long *wake_type_dual_edge_map;468	unsigned long *wake_sw_status_map;469	unsigned long *wake_cntrl_level_map;470	struct syscore_ops syscore;471};472 473static struct tegra_pmc *pmc = &(struct tegra_pmc) {474	.base = NULL,475	.suspend_mode = TEGRA_SUSPEND_NOT_READY,476};477 478static inline struct tegra_powergate *479to_powergate(struct generic_pm_domain *domain)480{481	return container_of(domain, struct tegra_powergate, genpd);482}483 484static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)485{486	struct arm_smccc_res res;487 488	if (pmc->tz_only) {489		arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,490			      0, 0, 0, &res);491		if (res.a0) {492			if (pmc->dev)493				dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",494					 __func__, res.a0);495			else496				pr_warn("%s(): SMC failed: %lu\n", __func__,497					res.a0);498		}499 500		return res.a1;501	}502 503	return readl(pmc->base + offset);504}505 506static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,507			     unsigned long offset)508{509	struct arm_smccc_res res;510 511	if (pmc->tz_only) {512		arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,513			      value, 0, 0, 0, 0, &res);514		if (res.a0) {515			if (pmc->dev)516				dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",517					 __func__, res.a0);518			else519				pr_warn("%s(): SMC failed: %lu\n", __func__,520					res.a0);521		}522	} else {523		writel(value, pmc->base + offset);524	}525}526 527static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)528{529	if (pmc->tz_only)530		return tegra_pmc_readl(pmc, offset);531 532	return readl(pmc->scratch + offset);533}534 535static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,536				     unsigned long offset)537{538	if (pmc->tz_only)539		tegra_pmc_writel(pmc, value, offset);540	else541		writel(value, pmc->scratch + offset);542}543 544/*545 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.546 * This currently doesn't work because readx_poll_timeout() can only operate547 * on functions that take a single argument.548 */549static inline bool tegra_powergate_state(int id)550{551	if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)552		return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;553	else554		return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;555}556 557static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)558{559	return (pmc->soc && pmc->soc->powergates[id]);560}561 562static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)563{564	return test_bit(id, pmc->powergates_available);565}566 567static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)568{569	unsigned int i;570 571	if (!pmc || !pmc->soc || !name)572		return -EINVAL;573 574	for (i = 0; i < pmc->soc->num_powergates; i++) {575		if (!tegra_powergate_is_valid(pmc, i))576			continue;577 578		if (!strcmp(name, pmc->soc->powergates[i]))579			return i;580	}581 582	return -ENODEV;583}584 585static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,586				 bool new_state)587{588	unsigned int retries = 100;589	bool status;590	int ret;591 592	/*593	 * As per TRM documentation, the toggle command will be dropped by PMC594	 * if there is contention with a HW-initiated toggling (i.e. CPU core595	 * power-gated), the command should be retried in that case.596	 */597	do {598		tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);599 600		/* wait for PMC to execute the command */601		ret = readx_poll_timeout(tegra_powergate_state, id, status,602					 status == new_state, 1, 10);603	} while (ret == -ETIMEDOUT && retries--);604 605	return ret;606}607 608static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)609{610	return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);611}612 613static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,614				  bool new_state)615{616	bool status;617	int err;618 619	/* wait while PMC power gating is contended */620	err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,621				 status == true, 1, 100);622	if (err)623		return err;624 625	tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);626 627	/* wait for PMC to accept the command */628	err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,629				 status == true, 1, 100);630	if (err)631		return err;632 633	/* wait for PMC to execute the command */634	err = readx_poll_timeout(tegra_powergate_state, id, status,635				 status == new_state, 10, 100000);636	if (err)637		return err;638 639	return 0;640}641 642/**643 * tegra_powergate_set() - set the state of a partition644 * @pmc: power management controller645 * @id: partition ID646 * @new_state: new state of the partition647 */648static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,649			       bool new_state)650{651	int err;652 653	if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)654		return -EINVAL;655 656	mutex_lock(&pmc->powergates_lock);657 658	if (tegra_powergate_state(id) == new_state) {659		mutex_unlock(&pmc->powergates_lock);660		return 0;661	}662 663	err = pmc->soc->powergate_set(pmc, id, new_state);664 665	mutex_unlock(&pmc->powergates_lock);666 667	return err;668}669 670static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,671					     unsigned int id)672{673	u32 mask;674 675	mutex_lock(&pmc->powergates_lock);676 677	/*678	 * On Tegra124 and later, the clamps for the GPU are controlled by a679	 * separate register (with different semantics).680	 */681	if (id == TEGRA_POWERGATE_3D) {682		if (pmc->soc->has_gpu_clamps) {683			tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);684			goto out;685		}686	}687 688	/*689	 * Tegra 2 has a bug where PCIE and VDE clamping masks are690	 * swapped relatively to the partition ids691	 */692	if (id == TEGRA_POWERGATE_VDEC)693		mask = (1 << TEGRA_POWERGATE_PCIE);694	else if (id == TEGRA_POWERGATE_PCIE)695		mask = (1 << TEGRA_POWERGATE_VDEC);696	else697		mask = (1 << id);698 699	tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);700 701out:702	mutex_unlock(&pmc->powergates_lock);703 704	return 0;705}706 707static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)708{709	unsigned long safe_rate = 100 * 1000 * 1000;710	unsigned int i;711	int err;712 713	for (i = 0; i < pg->num_clks; i++) {714		pg->clk_rates[i] = clk_get_rate(pg->clks[i]);715 716		if (!pg->clk_rates[i]) {717			err = -EINVAL;718			goto out;719		}720 721		if (pg->clk_rates[i] <= safe_rate)722			continue;723 724		/*725		 * We don't know whether voltage state is okay for the726		 * current clock rate, hence it's better to temporally727		 * switch clock to a safe rate which is suitable for728		 * all voltages, before enabling the clock.729		 */730		err = clk_set_rate(pg->clks[i], safe_rate);731		if (err)732			goto out;733	}734 735	return 0;736 737out:738	while (i--)739		clk_set_rate(pg->clks[i], pg->clk_rates[i]);740 741	return err;742}743 744static int tegra_powergate_unprepare_clocks(struct tegra_powergate *pg)745{746	unsigned int i;747	int err;748 749	for (i = 0; i < pg->num_clks; i++) {750		err = clk_set_rate(pg->clks[i], pg->clk_rates[i]);751		if (err)752			return err;753	}754 755	return 0;756}757 758static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)759{760	unsigned int i;761 762	for (i = 0; i < pg->num_clks; i++)763		clk_disable_unprepare(pg->clks[i]);764}765 766static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)767{768	unsigned int i;769	int err;770 771	for (i = 0; i < pg->num_clks; i++) {772		err = clk_prepare_enable(pg->clks[i]);773		if (err)774			goto out;775	}776 777	return 0;778 779out:780	while (i--)781		clk_disable_unprepare(pg->clks[i]);782 783	return err;784}785 786static int tegra_powergate_power_up(struct tegra_powergate *pg,787				    bool disable_clocks)788{789	int err;790 791	err = reset_control_assert(pg->reset);792	if (err)793		return err;794 795	usleep_range(10, 20);796 797	err = tegra_powergate_set(pg->pmc, pg->id, true);798	if (err < 0)799		return err;800 801	usleep_range(10, 20);802 803	err = tegra_powergate_prepare_clocks(pg);804	if (err)805		goto powergate_off;806 807	err = tegra_powergate_enable_clocks(pg);808	if (err)809		goto unprepare_clks;810 811	usleep_range(10, 20);812 813	err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);814	if (err)815		goto disable_clks;816 817	usleep_range(10, 20);818 819	err = reset_control_deassert(pg->reset);820	if (err)821		goto disable_clks;822 823	usleep_range(10, 20);824 825	if (pg->pmc->soc->needs_mbist_war)826		err = tegra210_clk_handle_mbist_war(pg->id);827	if (err)828		goto disable_clks;829 830	if (disable_clocks)831		tegra_powergate_disable_clocks(pg);832 833	err = tegra_powergate_unprepare_clocks(pg);834	if (err)835		return err;836 837	return 0;838 839disable_clks:840	tegra_powergate_disable_clocks(pg);841	usleep_range(10, 20);842 843unprepare_clks:844	tegra_powergate_unprepare_clocks(pg);845 846powergate_off:847	tegra_powergate_set(pg->pmc, pg->id, false);848 849	return err;850}851 852static int tegra_powergate_power_down(struct tegra_powergate *pg)853{854	int err;855 856	err = tegra_powergate_prepare_clocks(pg);857	if (err)858		return err;859 860	err = tegra_powergate_enable_clocks(pg);861	if (err)862		goto unprepare_clks;863 864	usleep_range(10, 20);865 866	err = reset_control_assert(pg->reset);867	if (err)868		goto disable_clks;869 870	usleep_range(10, 20);871 872	tegra_powergate_disable_clocks(pg);873 874	usleep_range(10, 20);875 876	err = tegra_powergate_set(pg->pmc, pg->id, false);877	if (err)878		goto assert_resets;879 880	err = tegra_powergate_unprepare_clocks(pg);881	if (err)882		return err;883 884	return 0;885 886assert_resets:887	tegra_powergate_enable_clocks(pg);888	usleep_range(10, 20);889	reset_control_deassert(pg->reset);890	usleep_range(10, 20);891 892disable_clks:893	tegra_powergate_disable_clocks(pg);894 895unprepare_clks:896	tegra_powergate_unprepare_clocks(pg);897 898	return err;899}900 901static int tegra_genpd_power_on(struct generic_pm_domain *domain)902{903	struct tegra_powergate *pg = to_powergate(domain);904	struct device *dev = pg->pmc->dev;905	int err;906 907	err = tegra_powergate_power_up(pg, true);908	if (err) {909		dev_err(dev, "failed to turn on PM domain %s: %d\n",910			pg->genpd.name, err);911		goto out;912	}913 914	reset_control_release(pg->reset);915 916out:917	return err;918}919 920static int tegra_genpd_power_off(struct generic_pm_domain *domain)921{922	struct tegra_powergate *pg = to_powergate(domain);923	struct device *dev = pg->pmc->dev;924	int err;925 926	err = reset_control_acquire(pg->reset);927	if (err < 0) {928		dev_err(dev, "failed to acquire resets for PM domain %s: %d\n",929			pg->genpd.name, err);930		return err;931	}932 933	err = tegra_powergate_power_down(pg);934	if (err) {935		dev_err(dev, "failed to turn off PM domain %s: %d\n",936			pg->genpd.name, err);937		reset_control_release(pg->reset);938	}939 940	return err;941}942 943/**944 * tegra_powergate_power_on() - power on partition945 * @id: partition ID946 */947int tegra_powergate_power_on(unsigned int id)948{949	if (!tegra_powergate_is_available(pmc, id))950		return -EINVAL;951 952	return tegra_powergate_set(pmc, id, true);953}954EXPORT_SYMBOL(tegra_powergate_power_on);955 956/**957 * tegra_powergate_power_off() - power off partition958 * @id: partition ID959 */960int tegra_powergate_power_off(unsigned int id)961{962	if (!tegra_powergate_is_available(pmc, id))963		return -EINVAL;964 965	return tegra_powergate_set(pmc, id, false);966}967EXPORT_SYMBOL(tegra_powergate_power_off);968 969/**970 * tegra_powergate_is_powered() - check if partition is powered971 * @pmc: power management controller972 * @id: partition ID973 */974static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)975{976	if (!tegra_powergate_is_valid(pmc, id))977		return -EINVAL;978 979	return tegra_powergate_state(id);980}981 982/**983 * tegra_powergate_remove_clamping() - remove power clamps for partition984 * @id: partition ID985 */986int tegra_powergate_remove_clamping(unsigned int id)987{988	if (!tegra_powergate_is_available(pmc, id))989		return -EINVAL;990 991	return __tegra_powergate_remove_clamping(pmc, id);992}993EXPORT_SYMBOL(tegra_powergate_remove_clamping);994 995/**996 * tegra_powergate_sequence_power_up() - power up partition997 * @id: partition ID998 * @clk: clock for partition999 * @rst: reset for partition1000 *1001 * Must be called with clk disabled, and returns with clk enabled.1002 */1003int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,1004				      struct reset_control *rst)1005{1006	struct tegra_powergate *pg;1007	int err;1008 1009	if (!tegra_powergate_is_available(pmc, id))1010		return -EINVAL;1011 1012	pg = kzalloc(sizeof(*pg), GFP_KERNEL);1013	if (!pg)1014		return -ENOMEM;1015 1016	pg->clk_rates = kzalloc(sizeof(*pg->clk_rates), GFP_KERNEL);1017	if (!pg->clk_rates) {1018		kfree(pg->clks);1019		return -ENOMEM;1020	}1021 1022	pg->id = id;1023	pg->clks = &clk;1024	pg->num_clks = 1;1025	pg->reset = rst;1026	pg->pmc = pmc;1027 1028	err = tegra_powergate_power_up(pg, false);1029	if (err)1030		dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,1031			err);1032 1033	kfree(pg->clk_rates);1034	kfree(pg);1035 1036	return err;1037}1038EXPORT_SYMBOL(tegra_powergate_sequence_power_up);1039 1040/**1041 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID1042 * @pmc: power management controller1043 * @cpuid: CPU partition ID1044 *1045 * Returns the partition ID corresponding to the CPU partition ID or a1046 * negative error code on failure.1047 */1048static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,1049				      unsigned int cpuid)1050{1051	if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)1052		return pmc->soc->cpu_powergates[cpuid];1053 1054	return -EINVAL;1055}1056 1057/**1058 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered1059 * @cpuid: CPU partition ID1060 */1061bool tegra_pmc_cpu_is_powered(unsigned int cpuid)1062{1063	int id;1064 1065	id = tegra_get_cpu_powergate_id(pmc, cpuid);1066	if (id < 0)1067		return false;1068 1069	return tegra_powergate_is_powered(pmc, id);1070}1071 1072/**1073 * tegra_pmc_cpu_power_on() - power on CPU partition1074 * @cpuid: CPU partition ID1075 */1076int tegra_pmc_cpu_power_on(unsigned int cpuid)1077{1078	int id;1079 1080	id = tegra_get_cpu_powergate_id(pmc, cpuid);1081	if (id < 0)1082		return id;1083 1084	return tegra_powergate_set(pmc, id, true);1085}1086 1087/**1088 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition1089 * @cpuid: CPU partition ID1090 */1091int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)1092{1093	int id;1094 1095	id = tegra_get_cpu_powergate_id(pmc, cpuid);1096	if (id < 0)1097		return id;1098 1099	return tegra_powergate_remove_clamping(id);1100}1101 1102static void tegra_pmc_program_reboot_reason(const char *cmd)1103{1104	u32 value;1105 1106	value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);1107	value &= ~PMC_SCRATCH0_MODE_MASK;1108 1109	if (cmd) {1110		if (strcmp(cmd, "recovery") == 0)1111			value |= PMC_SCRATCH0_MODE_RECOVERY;1112 1113		if (strcmp(cmd, "bootloader") == 0)1114			value |= PMC_SCRATCH0_MODE_BOOTLOADER;1115 1116		if (strcmp(cmd, "forced-recovery") == 0)1117			value |= PMC_SCRATCH0_MODE_RCM;1118	}1119 1120	tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);1121}1122 1123static int tegra_pmc_reboot_notify(struct notifier_block *this,1124				   unsigned long action, void *data)1125{1126	if (action == SYS_RESTART)1127		tegra_pmc_program_reboot_reason(data);1128 1129	return NOTIFY_DONE;1130}1131 1132static struct notifier_block tegra_pmc_reboot_notifier = {1133	.notifier_call = tegra_pmc_reboot_notify,1134};1135 1136static void tegra_pmc_restart(void)1137{1138	u32 value;1139 1140	/* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */1141	value = tegra_pmc_readl(pmc, PMC_CNTRL);1142	value |= PMC_CNTRL_MAIN_RST;1143	tegra_pmc_writel(pmc, value, PMC_CNTRL);1144}1145 1146static int tegra_pmc_restart_handler(struct sys_off_data *data)1147{1148	tegra_pmc_restart();1149 1150	return NOTIFY_DONE;1151}1152 1153static int tegra_pmc_power_off_handler(struct sys_off_data *data)1154{1155	/*1156	 * Reboot Nexus 7 into special bootloader mode if USB cable is1157	 * connected in order to display battery status and power off.1158	 */1159	if (of_machine_is_compatible("asus,grouper") &&1160	    power_supply_is_system_supplied()) {1161		const u32 go_to_charger_mode = 0xa5a55a5a;1162 1163		tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37);1164		tegra_pmc_restart();1165	}1166 1167	return NOTIFY_DONE;1168}1169 1170static int powergate_show(struct seq_file *s, void *data)1171{1172	unsigned int i;1173	int status;1174 1175	seq_printf(s, " powergate powered\n");1176	seq_printf(s, "------------------\n");1177 1178	for (i = 0; i < pmc->soc->num_powergates; i++) {1179		status = tegra_powergate_is_powered(pmc, i);1180		if (status < 0)1181			continue;1182 1183		seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],1184			   status ? "yes" : "no");1185	}1186 1187	return 0;1188}1189 1190DEFINE_SHOW_ATTRIBUTE(powergate);1191 1192static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,1193				       struct device_node *np)1194{1195	struct clk *clk;1196	unsigned int i, count;1197	int err;1198 1199	count = of_clk_get_parent_count(np);1200	if (count == 0)1201		return -ENODEV;1202 1203	pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);1204	if (!pg->clks)1205		return -ENOMEM;1206 1207	pg->clk_rates = kcalloc(count, sizeof(*pg->clk_rates), GFP_KERNEL);1208	if (!pg->clk_rates) {1209		kfree(pg->clks);1210		return -ENOMEM;1211	}1212 1213	for (i = 0; i < count; i++) {1214		pg->clks[i] = of_clk_get(np, i);1215		if (IS_ERR(pg->clks[i])) {1216			err = PTR_ERR(pg->clks[i]);1217			goto err;1218		}1219	}1220 1221	pg->num_clks = count;1222 1223	return 0;1224 1225err:1226	while (i--)1227		clk_put(pg->clks[i]);1228 1229	kfree(pg->clk_rates);1230	kfree(pg->clks);1231 1232	return err;1233}1234 1235static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,1236					 struct device_node *np, bool off)1237{1238	struct device *dev = pg->pmc->dev;1239	int err;1240 1241	pg->reset = of_reset_control_array_get_exclusive_released(np);1242	if (IS_ERR(pg->reset)) {1243		err = PTR_ERR(pg->reset);1244		dev_err(dev, "failed to get device resets: %d\n", err);1245		return err;1246	}1247 1248	err = reset_control_acquire(pg->reset);1249	if (err < 0) {1250		pr_err("failed to acquire resets: %d\n", err);1251		goto out;1252	}1253 1254	if (off) {1255		err = reset_control_assert(pg->reset);1256	} else {1257		err = reset_control_deassert(pg->reset);1258		if (err < 0)1259			goto out;1260 1261		reset_control_release(pg->reset);1262	}1263 1264out:1265	if (err) {1266		reset_control_release(pg->reset);1267		reset_control_put(pg->reset);1268	}1269 1270	return err;1271}1272 1273static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)1274{1275	struct device *dev = pmc->dev;1276	struct tegra_powergate *pg;1277	int id, err = 0;1278	bool off;1279 1280	pg = kzalloc(sizeof(*pg), GFP_KERNEL);1281	if (!pg)1282		return -ENOMEM;1283 1284	id = tegra_powergate_lookup(pmc, np->name);1285	if (id < 0) {1286		dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);1287		err = -ENODEV;1288		goto free_mem;1289	}1290 1291	/*1292	 * Clear the bit for this powergate so it cannot be managed1293	 * directly via the legacy APIs for controlling powergates.1294	 */1295	clear_bit(id, pmc->powergates_available);1296 1297	pg->id = id;1298	pg->genpd.name = np->name;1299	pg->genpd.power_off = tegra_genpd_power_off;1300	pg->genpd.power_on = tegra_genpd_power_on;1301	pg->pmc = pmc;1302 1303	off = !tegra_powergate_is_powered(pmc, pg->id);1304 1305	err = tegra_powergate_of_get_clks(pg, np);1306	if (err < 0) {1307		dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);1308		goto set_available;1309	}1310 1311	err = tegra_powergate_of_get_resets(pg, np, off);1312	if (err < 0) {1313		dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);1314		goto remove_clks;1315	}1316 1317	if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {1318		if (off)1319			WARN_ON(tegra_powergate_power_up(pg, true));1320 1321		goto remove_resets;1322	}1323 1324	err = pm_genpd_init(&pg->genpd, NULL, off);1325	if (err < 0) {1326		dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,1327		       err);1328		goto remove_resets;1329	}1330 1331	err = of_genpd_add_provider_simple(np, &pg->genpd);1332	if (err < 0) {1333		dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",1334			np, err);1335		goto remove_genpd;1336	}1337 1338	dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);1339 1340	return 0;1341 1342remove_genpd:1343	pm_genpd_remove(&pg->genpd);1344 1345remove_resets:1346	reset_control_put(pg->reset);1347 1348remove_clks:1349	while (pg->num_clks--)1350		clk_put(pg->clks[pg->num_clks]);1351 1352	kfree(pg->clks);1353 1354set_available:1355	set_bit(id, pmc->powergates_available);1356 1357free_mem:1358	kfree(pg);1359 1360	return err;1361}1362 1363bool tegra_pmc_core_domain_state_synced(void)1364{1365	return pmc->core_domain_state_synced;1366}1367 1368static int1369tegra_pmc_core_pd_set_performance_state(struct generic_pm_domain *genpd,1370					unsigned int level)1371{1372	struct dev_pm_opp *opp;1373	int err;1374 1375	opp = dev_pm_opp_find_level_ceil(&genpd->dev, &level);1376	if (IS_ERR(opp)) {1377		dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",1378			level, opp);1379		return PTR_ERR(opp);1380	}1381 1382	mutex_lock(&pmc->powergates_lock);1383	err = dev_pm_opp_set_opp(pmc->dev, opp);1384	mutex_unlock(&pmc->powergates_lock);1385 1386	dev_pm_opp_put(opp);1387 1388	if (err) {1389		dev_err(&genpd->dev, "failed to set voltage to %duV: %d\n",1390			level, err);1391		return err;1392	}1393 1394	return 0;1395}1396 1397static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)1398{1399	struct generic_pm_domain *genpd;1400	const char *rname[] = { "core", NULL};1401	int err;1402 1403	genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL);1404	if (!genpd)1405		return -ENOMEM;1406 1407	genpd->name = "core";1408	genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state;1409 1410	err = devm_pm_opp_set_regulators(pmc->dev, rname);1411	if (err)1412		return dev_err_probe(pmc->dev, err,1413				     "failed to set core OPP regulator\n");1414 1415	err = pm_genpd_init(genpd, NULL, false);1416	if (err) {1417		dev_err(pmc->dev, "failed to init core genpd: %d\n", err);1418		return err;1419	}1420 1421	err = of_genpd_add_provider_simple(np, genpd);1422	if (err) {1423		dev_err(pmc->dev, "failed to add core genpd: %d\n", err);1424		goto remove_genpd;1425	}1426 1427	pmc->core_domain_registered = true;1428 1429	return 0;1430 1431remove_genpd:1432	pm_genpd_remove(genpd);1433 1434	return err;1435}1436 1437static int tegra_powergate_init(struct tegra_pmc *pmc,1438				struct device_node *parent)1439{1440	struct of_phandle_args child_args, parent_args;1441	struct device_node *np;1442	int err = 0;1443 1444	/*1445	 * Core power domain is the parent of powergate domains, hence it1446	 * should be registered first.1447	 */1448	np = of_get_child_by_name(parent, "core-domain");1449	if (np) {1450		err = tegra_pmc_core_pd_add(pmc, np);1451		of_node_put(np);1452		if (err)1453			return err;1454	}1455 1456	np = of_get_child_by_name(parent, "powergates");1457	if (!np)1458		return 0;1459 1460	for_each_child_of_node_scoped(np, child) {1461		err = tegra_powergate_add(pmc, child);1462		if (err < 0)1463			break;1464 1465		if (of_parse_phandle_with_args(child, "power-domains",1466					       "#power-domain-cells",1467					       0, &parent_args))1468			continue;1469 1470		child_args.np = child;1471		child_args.args_count = 0;1472 1473		err = of_genpd_add_subdomain(&parent_args, &child_args);1474		of_node_put(parent_args.np);1475		if (err)1476			break;1477	}1478 1479	of_node_put(np);1480 1481	return err;1482}1483 1484static void tegra_powergate_remove(struct generic_pm_domain *genpd)1485{1486	struct tegra_powergate *pg = to_powergate(genpd);1487 1488	reset_control_put(pg->reset);1489 1490	while (pg->num_clks--)1491		clk_put(pg->clks[pg->num_clks]);1492 1493	kfree(pg->clks);1494 1495	set_bit(pg->id, pmc->powergates_available);1496 1497	kfree(pg);1498}1499 1500static void tegra_powergate_remove_all(struct device_node *parent)1501{1502	struct generic_pm_domain *genpd;1503	struct device_node *np, *child;1504 1505	np = of_get_child_by_name(parent, "powergates");1506	if (!np)1507		return;1508 1509	for_each_child_of_node(np, child) {1510		of_genpd_del_provider(child);1511 1512		genpd = of_genpd_remove_last(child);1513		if (IS_ERR(genpd))1514			continue;1515 1516		tegra_powergate_remove(genpd);1517	}1518 1519	of_node_put(np);1520 1521	np = of_get_child_by_name(parent, "core-domain");1522	if (np) {1523		of_genpd_del_provider(np);1524		of_genpd_remove_last(np);1525	}1526}1527 1528static const struct tegra_io_pad_soc *1529tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)1530{1531	unsigned int i;1532 1533	for (i = 0; i < pmc->soc->num_io_pads; i++)1534		if (pmc->soc->io_pads[i].id == id)1535			return &pmc->soc->io_pads[i];1536 1537	return NULL;1538}1539 1540static int tegra_io_pad_prepare(struct tegra_pmc *pmc,1541				const struct tegra_io_pad_soc *pad,1542				unsigned long *request,1543				unsigned long *status,1544				u32 *mask)1545{1546	unsigned long rate, value;1547 1548	if (pad->dpd == UINT_MAX)1549		return -EINVAL;1550 1551	*request = pad->request;1552	*status = pad->status;1553	*mask = BIT(pad->dpd);1554 1555	if (pmc->clk) {1556		rate = pmc->rate;1557		if (!rate) {1558			dev_err(pmc->dev, "failed to get clock rate\n");1559			return -ENODEV;1560		}1561 1562		tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);1563 1564		/* must be at least 200 ns, in APB (PCLK) clock cycles */1565		value = DIV_ROUND_UP(1000000000, rate);1566		value = DIV_ROUND_UP(200, value);1567		tegra_pmc_writel(pmc, value, SEL_DPD_TIM);1568	}1569 1570	return 0;1571}1572 1573static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,1574			     u32 mask, u32 val, unsigned long timeout)1575{1576	u32 value;1577 1578	timeout = jiffies + msecs_to_jiffies(timeout);1579 1580	while (time_after(timeout, jiffies)) {1581		value = tegra_pmc_readl(pmc, offset);1582		if ((value & mask) == val)1583			return 0;1584 1585		usleep_range(250, 1000);1586	}1587 1588	return -ETIMEDOUT;1589}1590 1591static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)1592{1593	if (pmc->clk)1594		tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);1595}1596 1597/**1598 * tegra_io_pad_power_enable() - enable power to I/O pad1599 * @id: Tegra I/O pad ID for which to enable power1600 *1601 * Returns: 0 on success or a negative error code on failure.1602 */1603int tegra_io_pad_power_enable(enum tegra_io_pad id)1604{1605	const struct tegra_io_pad_soc *pad;1606	unsigned long request, status;1607	u32 mask;1608	int err;1609 1610	pad = tegra_io_pad_find(pmc, id);1611	if (!pad) {1612		dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);1613		return -ENOENT;1614	}1615 1616	mutex_lock(&pmc->powergates_lock);1617 1618	err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);1619	if (err < 0) {1620		dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);1621		goto unlock;1622	}1623 1624	tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);1625 1626	err = tegra_io_pad_poll(pmc, status, mask, 0, 250);1627	if (err < 0) {1628		dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);1629		goto unlock;1630	}1631 1632	tegra_io_pad_unprepare(pmc);1633 1634unlock:1635	mutex_unlock(&pmc->powergates_lock);1636	return err;1637}1638EXPORT_SYMBOL(tegra_io_pad_power_enable);1639 1640/**1641 * tegra_io_pad_power_disable() - disable power to I/O pad1642 * @id: Tegra I/O pad ID for which to disable power1643 *1644 * Returns: 0 on success or a negative error code on failure.1645 */1646int tegra_io_pad_power_disable(enum tegra_io_pad id)1647{1648	const struct tegra_io_pad_soc *pad;1649	unsigned long request, status;1650	u32 mask;1651	int err;1652 1653	pad = tegra_io_pad_find(pmc, id);1654	if (!pad) {1655		dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);1656		return -ENOENT;1657	}1658 1659	mutex_lock(&pmc->powergates_lock);1660 1661	err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);1662	if (err < 0) {1663		dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);1664		goto unlock;1665	}1666 1667	tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);1668 1669	err = tegra_io_pad_poll(pmc, status, mask, mask, 250);1670	if (err < 0) {1671		dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);1672		goto unlock;1673	}1674 1675	tegra_io_pad_unprepare(pmc);1676 1677unlock:1678	mutex_unlock(&pmc->powergates_lock);1679	return err;1680}1681EXPORT_SYMBOL(tegra_io_pad_power_disable);1682 1683static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)1684{1685	const struct tegra_io_pad_soc *pad;1686	unsigned long status;1687	u32 mask, value;1688 1689	pad = tegra_io_pad_find(pmc, id);1690	if (!pad) {1691		dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);1692		return -ENOENT;1693	}1694 1695	if (pad->dpd == UINT_MAX)1696		return -EINVAL;1697 1698	status = pad->status;1699	mask = BIT(pad->dpd);1700 1701	value = tegra_pmc_readl(pmc, status);1702 1703	return !(value & mask);1704}1705 1706static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,1707				    int voltage)1708{1709	const struct tegra_io_pad_soc *pad;1710	u32 value;1711 1712	pad = tegra_io_pad_find(pmc, id);1713	if (!pad)1714		return -ENOENT;1715 1716	if (pad->voltage == UINT_MAX)1717		return -ENOTSUPP;1718 1719	mutex_lock(&pmc->powergates_lock);1720 1721	if (pmc->soc->has_impl_33v_pwr) {1722		value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);1723 1724		if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)1725			value &= ~BIT(pad->voltage);1726		else1727			value |= BIT(pad->voltage);1728 1729		tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);1730	} else {1731		/* write-enable PMC_PWR_DET_VALUE[pad->voltage] */1732		value = tegra_pmc_readl(pmc, PMC_PWR_DET);1733		value |= BIT(pad->voltage);1734		tegra_pmc_writel(pmc, value, PMC_PWR_DET);1735 1736		/* update I/O voltage */1737		value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);1738 1739		if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)1740			value &= ~BIT(pad->voltage);1741		else1742			value |= BIT(pad->voltage);1743 1744		tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);1745	}1746 1747	mutex_unlock(&pmc->powergates_lock);1748 1749	usleep_range(100, 250);1750 1751	return 0;1752}1753 1754static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)1755{1756	const struct tegra_io_pad_soc *pad;1757	u32 value;1758 1759	pad = tegra_io_pad_find(pmc, id);1760	if (!pad)1761		return -ENOENT;1762 1763	if (pad->voltage == UINT_MAX)1764		return -ENOTSUPP;1765 1766	if (pmc->soc->has_impl_33v_pwr)1767		value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);1768	else1769		value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);1770 1771	if ((value & BIT(pad->voltage)) == 0)1772		return TEGRA_IO_PAD_VOLTAGE_1V8;1773 1774	return TEGRA_IO_PAD_VOLTAGE_3V3;1775}1776 1777#ifdef CONFIG_PM_SLEEP1778enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)1779{1780	return pmc->suspend_mode;1781}1782 1783void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)1784{1785	if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)1786		return;1787 1788	pmc->suspend_mode = mode;1789}1790 1791void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)1792{1793	unsigned long long rate = 0;1794	u64 ticks;1795	u32 value;1796 1797	switch (mode) {1798	case TEGRA_SUSPEND_LP1:1799		rate = 32768;1800		break;1801 1802	case TEGRA_SUSPEND_LP2:1803		rate = pmc->rate;1804		break;1805 1806	default:1807		break;1808	}1809 1810	if (WARN_ON_ONCE(rate == 0))1811		rate = 100000000;1812 1813	ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;1814	do_div(ticks, USEC_PER_SEC);1815	tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);1816 1817	ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;1818	do_div(ticks, USEC_PER_SEC);1819	tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);1820 1821	value = tegra_pmc_readl(pmc, PMC_CNTRL);1822	value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;1823	value |= PMC_CNTRL_CPU_PWRREQ_OE;1824	tegra_pmc_writel(pmc, value, PMC_CNTRL);1825}1826#endif1827 1828static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)1829{1830	u32 value, values[2];1831 1832	if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {1833		pmc->suspend_mode = TEGRA_SUSPEND_NONE;1834	} else {1835		switch (value) {1836		case 0:1837			pmc->suspend_mode = TEGRA_SUSPEND_LP0;1838			break;1839 1840		case 1:1841			pmc->suspend_mode = TEGRA_SUSPEND_LP1;1842			break;1843 1844		case 2:1845			pmc->suspend_mode = TEGRA_SUSPEND_LP2;1846			break;1847 1848		default:1849			pmc->suspend_mode = TEGRA_SUSPEND_NONE;1850			break;1851		}1852	}1853 1854	pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);1855 1856	if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))1857		pmc->suspend_mode = TEGRA_SUSPEND_NONE;1858 1859	pmc->cpu_good_time = value;1860 1861	if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))1862		pmc->suspend_mode = TEGRA_SUSPEND_NONE;1863 1864	pmc->cpu_off_time = value;1865 1866	if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",1867				       values, ARRAY_SIZE(values)))1868		pmc->suspend_mode = TEGRA_SUSPEND_NONE;1869 1870	pmc->core_osc_time = values[0];1871	pmc->core_pmu_time = values[1];1872 1873	if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))1874		pmc->suspend_mode = TEGRA_SUSPEND_NONE;1875 1876	pmc->core_off_time = value;1877 1878	pmc->corereq_high = of_property_read_bool(np,1879				"nvidia,core-power-req-active-high");1880 1881	pmc->sysclkreq_high = of_property_read_bool(np,1882				"nvidia,sys-clock-req-active-high");1883 1884	pmc->combined_req = of_property_read_bool(np,1885				"nvidia,combined-power-req");1886 1887	pmc->cpu_pwr_good_en = of_property_read_bool(np,1888				"nvidia,cpu-pwr-good-en");1889 1890	if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,1891				       ARRAY_SIZE(values)))1892		if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)1893			pmc->suspend_mode = TEGRA_SUSPEND_LP1;1894 1895	pmc->lp0_vec_phys = values[0];1896	pmc->lp0_vec_size = values[1];1897 1898	return 0;1899}1900 1901static int tegra_pmc_init(struct tegra_pmc *pmc)1902{1903	if (pmc->soc->max_wake_events > 0) {1904		pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);1905		if (!pmc->wake_type_level_map)1906			return -ENOMEM;1907 1908		pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);1909		if (!pmc->wake_type_dual_edge_map)1910			return -ENOMEM;1911 1912		pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);1913		if (!pmc->wake_sw_status_map)1914			return -ENOMEM;1915 1916		pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);1917		if (!pmc->wake_cntrl_level_map)1918			return -ENOMEM;1919	}1920 1921	if (pmc->soc->init)1922		pmc->soc->init(pmc);1923 1924	return 0;1925}1926 1927static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)1928{1929	static const char disabled[] = "emergency thermal reset disabled";1930	u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;1931	struct device *dev = pmc->dev;1932	struct device_node *np;1933	u32 value, checksum;1934 1935	if (!pmc->soc->has_tsense_reset)1936		return;1937 1938	np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");1939	if (!np) {1940		dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);1941		return;1942	}1943 1944	if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {1945		dev_err(dev, "I2C controller ID missing, %s.\n", disabled);1946		goto out;1947	}1948 1949	if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {1950		dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);1951		goto out;1952	}1953 1954	if (of_property_read_u32(np, "nvidia,reg-addr", &reg_addr)) {1955		dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);1956		goto out;1957	}1958 1959	if (of_property_read_u32(np, "nvidia,reg-data", &reg_data)) {1960		dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);1961		goto out;1962	}1963 1964	if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))1965		pinmux = 0;1966 1967	value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);1968	value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;1969	tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);1970 1971	value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |1972		(reg_addr << PMC_SCRATCH54_ADDR_SHIFT);1973	tegra_pmc_writel(pmc, value, PMC_SCRATCH54);1974 1975	value = PMC_SCRATCH55_RESET_TEGRA;1976	value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;1977	value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;1978	value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;1979 1980	/*1981	 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will1982	 * contain the checksum and are currently zero, so they are not added.1983	 */1984	checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)1985		+ ((value >> 24) & 0xff);1986	checksum &= 0xff;1987	checksum = 0x100 - checksum;1988 1989	value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;1990 1991	tegra_pmc_writel(pmc, value, PMC_SCRATCH55);1992 1993	value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);1994	value |= PMC_SENSOR_CTRL_ENABLE_RST;1995	tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);1996 1997	dev_info(pmc->dev, "emergency thermal reset enabled\n");1998 1999out:2000	of_node_put(np);2001}2002 2003static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)2004{2005	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);2006 2007	return pmc->soc->num_io_pads;2008}2009 2010static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,2011						       unsigned int group)2012{2013	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);2014 2015	return pmc->soc->io_pads[group].name;2016}2017 2018static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,2019					       unsigned int group,2020					       const unsigned int **pins,2021					       unsigned int *num_pins)2022{2023	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);2024 2025	*pins = &pmc->soc->io_pads[group].id;2026	*num_pins = 1;2027 2028	return 0;2029}2030 2031static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {2032	.get_groups_count = tegra_io_pad_pinctrl_get_groups_count,2033	.get_group_name = tegra_io_pad_pinctrl_get_group_name,2034	.get_group_pins = tegra_io_pad_pinctrl_get_group_pins,2035	.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,2036	.dt_free_map = pinconf_generic_dt_free_map,2037};2038 2039static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,2040				    unsigned int pin, unsigned long *config)2041{2042	enum pin_config_param param = pinconf_to_config_param(*config);2043	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);2044	const struct tegra_io_pad_soc *pad;2045	int ret;2046	u32 arg;2047 2048	pad = tegra_io_pad_find(pmc, pin);2049	if (!pad)2050		return -EINVAL;2051 2052	switch (param) {2053	case PIN_CONFIG_POWER_SOURCE:2054		ret = tegra_io_pad_get_voltage(pmc, pad->id);2055		if (ret < 0)2056			return ret;2057 2058		arg = ret;2059		break;2060 2061	case PIN_CONFIG_MODE_LOW_POWER:2062		ret = tegra_io_pad_is_powered(pmc, pad->id);2063		if (ret < 0)2064			return ret;2065 2066		arg = !ret;2067		break;2068 2069	default:2070		return -EINVAL;2071	}2072 2073	*config = pinconf_to_config_packed(param, arg);2074 2075	return 0;2076}2077 2078static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,2079				    unsigned int pin, unsigned long *configs,2080				    unsigned int num_configs)2081{2082	struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);2083	const struct tegra_io_pad_soc *pad;2084	enum pin_config_param param;2085	unsigned int i;2086	int err;2087	u32 arg;2088 2089	pad = tegra_io_pad_find(pmc, pin);2090	if (!pad)2091		return -EINVAL;2092 2093	for (i = 0; i < num_configs; ++i) {2094		param = pinconf_to_config_param(configs[i]);2095		arg = pinconf_to_config_argument(configs[i]);2096 2097		switch (param) {2098		case PIN_CONFIG_MODE_LOW_POWER:2099			if (arg)2100				err = tegra_io_pad_power_disable(pad->id);2101			else2102				err = tegra_io_pad_power_enable(pad->id);2103			if (err)2104				return err;2105			break;2106		case PIN_CONFIG_POWER_SOURCE:2107			if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&2108			    arg != TEGRA_IO_PAD_VOLTAGE_3V3)2109				return -EINVAL;2110			err = tegra_io_pad_set_voltage(pmc, pad->id, arg);2111			if (err)2112				return err;2113			break;2114		default:2115			return -EINVAL;2116		}2117	}2118 2119	return 0;2120}2121 2122static const struct pinconf_ops tegra_io_pad_pinconf_ops = {2123	.pin_config_get = tegra_io_pad_pinconf_get,2124	.pin_config_set = tegra_io_pad_pinconf_set,2125	.is_generic = true,2126};2127 2128static struct pinctrl_desc tegra_pmc_pctl_desc = {2129	.pctlops = &tegra_io_pad_pinctrl_ops,2130	.confops = &tegra_io_pad_pinconf_ops,2131};2132 2133static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)2134{2135	int err;2136 2137	if (!pmc->soc->num_pin_descs)2138		return 0;2139 2140	tegra_pmc_pctl_desc.name = dev_name(pmc->dev);2141	tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;2142	tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;2143 2144	pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,2145					      pmc);2146	if (IS_ERR(pmc->pctl_dev)) {2147		err = PTR_ERR(pmc->pctl_dev);2148		dev_err(pmc->dev, "failed to register pin controller: %d\n",2149			err);2150		return err;2151	}2152 2153	return 0;2154}2155 2156static ssize_t reset_reason_show(struct device *dev,2157				 struct device_attribute *attr, char *buf)2158{2159	u32 value;2160 2161	value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);2162	value &= pmc->soc->regs->rst_source_mask;2163	value >>= pmc->soc->regs->rst_source_shift;2164 2165	if (WARN_ON(value >= pmc->soc->num_reset_sources))2166		return sprintf(buf, "%s\n", "UNKNOWN");2167 2168	return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);2169}2170 2171static DEVICE_ATTR_RO(reset_reason);2172 2173static ssize_t reset_level_show(struct device *dev,2174				struct device_attribute *attr, char *buf)2175{2176	u32 value;2177 2178	value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);2179	value &= pmc->soc->regs->rst_level_mask;2180	value >>= pmc->soc->regs->rst_level_shift;2181 2182	if (WARN_ON(value >= pmc->soc->num_reset_levels))2183		return sprintf(buf, "%s\n", "UNKNOWN");2184 2185	return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);2186}2187 2188static DEVICE_ATTR_RO(reset_level);2189 2190static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)2191{2192	struct device *dev = pmc->dev;2193	int err = 0;2194 2195	if (pmc->soc->reset_sources) {2196		err = device_create_file(dev, &dev_attr_reset_reason);2197		if (err < 0)2198			dev_warn(dev,2199				 "failed to create attr \"reset_reason\": %d\n",2200				 err);2201	}2202 2203	if (pmc->soc->reset_levels) {2204		err = device_create_file(dev, &dev_attr_reset_level);2205		if (err < 0)2206			dev_warn(dev,2207				 "failed to create attr \"reset_level\": %d\n",2208				 err);2209	}2210}2211 2212static int tegra_pmc_irq_translate(struct irq_domain *domain,2213				   struct irq_fwspec *fwspec,2214				   unsigned long *hwirq,2215				   unsigned int *type)2216{2217	if (WARN_ON(fwspec->param_count < 2))2218		return -EINVAL;2219 2220	*hwirq = fwspec->param[0];2221	*type = fwspec->param[1];2222 2223	return 0;2224}2225 2226static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,2227			       unsigned int num_irqs, void *data)2228{2229	struct tegra_pmc *pmc = domain->host_data;2230	const struct tegra_pmc_soc *soc = pmc->soc;2231	struct irq_fwspec *fwspec = data;2232	unsigned int i;2233	int err = 0;2234 2235	if (WARN_ON(num_irqs > 1))2236		return -EINVAL;2237 2238	for (i = 0; i < soc->num_wake_events; i++) {2239		const struct tegra_wake_event *event = &soc->wake_events[i];2240 2241		/* IRQ and simple wake events */2242		if (fwspec->param_count == 2) {2243			struct irq_fwspec spec;2244 2245			if (event->id != fwspec->param[0])2246				continue;2247 2248			err = irq_domain_set_hwirq_and_chip(domain, virq,2249							    event->id,2250							    &pmc->irq, pmc);2251			if (err < 0)2252				break;2253 2254			/* simple hierarchies stop at the PMC level */2255			if (event->irq == 0) {2256				err = irq_domain_disconnect_hierarchy(domain->parent, virq);2257				break;2258			}2259 2260			spec.fwnode = &pmc->dev->of_node->fwnode;2261			spec.param_count = 3;2262			spec.param[0] = GIC_SPI;2263			spec.param[1] = event->irq;2264			spec.param[2] = fwspec->param[1];2265 2266			err = irq_domain_alloc_irqs_parent(domain, virq,2267							   num_irqs, &spec);2268 2269			break;2270		}2271 2272		/* GPIO wake events */2273		if (fwspec->param_count == 3) {2274			if (event->gpio.instance != fwspec->param[0] ||2275			    event->gpio.pin != fwspec->param[1])2276				continue;2277 2278			err = irq_domain_set_hwirq_and_chip(domain, virq,2279							    event->id,2280							    &pmc->irq, pmc);2281 2282			/* GPIO hierarchies stop at the PMC level */2283			if (!err && domain->parent)2284				err = irq_domain_disconnect_hierarchy(domain->parent,2285								      virq);2286			break;2287		}2288	}2289 2290	/* If there is no wake-up event, there is no PMC mapping */2291	if (i == soc->num_wake_events)2292		err = irq_domain_disconnect_hierarchy(domain, virq);2293 2294	return err;2295}2296 2297static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {2298	.translate = tegra_pmc_irq_translate,2299	.alloc = tegra_pmc_irq_alloc,2300};2301 2302static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)2303{2304	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);2305	unsigned int offset, bit;2306	u32 value;2307 2308	offset = data->hwirq / 32;2309	bit = data->hwirq % 32;2310 2311	/* clear wake status */2312	tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);2313	tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);2314 2315	tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);2316	tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);2317 2318	/* enable PMC wake */2319	if (data->hwirq >= 32)2320		offset = PMC_WAKE2_MASK;2321	else2322		offset = PMC_WAKE_MASK;2323 2324	value = tegra_pmc_readl(pmc, offset);2325 2326	if (on)2327		value |= BIT(bit);2328	else2329		value &= ~BIT(bit);2330 2331	tegra_pmc_writel(pmc, value, offset);2332 2333	return 0;2334}2335 2336static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)2337{2338	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);2339	unsigned int offset, bit;2340	u32 value;2341 2342	offset = data->hwirq / 32;2343	bit = data->hwirq % 32;2344 2345	if (data->hwirq >= 32)2346		offset = PMC_WAKE2_LEVEL;2347	else2348		offset = PMC_WAKE_LEVEL;2349 2350	value = tegra_pmc_readl(pmc, offset);2351 2352	switch (type) {2353	case IRQ_TYPE_EDGE_RISING:2354	case IRQ_TYPE_LEVEL_HIGH:2355		value |= BIT(bit);2356		break;2357 2358	case IRQ_TYPE_EDGE_FALLING:2359	case IRQ_TYPE_LEVEL_LOW:2360		value &= ~BIT(bit);2361		break;2362 2363	case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:2364		value ^= BIT(bit);2365		break;2366 2367	default:2368		return -EINVAL;2369	}2370 2371	tegra_pmc_writel(pmc, value, offset);2372 2373	return 0;2374}2375 2376static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc)2377{2378	u32 value;2379 2380	/* SW Wake (wake83) needs SR_CAPTURE filter to be enabled */2381	value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID));2382	value |= WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN;2383	writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID));2384	dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value);2385}2386 2387static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)2388{2389	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);2390	unsigned int offset, bit;2391	u32 value;2392 2393	offset = data->hwirq / 32;2394	bit = data->hwirq % 32;2395 2396	/* clear wake status */2397	writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));2398 2399	/* route wake to tier 2 */2400	value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));2401 2402	if (!on)2403		value &= ~(1 << bit);2404	else2405		value |= 1 << bit;2406 2407	writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));2408 2409	/* enable wakeup event */2410	writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));2411 2412	return 0;2413}2414 2415static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)2416{2417	struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);2418	u32 value;2419 2420	value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));2421 2422	switch (type) {2423	case IRQ_TYPE_EDGE_RISING:2424	case IRQ_TYPE_LEVEL_HIGH:2425		value |= WAKE_AOWAKE_CNTRL_LEVEL;2426		set_bit(data->hwirq, pmc->wake_type_level_map);2427		clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);2428		break;2429 2430	case IRQ_TYPE_EDGE_FALLING:2431	case IRQ_TYPE_LEVEL_LOW:2432		value &= ~WAKE_AOWAKE_CNTRL_LEVEL;2433		clear_bit(data->hwirq, pmc->wake_type_level_map);2434		clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);2435		break;2436 2437	case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:2438		value ^= WAKE_AOWAKE_CNTRL_LEVEL;2439		clear_bit(data->hwirq, pmc->wake_type_level_map);2440		set_bit(data->hwirq, pmc->wake_type_dual_edge_map);2441		break;2442 2443	default:2444		return -EINVAL;2445	}2446 2447	writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));2448 2449	return 0;2450}2451 2452static void tegra_irq_mask_parent(struct irq_data *data)2453{2454	if (data->parent_data)2455		irq_chip_mask_parent(data);2456}2457 2458static void tegra_irq_unmask_parent(struct irq_data *data)2459{2460	if (data->parent_data)2461		irq_chip_unmask_parent(data);2462}2463 2464static void tegra_irq_eoi_parent(struct irq_data *data)2465{2466	if (data->parent_data)2467		irq_chip_eoi_parent(data);2468}2469 2470static int tegra_irq_set_affinity_parent(struct irq_data *data,2471					 const struct cpumask *dest,2472					 bool force)2473{2474	if (data->parent_data)2475		return irq_chip_set_affinity_parent(data, dest, force);2476 2477	return -EINVAL;2478}2479 2480static int tegra_pmc_irq_init(struct tegra_pmc *pmc)2481{2482	struct irq_domain *parent = NULL;2483	struct device_node *np;2484 2485	np = of_irq_find_parent(pmc->dev->of_node);2486	if (np) {2487		parent = irq_find_host(np);2488		of_node_put(np);2489	}2490 2491	if (!parent)2492		return 0;2493 2494	pmc->irq.name = dev_name(pmc->dev);2495	pmc->irq.irq_mask = tegra_irq_mask_parent;2496	pmc->irq.irq_unmask = tegra_irq_unmask_parent;2497	pmc->irq.irq_eoi = tegra_irq_eoi_parent;2498	pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;2499	pmc->irq.irq_set_type = pmc->soc->irq_set_type;2500	pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;2501 2502	pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,2503					       &tegra_pmc_irq_domain_ops, pmc);2504	if (!pmc->domain) {2505		dev_err(pmc->dev, "failed to allocate domain\n");2506		return -ENOMEM;2507	}2508 2509	return 0;2510}2511 2512static int tegra_pmc_clk_notify_cb(struct notifier_block *nb,2513				   unsigned long action, void *ptr)2514{2515	struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);2516	struct clk_notifier_data *data = ptr;2517 2518	switch (action) {2519	case PRE_RATE_CHANGE:2520		mutex_lock(&pmc->powergates_lock);2521		break;2522 2523	case POST_RATE_CHANGE:2524		pmc->rate = data->new_rate;2525		fallthrough;2526 2527	case ABORT_RATE_CHANGE:2528		mutex_unlock(&pmc->powergates_lock);2529		break;2530 2531	default:2532		WARN_ON_ONCE(1);2533		return notifier_from_errno(-EINVAL);2534	}2535 2536	return NOTIFY_OK;2537}2538 2539static void pmc_clk_fence_udelay(u32 offset)2540{2541	tegra_pmc_readl(pmc, offset);2542	/* pmc clk propagation delay 2 us */2543	udelay(2);2544}2545 2546static u8 pmc_clk_mux_get_parent(struct clk_hw *hw)2547{2548	struct pmc_clk *clk = to_pmc_clk(hw);2549	u32 val;2550 2551	val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;2552	val &= PMC_CLK_OUT_MUX_MASK;2553 2554	return val;2555}2556 2557static int pmc_clk_mux_set_parent(struct clk_hw *hw, u8 index)2558{2559	struct pmc_clk *clk = to_pmc_clk(hw);2560	u32 val;2561 2562	val = tegra_pmc_readl(pmc, clk->offs);2563	val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift);2564	val |= index << clk->mux_shift;2565	tegra_pmc_writel(pmc, val, clk->offs);2566	pmc_clk_fence_udelay(clk->offs);2567 2568	return 0;2569}2570 2571static int pmc_clk_is_enabled(struct clk_hw *hw)2572{2573	struct pmc_clk *clk = to_pmc_clk(hw);2574	u32 val;2575 2576	val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);2577 2578	return val ? 1 : 0;2579}2580 2581static void pmc_clk_set_state(unsigned long offs, u32 shift, int state)2582{2583	u32 val;2584 2585	val = tegra_pmc_readl(pmc, offs);2586	val = state ? (val | BIT(shift)) : (val & ~BIT(shift));2587	tegra_pmc_writel(pmc, val, offs);2588	pmc_clk_fence_udelay(offs);2589}2590 2591static int pmc_clk_enable(struct clk_hw *hw)2592{2593	struct pmc_clk *clk = to_pmc_clk(hw);2594 2595	pmc_clk_set_state(clk->offs, clk->force_en_shift, 1);2596 2597	return 0;2598}2599 2600static void pmc_clk_disable(struct clk_hw *hw)2601{2602	struct pmc_clk *clk = to_pmc_clk(hw);2603 2604	pmc_clk_set_state(clk->offs, clk->force_en_shift, 0);2605}2606 2607static const struct clk_ops pmc_clk_ops = {2608	.get_parent = pmc_clk_mux_get_parent,2609	.set_parent = pmc_clk_mux_set_parent,2610	.determine_rate = __clk_mux_determine_rate,2611	.is_enabled = pmc_clk_is_enabled,2612	.enable = pmc_clk_enable,2613	.disable = pmc_clk_disable,2614};2615 2616static struct clk *2617tegra_pmc_clk_out_register(struct tegra_pmc *pmc,2618			   const struct pmc_clk_init_data *data,2619			   unsigned long offset)2620{2621	struct clk_init_data init;2622	struct pmc_clk *pmc_clk;2623 2624	pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);2625	if (!pmc_clk)2626		return ERR_PTR(-ENOMEM);2627 2628	init.name = data->name;2629	init.ops = &pmc_clk_ops;2630	init.parent_names = data->parents;2631	init.num_parents = data->num_parents;2632	init.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT |2633		     CLK_SET_PARENT_GATE;2634 2635	pmc_clk->hw.init = &init;2636	pmc_clk->offs = offset;2637	pmc_clk->mux_shift = data->mux_shift;2638	pmc_clk->force_en_shift = data->force_en_shift;2639 2640	return clk_register(NULL, &pmc_clk->hw);2641}2642 2643static int pmc_clk_gate_is_enabled(struct clk_hw *hw)2644{2645	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);2646 2647	return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;2648}2649 2650static int pmc_clk_gate_enable(struct clk_hw *hw)2651{2652	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);2653 2654	pmc_clk_set_state(gate->offs, gate->shift, 1);2655 2656	return 0;2657}2658 2659static void pmc_clk_gate_disable(struct clk_hw *hw)2660{2661	struct pmc_clk_gate *gate = to_pmc_clk_gate(hw);2662 2663	pmc_clk_set_state(gate->offs, gate->shift, 0);2664}2665 2666static const struct clk_ops pmc_clk_gate_ops = {2667	.is_enabled = pmc_clk_gate_is_enabled,2668	.enable = pmc_clk_gate_enable,2669	.disable = pmc_clk_gate_disable,2670};2671 2672static struct clk *2673tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,2674			    const char *parent_name, unsigned long offset,2675			    u32 shift)2676{2677	struct clk_init_data init;2678	struct pmc_clk_gate *gate;2679 2680	gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);2681	if (!gate)2682		return ERR_PTR(-ENOMEM);2683 2684	init.name = name;2685	init.ops = &pmc_clk_gate_ops;2686	init.parent_names = &parent_name;2687	init.num_parents = 1;2688	init.flags = 0;2689 2690	gate->hw.init = &init;2691	gate->offs = offset;2692	gate->shift = shift;2693 2694	return clk_register(NULL, &gate->hw);2695}2696 2697static void tegra_pmc_clock_register(struct tegra_pmc *pmc,2698				     struct device_node *np)2699{2700	struct clk *clk;2701	struct clk_onecell_data *clk_data;2702	unsigned int num_clks;2703	int i, err;2704 2705	num_clks = pmc->soc->num_pmc_clks;2706	if (pmc->soc->has_blink_output)2707		num_clks += 1;2708 2709	if (!num_clks)2710		return;2711 2712	clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);2713	if (!clk_data)2714		return;2715 2716	clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,2717				      sizeof(*clk_data->clks), GFP_KERNEL);2718	if (!clk_data->clks)2719		return;2720 2721	clk_data->clk_num = TEGRA_PMC_CLK_MAX;2722 2723	for (i = 0; i < TEGRA_PMC_CLK_MAX; i++)2724		clk_data->clks[i] = ERR_PTR(-ENOENT);2725 2726	for (i = 0; i < pmc->soc->num_pmc_clks; i++) {2727		const struct pmc_clk_init_data *data;2728 2729		data = pmc->soc->pmc_clks_data + i;2730 2731		clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);2732		if (IS_ERR(clk)) {2733			dev_warn(pmc->dev, "unable to register clock %s: %d\n",2734				 data->name, PTR_ERR_OR_ZERO(clk));2735			return;2736		}2737 2738		err = clk_register_clkdev(clk, data->name, NULL);2739		if (err) {2740			dev_warn(pmc->dev,2741				 "unable to register %s clock lookup: %d\n",2742				 data->name, err);2743			return;2744		}2745 2746		clk_data->clks[data->clk_id] = clk;2747	}2748 2749	if (pmc->soc->has_blink_output) {2750		tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);2751		clk = tegra_pmc_clk_gate_register(pmc,2752						  "pmc_blink_override",2753						  "clk_32k",2754						  PMC_DPD_PADS_ORIDE,2755						  PMC_DPD_PADS_ORIDE_BLINK);2756		if (IS_ERR(clk)) {2757			dev_warn(pmc->dev,2758				 "unable to register pmc_blink_override: %d\n",2759				 PTR_ERR_OR_ZERO(clk));2760			return;2761		}2762 2763		clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",2764						  "pmc_blink_override",2765						  PMC_CNTRL,2766						  PMC_CNTRL_BLINK_EN);2767		if (IS_ERR(clk)) {2768			dev_warn(pmc->dev,2769				 "unable to register pmc_blink: %d\n",2770				 PTR_ERR_OR_ZERO(clk));2771			return;2772		}2773 2774		err = clk_register_clkdev(clk, "pmc_blink", NULL);2775		if (err) {2776			dev_warn(pmc->dev,2777				 "unable to register pmc_blink lookup: %d\n",2778				 err);2779			return;2780		}2781 2782		clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk;2783	}2784 2785	err = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);2786	if (err)2787		dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",2788			 err);2789}2790 2791static const struct regmap_range pmc_usb_sleepwalk_ranges[] = {2792	regmap_reg_range(PMC_USB_DEBOUNCE_DEL, PMC_USB_AO),2793	regmap_reg_range(PMC_UTMIP_UHSIC_TRIGGERS, PMC_UTMIP_UHSIC_SAVED_STATE),2794	regmap_reg_range(PMC_UTMIP_TERM_PAD_CFG, PMC_UTMIP_UHSIC_FAKE),2795	regmap_reg_range(PMC_UTMIP_UHSIC_LINE_WAKEUP, PMC_UTMIP_UHSIC_LINE_WAKEUP),2796	regmap_reg_range(PMC_UTMIP_BIAS_MASTER_CNTRL, PMC_UTMIP_MASTER_CONFIG),2797	regmap_reg_range(PMC_UTMIP_UHSIC2_TRIGGERS, PMC_UTMIP_MASTER2_CONFIG),2798	regmap_reg_range(PMC_UTMIP_PAD_CFG0, PMC_UTMIP_UHSIC_SLEEP_CFG1),2799	regmap_reg_range(PMC_UTMIP_SLEEPWALK_P3, PMC_UTMIP_SLEEPWALK_P3),2800};2801 2802static const struct regmap_access_table pmc_usb_sleepwalk_table = {2803	.yes_ranges = pmc_usb_sleepwalk_ranges,2804	.n_yes_ranges = ARRAY_SIZE(pmc_usb_sleepwalk_ranges),2805};2806 2807static int tegra_pmc_regmap_readl(void *context, unsigned int offset, unsigned int *value)2808{2809	struct tegra_pmc *pmc = context;2810 2811	*value = tegra_pmc_readl(pmc, offset);2812	return 0;2813}2814 2815static int tegra_pmc_regmap_writel(void *context, unsigned int offset, unsigned int value)2816{2817	struct tegra_pmc *pmc = context;2818 2819	tegra_pmc_writel(pmc, value, offset);2820	return 0;2821}2822 2823static const struct regmap_config usb_sleepwalk_regmap_config = {2824	.name = "usb_sleepwalk",2825	.reg_bits = 32,2826	.val_bits = 32,2827	.reg_stride = 4,2828	.fast_io = true,2829	.rd_table = &pmc_usb_sleepwalk_table,2830	.wr_table = &pmc_usb_sleepwalk_table,2831	.reg_read = tegra_pmc_regmap_readl,2832	.reg_write = tegra_pmc_regmap_writel,2833};2834 2835static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)2836{2837	struct regmap *regmap;2838	int err;2839 2840	if (pmc->soc->has_usb_sleepwalk) {2841		regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);2842		if (IS_ERR(regmap)) {2843			err = PTR_ERR(regmap);2844			dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);2845			return err;2846		}2847	}2848 2849	return 0;2850}2851 2852static void tegra_pmc_reset_suspend_mode(void *data)2853{2854	pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;2855}2856 2857static int tegra_pmc_probe(struct platform_device *pdev)2858{2859	void __iomem *base;2860	struct resource *res;2861	int err;2862 2863	/*2864	 * Early initialisation should have configured an initial2865	 * register mapping and setup the soc data pointer. If these2866	 * are not valid then something went badly wrong!2867	 */2868	if (WARN_ON(!pmc->base || !pmc->soc))2869		return -ENODEV;2870 2871	err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);2872	if (err < 0)2873		return err;2874 2875	err = devm_add_action_or_reset(&pdev->dev, tegra_pmc_reset_suspend_mode,2876				       NULL);2877	if (err)2878		return err;2879 2880	/* take over the memory region from the early initialization */2881	base = devm_platform_ioremap_resource(pdev, 0);2882	if (IS_ERR(base))2883		return PTR_ERR(base);2884 2885	if (pmc->soc->has_single_mmio_aperture) {2886		pmc->wake = base;2887		pmc->aotag = base;2888		pmc->scratch = base;2889	} else {2890		pmc->wake = devm_platform_ioremap_resource_byname(pdev, "wake");2891		if (IS_ERR(pmc->wake))2892			return PTR_ERR(pmc->wake);2893 2894		pmc->aotag = devm_platform_ioremap_resource_byname(pdev, "aotag");2895		if (IS_ERR(pmc->aotag))2896			return PTR_ERR(pmc->aotag);2897 2898		/* "scratch" is an optional aperture */2899		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,2900						"scratch");2901		if (res) {2902			pmc->scratch = devm_ioremap_resource(&pdev->dev, res);2903			if (IS_ERR(pmc->scratch))2904				return PTR_ERR(pmc->scratch);2905		} else {2906			pmc->scratch = NULL;2907		}2908	}2909 2910	pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk");2911	if (IS_ERR(pmc->clk))2912		return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk),2913				     "failed to get pclk\n");2914 2915	/*2916	 * PMC should be last resort for restarting since it soft-resets2917	 * CPU without resetting everything else.2918	 */2919	if (pmc->scratch) {2920		err = devm_register_reboot_notifier(&pdev->dev,2921						    &tegra_pmc_reboot_notifier);2922		if (err) {2923			dev_err(&pdev->dev,2924				"unable to register reboot notifier, %d\n",2925				err);2926			return err;2927		}2928	}2929 2930	err = devm_register_sys_off_handler(&pdev->dev,2931					    SYS_OFF_MODE_RESTART,2932					    SYS_OFF_PRIO_LOW,2933					    tegra_pmc_restart_handler, NULL);2934	if (err) {2935		dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",2936			err);2937		return err;2938	}2939 2940	/*2941	 * PMC should be primary power-off method if it soft-resets CPU,2942	 * asking bootloader to shutdown hardware.2943	 */2944	err = devm_register_sys_off_handler(&pdev->dev,2945					    SYS_OFF_MODE_POWER_OFF,2946					    SYS_OFF_PRIO_FIRMWARE,2947					    tegra_pmc_power_off_handler, NULL);2948	if (err) {2949		dev_err(&pdev->dev, "failed to register sys-off handler: %d\n",2950			err);2951		return err;2952	}2953 2954	/*2955	 * PCLK clock rate can't be retrieved using CLK API because it2956	 * causes lockup if CPU enters LP2 idle state from some other2957	 * CLK notifier, hence we're caching the rate's value locally.2958	 */2959	if (pmc->clk) {2960		pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;2961		err = devm_clk_notifier_register(&pdev->dev, pmc->clk,2962						 &pmc->clk_nb);2963		if (err) {2964			dev_err(&pdev->dev,2965				"failed to register clk notifier\n");2966			return err;2967		}2968 2969		pmc->rate = clk_get_rate(pmc->clk);2970	}2971 2972	pmc->dev = &pdev->dev;2973 2974	err = tegra_pmc_init(pmc);2975	if (err < 0) {2976		dev_err(&pdev->dev, "failed to initialize PMC: %d\n", err);2977		return err;2978	}2979 2980	tegra_pmc_init_tsense_reset(pmc);2981 2982	tegra_pmc_reset_sysfs_init(pmc);2983 2984	err = tegra_pmc_pinctrl_init(pmc);2985	if (err)2986		goto cleanup_sysfs;2987 2988	err = tegra_pmc_regmap_init(pmc);2989	if (err < 0)2990		goto cleanup_sysfs;2991 2992	err = tegra_powergate_init(pmc, pdev->dev.of_node);2993	if (err < 0)2994		goto cleanup_powergates;2995 2996	err = tegra_pmc_irq_init(pmc);2997	if (err < 0)2998		goto cleanup_powergates;2999 3000	mutex_lock(&pmc->powergates_lock);3001	iounmap(pmc->base);3002	pmc->base = base;3003	mutex_unlock(&pmc->powergates_lock);3004 3005	tegra_pmc_clock_register(pmc, pdev->dev.of_node);3006	platform_set_drvdata(pdev, pmc);3007	tegra_pm_init_suspend();3008 3009	/* Some wakes require specific filter configuration */3010	if (pmc->soc->set_wake_filters)3011		pmc->soc->set_wake_filters(pmc);3012 3013	debugfs_create_file("powergate", 0444, NULL, NULL, &powergate_fops);3014 3015	return 0;3016 3017cleanup_powergates:3018	tegra_powergate_remove_all(pdev->dev.of_node);3019cleanup_sysfs:3020	device_remove_file(&pdev->dev, &dev_attr_reset_reason);3021	device_remove_file(&pdev->dev, &dev_attr_reset_level);3022 3023	return err;3024}3025 3026/*3027 * Ensures that sufficient time is passed for a register write to3028 * serialize into the 32KHz domain.3029 */3030static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset)3031{3032	writel(value, pmc->wake + offset);3033	udelay(130);3034}3035 3036static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level)3037{3038	unsigned int offset = WAKE_AOWAKE_CNTRL(wake);3039	u32 value;3040 3041	value = readl(pmc->wake + offset);3042	if (level)3043		value |= WAKE_AOWAKE_CNTRL_LEVEL;3044	else3045		value &= ~WAKE_AOWAKE_CNTRL_LEVEL;3046 3047	writel(value, pmc->wake + offset);3048}3049 3050static void wke_write_wake_levels(struct tegra_pmc *pmc)3051{3052	unsigned int i;3053 3054	for (i = 0; i < pmc->soc->max_wake_events; i++)3055		wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map));3056}3057 3058static void wke_clear_sw_wake_status(struct tegra_pmc *pmc)3059{3060	wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0);3061}3062 3063static void wke_read_sw_wake_status(struct tegra_pmc *pmc)3064{3065	unsigned long status;3066	unsigned int wake, i;3067 3068	for (i = 0; i < pmc->soc->max_wake_events; i++)3069		wke_write_wake_level(pmc, i, 0);3070 3071	wke_clear_sw_wake_status(pmc);3072 3073	wke_32kwritel(pmc, 1, WAKE_LATCH_SW);3074 3075	/*3076	 * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to3077	 * obtain the current status of the input wake signals, change3078	 * the polarity of the wake level from 0->1 while latching to force3079	 * a positive edge if the sampled signal is '1'.3080	 */3081	for (i = 0; i < pmc->soc->max_wake_events; i++)3082		wke_write_wake_level(pmc, i, 1);3083 3084	/*3085	 * Wait for the update to be synced into the 32kHz domain,3086	 * and let enough time lapse, so that the wake signals have time to3087	 * be sampled.3088	 */3089	udelay(300);3090 3091	wke_32kwritel(pmc, 0, WAKE_LATCH_SW);3092 3093	bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events);3094 3095	for (i = 0; i < pmc->soc->max_wake_vectors; i++) {3096		status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i));3097 3098		for_each_set_bit(wake, &status, 32)3099			set_bit(wake + (i * 32), pmc->wake_sw_status_map);3100	}3101}3102 3103static void wke_clear_wake_status(struct tegra_pmc *pmc)3104{3105	unsigned long status;3106	unsigned int i, wake;3107	u32 mask;3108 3109	for (i = 0; i < pmc->soc->max_wake_vectors; i++) {3110		mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));3111		status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;3112 3113		for_each_set_bit(wake, &status, 32)3114			wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake));3115	}3116}3117 3118/* translate sc7 wake sources back into IRQs to catch edge triggered wakeups */3119static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index,3120					     unsigned long status)3121{3122	unsigned int wake;3123 3124	dev_dbg(pmc->dev, "Wake[%d:%d]  status=%#lx\n", (index * 32) + 31, index * 32, status);3125 3126	for_each_set_bit(wake, &status, 32) {3127		irq_hw_number_t hwirq = wake + 32 * index;3128		struct irq_desc *desc;3129		unsigned int irq;3130 3131		irq = irq_find_mapping(pmc->domain, hwirq);3132 3133		desc = irq_to_desc(irq);3134		if (!desc || !desc->action || !desc->action->name) {3135			dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq);3136			continue;3137		}3138 3139		dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name);3140		generic_handle_irq(irq);3141	}3142}3143 3144static void tegra186_pmc_wake_syscore_resume(void)3145{3146	u32 status, mask;3147	unsigned int i;3148 3149	for (i = 0; i < pmc->soc->max_wake_vectors; i++) {3150		mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));3151		status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;3152 3153		tegra186_pmc_process_wake_events(pmc, i, status);3154	}3155}3156 3157static int tegra186_pmc_wake_syscore_suspend(void)3158{3159	wke_read_sw_wake_status(pmc);3160 3161	/* flip the wakeup trigger for dual-edge triggered pads3162	 * which are currently asserting as wakeups3163	 */3164	bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map,3165		      pmc->wake_sw_status_map, pmc->soc->max_wake_events);3166	bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map,3167		  pmc->wake_type_level_map, pmc->soc->max_wake_events);3168 3169	/* Clear PMC Wake Status registers while going to suspend */3170	wke_clear_wake_status(pmc);3171	wke_write_wake_levels(pmc);3172 3173	return 0;3174}3175 3176#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)3177static int tegra_pmc_suspend(struct device *dev)3178{3179	struct tegra_pmc *pmc = dev_get_drvdata(dev);3180 3181	tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);3182 3183	return 0;3184}3185 3186static int tegra_pmc_resume(struct device *dev)3187{3188	struct tegra_pmc *pmc = dev_get_drvdata(dev);3189 3190	tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);3191 3192	return 0;3193}3194 3195static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);3196 3197#endif3198 3199static const char * const tegra20_powergates[] = {3200	[TEGRA_POWERGATE_CPU] = "cpu",3201	[TEGRA_POWERGATE_3D] = "td",3202	[TEGRA_POWERGATE_VENC] = "venc",3203	[TEGRA_POWERGATE_VDEC] = "vdec",3204	[TEGRA_POWERGATE_PCIE] = "pcie",3205	[TEGRA_POWERGATE_L2] = "l2",3206	[TEGRA_POWERGATE_MPE] = "mpe",3207};3208 3209static const struct tegra_pmc_regs tegra20_pmc_regs = {3210	.scratch0 = 0x50,3211	.rst_status = 0x1b4,3212	.rst_source_shift = 0x0,3213	.rst_source_mask = 0x7,3214	.rst_level_shift = 0x0,3215	.rst_level_mask = 0x0,3216};3217 3218static void tegra20_pmc_init(struct tegra_pmc *pmc)3219{3220	u32 value, osc, pmu, off;3221 3222	/* Always enable CPU power request */3223	value = tegra_pmc_readl(pmc, PMC_CNTRL);3224	value |= PMC_CNTRL_CPU_PWRREQ_OE;3225	tegra_pmc_writel(pmc, value, PMC_CNTRL);3226 3227	value = tegra_pmc_readl(pmc, PMC_CNTRL);3228 3229	if (pmc->sysclkreq_high)3230		value &= ~PMC_CNTRL_SYSCLK_POLARITY;3231	else3232		value |= PMC_CNTRL_SYSCLK_POLARITY;3233 3234	if (pmc->corereq_high)3235		value &= ~PMC_CNTRL_PWRREQ_POLARITY;3236	else3237		value |= PMC_CNTRL_PWRREQ_POLARITY;3238 3239	/* configure the output polarity while the request is tristated */3240	tegra_pmc_writel(pmc, value, PMC_CNTRL);3241 3242	/* now enable the request */3243	value = tegra_pmc_readl(pmc, PMC_CNTRL);3244	value |= PMC_CNTRL_SYSCLK_OE;3245	tegra_pmc_writel(pmc, value, PMC_CNTRL);3246 3247	/* program core timings which are applicable only for suspend state */3248	if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {3249		osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);3250		pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);3251		off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);3252		tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),3253				 PMC_COREPWRGOOD_TIMER);3254		tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);3255	}3256}3257 3258static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,3259					   struct device_node *np,3260					   bool invert)3261{3262	u32 value;3263 3264	value = tegra_pmc_readl(pmc, PMC_CNTRL);3265 3266	if (invert)3267		value |= PMC_CNTRL_INTR_POLARITY;3268	else3269		value &= ~PMC_CNTRL_INTR_POLARITY;3270 3271	tegra_pmc_writel(pmc, value, PMC_CNTRL);3272}3273 3274static const struct tegra_pmc_soc tegra20_pmc_soc = {3275	.supports_core_domain = true,3276	.num_powergates = ARRAY_SIZE(tegra20_powergates),3277	.powergates = tegra20_powergates,3278	.num_cpu_powergates = 0,3279	.cpu_powergates = NULL,3280	.has_tsense_reset = false,3281	.has_gpu_clamps = false,3282	.needs_mbist_war = false,3283	.has_impl_33v_pwr = false,3284	.maybe_tz_only = false,3285	.num_io_pads = 0,3286	.io_pads = NULL,3287	.num_pin_descs = 0,3288	.pin_descs = NULL,3289	.regs = &tegra20_pmc_regs,3290	.init = tegra20_pmc_init,3291	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,3292	.powergate_set = tegra20_powergate_set,3293	.reset_sources = NULL,3294	.num_reset_sources = 0,3295	.reset_levels = NULL,3296	.num_reset_levels = 0,3297	.pmc_clks_data = NULL,3298	.num_pmc_clks = 0,3299	.has_blink_output = true,3300	.has_usb_sleepwalk = true,3301	.has_single_mmio_aperture = true,3302};3303 3304static const char * const tegra30_powergates[] = {3305	[TEGRA_POWERGATE_CPU] = "cpu0",3306	[TEGRA_POWERGATE_3D] = "td",3307	[TEGRA_POWERGATE_VENC] = "venc",3308	[TEGRA_POWERGATE_VDEC] = "vdec",3309	[TEGRA_POWERGATE_PCIE] = "pcie",3310	[TEGRA_POWERGATE_L2] = "l2",3311	[TEGRA_POWERGATE_MPE] = "mpe",3312	[TEGRA_POWERGATE_HEG] = "heg",3313	[TEGRA_POWERGATE_SATA] = "sata",3314	[TEGRA_POWERGATE_CPU1] = "cpu1",3315	[TEGRA_POWERGATE_CPU2] = "cpu2",3316	[TEGRA_POWERGATE_CPU3] = "cpu3",3317	[TEGRA_POWERGATE_CELP] = "celp",3318	[TEGRA_POWERGATE_3D1] = "td2",3319};3320 3321static const u8 tegra30_cpu_powergates[] = {3322	TEGRA_POWERGATE_CPU,3323	TEGRA_POWERGATE_CPU1,3324	TEGRA_POWERGATE_CPU2,3325	TEGRA_POWERGATE_CPU3,3326};3327 3328static const char * const tegra30_reset_sources[] = {3329	"POWER_ON_RESET",3330	"WATCHDOG",3331	"SENSOR",3332	"SW_MAIN",3333	"LP0"3334};3335 3336static const struct tegra_pmc_soc tegra30_pmc_soc = {3337	.supports_core_domain = true,3338	.num_powergates = ARRAY_SIZE(tegra30_powergates),3339	.powergates = tegra30_powergates,3340	.num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),3341	.cpu_powergates = tegra30_cpu_powergates,3342	.has_tsense_reset = true,3343	.has_gpu_clamps = false,3344	.needs_mbist_war = false,3345	.has_impl_33v_pwr = false,3346	.maybe_tz_only = false,3347	.num_io_pads = 0,3348	.io_pads = NULL,3349	.num_pin_descs = 0,3350	.pin_descs = NULL,3351	.regs = &tegra20_pmc_regs,3352	.init = tegra20_pmc_init,3353	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,3354	.powergate_set = tegra20_powergate_set,3355	.reset_sources = tegra30_reset_sources,3356	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),3357	.reset_levels = NULL,3358	.num_reset_levels = 0,3359	.pmc_clks_data = tegra_pmc_clks_data,3360	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),3361	.has_blink_output = true,3362	.has_usb_sleepwalk = true,3363	.has_single_mmio_aperture = true,3364};3365 3366static const char * const tegra114_powergates[] = {3367	[TEGRA_POWERGATE_CPU] = "crail",3368	[TEGRA_POWERGATE_3D] = "td",3369	[TEGRA_POWERGATE_VENC] = "venc",3370	[TEGRA_POWERGATE_VDEC] = "vdec",3371	[TEGRA_POWERGATE_MPE] = "mpe",3372	[TEGRA_POWERGATE_HEG] = "heg",3373	[TEGRA_POWERGATE_CPU1] = "cpu1",3374	[TEGRA_POWERGATE_CPU2] = "cpu2",3375	[TEGRA_POWERGATE_CPU3] = "cpu3",3376	[TEGRA_POWERGATE_CELP] = "celp",3377	[TEGRA_POWERGATE_CPU0] = "cpu0",3378	[TEGRA_POWERGATE_C0NC] = "c0nc",3379	[TEGRA_POWERGATE_C1NC] = "c1nc",3380	[TEGRA_POWERGATE_DIS] = "dis",3381	[TEGRA_POWERGATE_DISB] = "disb",3382	[TEGRA_POWERGATE_XUSBA] = "xusba",3383	[TEGRA_POWERGATE_XUSBB] = "xusbb",3384	[TEGRA_POWERGATE_XUSBC] = "xusbc",3385};3386 3387static const u8 tegra114_cpu_powergates[] = {3388	TEGRA_POWERGATE_CPU0,3389	TEGRA_POWERGATE_CPU1,3390	TEGRA_POWERGATE_CPU2,3391	TEGRA_POWERGATE_CPU3,3392};3393 3394static const struct tegra_pmc_soc tegra114_pmc_soc = {3395	.supports_core_domain = false,3396	.num_powergates = ARRAY_SIZE(tegra114_powergates),3397	.powergates = tegra114_powergates,3398	.num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),3399	.cpu_powergates = tegra114_cpu_powergates,3400	.has_tsense_reset = true,3401	.has_gpu_clamps = false,3402	.needs_mbist_war = false,3403	.has_impl_33v_pwr = false,3404	.maybe_tz_only = false,3405	.num_io_pads = 0,3406	.io_pads = NULL,3407	.num_pin_descs = 0,3408	.pin_descs = NULL,3409	.regs = &tegra20_pmc_regs,3410	.init = tegra20_pmc_init,3411	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,3412	.powergate_set = tegra114_powergate_set,3413	.reset_sources = tegra30_reset_sources,3414	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),3415	.reset_levels = NULL,3416	.num_reset_levels = 0,3417	.pmc_clks_data = tegra_pmc_clks_data,3418	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),3419	.has_blink_output = true,3420	.has_usb_sleepwalk = true,3421	.has_single_mmio_aperture = true,3422};3423 3424static const char * const tegra124_powergates[] = {3425	[TEGRA_POWERGATE_CPU] = "crail",3426	[TEGRA_POWERGATE_3D] = "3d",3427	[TEGRA_POWERGATE_VENC] = "venc",3428	[TEGRA_POWERGATE_PCIE] = "pcie",3429	[TEGRA_POWERGATE_VDEC] = "vdec",3430	[TEGRA_POWERGATE_MPE] = "mpe",3431	[TEGRA_POWERGATE_HEG] = "heg",3432	[TEGRA_POWERGATE_SATA] = "sata",3433	[TEGRA_POWERGATE_CPU1] = "cpu1",3434	[TEGRA_POWERGATE_CPU2] = "cpu2",3435	[TEGRA_POWERGATE_CPU3] = "cpu3",3436	[TEGRA_POWERGATE_CELP] = "celp",3437	[TEGRA_POWERGATE_CPU0] = "cpu0",3438	[TEGRA_POWERGATE_C0NC] = "c0nc",3439	[TEGRA_POWERGATE_C1NC] = "c1nc",3440	[TEGRA_POWERGATE_SOR] = "sor",3441	[TEGRA_POWERGATE_DIS] = "dis",3442	[TEGRA_POWERGATE_DISB] = "disb",3443	[TEGRA_POWERGATE_XUSBA] = "xusba",3444	[TEGRA_POWERGATE_XUSBB] = "xusbb",3445	[TEGRA_POWERGATE_XUSBC] = "xusbc",3446	[TEGRA_POWERGATE_VIC] = "vic",3447	[TEGRA_POWERGATE_IRAM] = "iram",3448};3449 3450static const u8 tegra124_cpu_powergates[] = {3451	TEGRA_POWERGATE_CPU0,3452	TEGRA_POWERGATE_CPU1,3453	TEGRA_POWERGATE_CPU2,3454	TEGRA_POWERGATE_CPU3,3455};3456 3457#define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name)	\3458	((struct tegra_io_pad_soc) {					\3459		.id		= (_id),				\3460		.dpd		= (_dpd),				\3461		.request	= (_request),				\3462		.status		= (_status),				\3463		.voltage	= (_voltage),				\3464		.name		= (_name),				\3465	})3466 3467#define TEGRA_IO_PIN_DESC(_id, _name)	\3468	((struct pinctrl_pin_desc) {	\3469		.number	= (_id),	\3470		.name	= (_name),	\3471	})3472 3473static const struct tegra_io_pad_soc tegra124_io_pads[] = {3474	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, "audio"),3475	TEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, "bb"),3476	TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, "cam"),3477	TEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, "comp"),3478	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),3479	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),3480	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),3481	TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),3482	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),3483	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),3484	TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),3485	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),3486	TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),3487	TEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, "hv"),3488	TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),3489	TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),3490	TEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, "nand"),3491	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),3492	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),3493	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),3494	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, "pex-cntrl"),3495	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, "sdmmc1"),3496	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, "sdmmc3"),3497	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, "sdmmc4"),3498	TEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, "sys_ddc"),3499	TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, "uart"),3500	TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),3501	TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),3502	TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),3503	TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb_bias"),3504};3505 3506static const struct pinctrl_pin_desc tegra124_pin_descs[] = {3507	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),3508	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_BB, "bb"),3509	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),3510	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_COMP, "comp"),3511	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),3512	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),3513	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),3514	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),3515	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),3516	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),3517	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),3518	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),3519	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),3520	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HV, "hv"),3521	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),3522	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),3523	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_NAND, "nand"),3524	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),3525	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),3526	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),3527	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),3528	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),3529	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),3530	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),3531	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SYS_DDC, "sys_ddc"),3532	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),3533	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),3534	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),3535	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),3536	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb_bias"),3537};3538 3539static const struct tegra_pmc_soc tegra124_pmc_soc = {3540	.supports_core_domain = false,3541	.num_powergates = ARRAY_SIZE(tegra124_powergates),3542	.powergates = tegra124_powergates,3543	.num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),3544	.cpu_powergates = tegra124_cpu_powergates,3545	.has_tsense_reset = true,3546	.has_gpu_clamps = true,3547	.needs_mbist_war = false,3548	.has_impl_33v_pwr = false,3549	.maybe_tz_only = false,3550	.num_io_pads = ARRAY_SIZE(tegra124_io_pads),3551	.io_pads = tegra124_io_pads,3552	.num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),3553	.pin_descs = tegra124_pin_descs,3554	.regs = &tegra20_pmc_regs,3555	.init = tegra20_pmc_init,3556	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,3557	.powergate_set = tegra114_powergate_set,3558	.reset_sources = tegra30_reset_sources,3559	.num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),3560	.reset_levels = NULL,3561	.num_reset_levels = 0,3562	.pmc_clks_data = tegra_pmc_clks_data,3563	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),3564	.has_blink_output = true,3565	.has_usb_sleepwalk = true,3566	.has_single_mmio_aperture = true,3567};3568 3569static const char * const tegra210_powergates[] = {3570	[TEGRA_POWERGATE_CPU] = "crail",3571	[TEGRA_POWERGATE_3D] = "3d",3572	[TEGRA_POWERGATE_VENC] = "venc",3573	[TEGRA_POWERGATE_PCIE] = "pcie",3574	[TEGRA_POWERGATE_MPE] = "mpe",3575	[TEGRA_POWERGATE_SATA] = "sata",3576	[TEGRA_POWERGATE_CPU1] = "cpu1",3577	[TEGRA_POWERGATE_CPU2] = "cpu2",3578	[TEGRA_POWERGATE_CPU3] = "cpu3",3579	[TEGRA_POWERGATE_CPU0] = "cpu0",3580	[TEGRA_POWERGATE_C0NC] = "c0nc",3581	[TEGRA_POWERGATE_SOR] = "sor",3582	[TEGRA_POWERGATE_DIS] = "dis",3583	[TEGRA_POWERGATE_DISB] = "disb",3584	[TEGRA_POWERGATE_XUSBA] = "xusba",3585	[TEGRA_POWERGATE_XUSBB] = "xusbb",3586	[TEGRA_POWERGATE_XUSBC] = "xusbc",3587	[TEGRA_POWERGATE_VIC] = "vic",3588	[TEGRA_POWERGATE_IRAM] = "iram",3589	[TEGRA_POWERGATE_NVDEC] = "nvdec",3590	[TEGRA_POWERGATE_NVJPG] = "nvjpg",3591	[TEGRA_POWERGATE_AUD] = "aud",3592	[TEGRA_POWERGATE_DFD] = "dfd",3593	[TEGRA_POWERGATE_VE2] = "ve2",3594};3595 3596static const u8 tegra210_cpu_powergates[] = {3597	TEGRA_POWERGATE_CPU0,3598	TEGRA_POWERGATE_CPU1,3599	TEGRA_POWERGATE_CPU2,3600	TEGRA_POWERGATE_CPU3,3601};3602 3603static const struct tegra_io_pad_soc tegra210_io_pads[] = {3604	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, "audio"),3605	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, "audio-hv"),3606	TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, "cam"),3607	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, "csia"),3608	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, "csib"),3609	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, "csic"),3610	TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, "csid"),3611	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, "csie"),3612	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, "csif"),3613	TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, "dbg"),3614	TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, "debug-nonao"),3615	TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, "dmic"),3616	TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, "dp"),3617	TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, "dsi"),3618	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, "dsib"),3619	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, "dsic"),3620	TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, "dsid"),3621	TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, "emmc"),3622	TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, "emmc2"),3623	TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, "gpio"),3624	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, "hdmi"),3625	TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, "hsic"),3626	TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, "lvds"),3627	TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, "mipi-bias"),3628	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, "pex-bias"),3629	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, "pex-clk1"),3630	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, "pex-clk2"),3631	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, "pex-cntrl"),3632	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, "sdmmc1"),3633	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, "sdmmc3"),3634	TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, "spi"),3635	TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, "spi-hv"),3636	TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, "uart"),3637	TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, "usb0"),3638	TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, "usb1"),3639	TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, "usb2"),3640	TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, "usb3"),3641	TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, "usb-bias"),3642};3643 3644static const struct pinctrl_pin_desc tegra210_pin_descs[] = {3645	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),3646	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),3647	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),3648	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),3649	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),3650	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),3651	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),3652	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),3653	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),3654	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),3655	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"),3656	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"),3657	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"),3658	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),3659	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),3660	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),3661	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),3662	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"),3663	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"),3664	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"),3665	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"),3666	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),3667	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"),3668	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),3669	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"),3670	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),3671	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),3672	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),3673	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"),3674	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"),3675	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),3676	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"),3677	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),3678	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),3679	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),3680	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),3681	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"),3682	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),3683};3684 3685static const char * const tegra210_reset_sources[] = {3686	"POWER_ON_RESET",3687	"WATCHDOG",3688	"SENSOR",3689	"SW_MAIN",3690	"LP0",3691	"AOTAG"3692};3693 3694static const struct tegra_wake_event tegra210_wake_events[] = {3695	TEGRA_WAKE_IRQ("rtc", 16, 2),3696	TEGRA_WAKE_IRQ("pmu", 51, 86),3697};3698 3699static const struct tegra_pmc_soc tegra210_pmc_soc = {3700	.supports_core_domain = false,3701	.num_powergates = ARRAY_SIZE(tegra210_powergates),3702	.powergates = tegra210_powergates,3703	.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),3704	.cpu_powergates = tegra210_cpu_powergates,3705	.has_tsense_reset = true,3706	.has_gpu_clamps = true,3707	.needs_mbist_war = true,3708	.has_impl_33v_pwr = false,3709	.maybe_tz_only = true,3710	.num_io_pads = ARRAY_SIZE(tegra210_io_pads),3711	.io_pads = tegra210_io_pads,3712	.num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),3713	.pin_descs = tegra210_pin_descs,3714	.regs = &tegra20_pmc_regs,3715	.init = tegra20_pmc_init,3716	.setup_irq_polarity = tegra20_pmc_setup_irq_polarity,3717	.powergate_set = tegra114_powergate_set,3718	.irq_set_wake = tegra210_pmc_irq_set_wake,3719	.irq_set_type = tegra210_pmc_irq_set_type,3720	.reset_sources = tegra210_reset_sources,3721	.num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),3722	.reset_levels = NULL,3723	.num_reset_levels = 0,3724	.num_wake_events = ARRAY_SIZE(tegra210_wake_events),3725	.wake_events = tegra210_wake_events,3726	.pmc_clks_data = tegra_pmc_clks_data,3727	.num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data),3728	.has_blink_output = true,3729	.has_usb_sleepwalk = true,3730	.has_single_mmio_aperture = true,3731};3732 3733static const struct tegra_io_pad_soc tegra186_io_pads[] = {3734	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),3735	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),3736	TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, "dsi"),3737	TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),3738	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),3739	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),3740	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),3741	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),3742	TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, "usb0"),3743	TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, "usb1"),3744	TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, "usb2"),3745	TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, "usb-bias"),3746	TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),3747	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),3748	TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, "hsic"),3749	TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),3750	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),3751	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),3752	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),3753	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, "sdmmc2-hv"),3754	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),3755	TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),3756	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, "dsib"),3757	TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, "dsic"),3758	TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, "dsid"),3759	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),3760	TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),3761	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),3762	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),3763	TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),3764	TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),3765	TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, "dmic-hv"),3766	TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),3767	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),3768	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),3769	TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),3770	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),3771	TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),3772};3773 3774static const struct pinctrl_pin_desc tegra186_pin_descs[] = {3775	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),3776	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),3777	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"),3778	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),3779	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),3780	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),3781	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),3782	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),3783	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"),3784	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"),3785	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"),3786	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"),3787	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),3788	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),3789	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"),3790	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),3791	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),3792	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),3793	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),3794	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC2_HV, "sdmmc2-hv"),3795	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),3796	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),3797	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"),3798	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"),3799	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"),3800	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),3801	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),3802	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),3803	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),3804	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),3805	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),3806	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC_HV, "dmic-hv"),3807	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),3808	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),3809	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),3810	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),3811	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),3812	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),3813};3814 3815static const struct tegra_pmc_regs tegra186_pmc_regs = {3816	.scratch0 = 0x2000,3817	.rst_status = 0x70,3818	.rst_source_shift = 0x2,3819	.rst_source_mask = 0x3c,3820	.rst_level_shift = 0x0,3821	.rst_level_mask = 0x3,3822};3823 3824static void tegra186_pmc_init(struct tegra_pmc *pmc)3825{3826	pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend;3827	pmc->syscore.resume = tegra186_pmc_wake_syscore_resume;3828 3829	register_syscore_ops(&pmc->syscore);3830}3831 3832static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,3833					    struct device_node *np,3834					    bool invert)3835{3836	struct resource regs;3837	void __iomem *wake;3838	u32 value;3839	int index;3840 3841	index = of_property_match_string(np, "reg-names", "wake");3842	if (index < 0) {3843		dev_err(pmc->dev, "failed to find PMC wake registers\n");3844		return;3845	}3846 3847	of_address_to_resource(np, index, &regs);3848 3849	wake = ioremap(regs.start, resource_size(&regs));3850	if (!wake) {3851		dev_err(pmc->dev, "failed to map PMC wake registers\n");3852		return;3853	}3854 3855	value = readl(wake + WAKE_AOWAKE_CTRL);3856 3857	if (invert)3858		value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;3859	else3860		value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;3861 3862	writel(value, wake + WAKE_AOWAKE_CTRL);3863 3864	iounmap(wake);3865}3866 3867static const char * const tegra186_reset_sources[] = {3868	"SYS_RESET",3869	"AOWDT",3870	"MCCPLEXWDT",3871	"BPMPWDT",3872	"SCEWDT",3873	"SPEWDT",3874	"APEWDT",3875	"BCCPLEXWDT",3876	"SENSOR",3877	"AOTAG",3878	"VFSENSOR",3879	"SWREST",3880	"SC7",3881	"HSM",3882	"CORESIGHT"3883};3884 3885static const char * const tegra186_reset_levels[] = {3886	"L0", "L1", "L2", "WARM"3887};3888 3889static const struct tegra_wake_event tegra186_wake_events[] = {3890	TEGRA_WAKE_IRQ("pmu", 24, 209),3891	TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),3892	TEGRA_WAKE_IRQ("rtc", 73, 10),3893};3894 3895static const struct tegra_pmc_soc tegra186_pmc_soc = {3896	.supports_core_domain = false,3897	.num_powergates = 0,3898	.powergates = NULL,3899	.num_cpu_powergates = 0,3900	.cpu_powergates = NULL,3901	.has_tsense_reset = false,3902	.has_gpu_clamps = false,3903	.needs_mbist_war = false,3904	.has_impl_33v_pwr = true,3905	.maybe_tz_only = false,3906	.num_io_pads = ARRAY_SIZE(tegra186_io_pads),3907	.io_pads = tegra186_io_pads,3908	.num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),3909	.pin_descs = tegra186_pin_descs,3910	.regs = &tegra186_pmc_regs,3911	.init = tegra186_pmc_init,3912	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,3913	.set_wake_filters = tegra186_pmc_set_wake_filters,3914	.irq_set_wake = tegra186_pmc_irq_set_wake,3915	.irq_set_type = tegra186_pmc_irq_set_type,3916	.reset_sources = tegra186_reset_sources,3917	.num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),3918	.reset_levels = tegra186_reset_levels,3919	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),3920	.num_wake_events = ARRAY_SIZE(tegra186_wake_events),3921	.wake_events = tegra186_wake_events,3922	.max_wake_events = 96,3923	.max_wake_vectors = 3,3924	.pmc_clks_data = NULL,3925	.num_pmc_clks = 0,3926	.has_blink_output = false,3927	.has_usb_sleepwalk = false,3928	.has_single_mmio_aperture = false,3929};3930 3931static const struct tegra_io_pad_soc tegra194_io_pads[] = {3932	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, "csia"),3933	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, "csib"),3934	TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, "mipi-bias"),3935	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, "pex-clk-bias"),3936	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, "pex-clk3"),3937	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, "pex-clk2"),3938	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, "pex-clk1"),3939	TEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, "eqos"),3940	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, "pex-clk-2-bias"),3941	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, "pex-clk-2"),3942	TEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, "dap3"),3943	TEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, "dap5"),3944	TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, "uart"),3945	TEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, "pwr-ctl"),3946	TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, "soc-gpio53"),3947	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, "audio"),3948	TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, "gp-pwm2"),3949	TEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, "gp-pwm3"),3950	TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, "soc-gpio12"),3951	TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, "soc-gpio13"),3952	TEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, "soc-gpio10"),3953	TEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, "uart4"),3954	TEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, "uart5"),3955	TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, "dbg"),3956	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, "hdmi-dp3"),3957	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, "hdmi-dp2"),3958	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, "hdmi-dp0"),3959	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, "hdmi-dp1"),3960	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, "pex-cntrl"),3961	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, "pex-ctl2"),3962	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, "pex-l0-rst"),3963	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, "pex-l1-rst"),3964	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, "sdmmc4"),3965	TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, "pex-l5-rst"),3966	TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, "cam"),3967	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, "csic"),3968	TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, "csid"),3969	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, "csie"),3970	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, "csif"),3971	TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, "spi"),3972	TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, "ufs"),3973	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, "csig"),3974	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, "csih"),3975	TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, "edp"),3976	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, "sdmmc1-hv"),3977	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, "sdmmc3-hv"),3978	TEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, "conn"),3979	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, "audio-hv"),3980	TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),3981};3982 3983static const struct pinctrl_pin_desc tegra194_pin_descs[] = {3984	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),3985	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),3986	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"),3987	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_BIAS, "pex-clk-bias"),3988	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK3, "pex-clk3"),3989	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"),3990	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"),3991	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EQOS, "eqos"),3992	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2_BIAS, "pex-clk-2-bias"),3993	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK_2, "pex-clk-2"),3994	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP3, "dap3"),3995	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DAP5, "dap5"),3996	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"),3997	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PWR_CTL, "pwr-ctl"),3998	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO53, "soc-gpio53"),3999	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"),4000	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM2, "gp-pwm2"),4001	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GP_PWM3, "gp-pwm3"),4002	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO12, "soc-gpio12"),4003	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO13, "soc-gpio13"),4004	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SOC_GPIO10, "soc-gpio10"),4005	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART4, "uart4"),4006	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART5, "uart5"),4007	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"),4008	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP3, "hdmi-dp3"),4009	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP2, "hdmi-dp2"),4010	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),4011	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP1, "hdmi-dp1"),4012	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"),4013	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CTL2, "pex-ctl2"),4014	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L0_RST, "pex-l0-rst"),4015	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L1_RST, "pex-l1-rst"),4016	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC4, "sdmmc4"),4017	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_L5_RST, "pex-l5-rst"),4018	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"),4019	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),4020	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),4021	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),4022	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),4023	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"),4024	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),4025	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),4026	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),4027	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),4028	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),4029	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),4030	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CONN, "conn"),4031	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),4032	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),4033};4034 4035static const struct tegra_pmc_regs tegra194_pmc_regs = {4036	.scratch0 = 0x2000,4037	.rst_status = 0x70,4038	.rst_source_shift = 0x2,4039	.rst_source_mask = 0x7c,4040	.rst_level_shift = 0x0,4041	.rst_level_mask = 0x3,4042};4043 4044static const char * const tegra194_reset_sources[] = {4045	"SYS_RESET_N",4046	"AOWDT",4047	"BCCPLEXWDT",4048	"BPMPWDT",4049	"SCEWDT",4050	"SPEWDT",4051	"APEWDT",4052	"LCCPLEXWDT",4053	"SENSOR",4054	"AOTAG",4055	"VFSENSOR",4056	"MAINSWRST",4057	"SC7",4058	"HSM",4059	"CSITE",4060	"RCEWDT",4061	"PVA0WDT",4062	"PVA1WDT",4063	"L1A_ASYNC",4064	"BPMPBOOT",4065	"FUSECRC",4066};4067 4068static const struct tegra_wake_event tegra194_wake_events[] = {4069	TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA194_MAIN_GPIO(G, 4)),4070	TEGRA_WAKE_IRQ("pmu", 24, 209),4071	TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),4072	TEGRA_WAKE_IRQ("rtc", 73, 10),4073	TEGRA_WAKE_SIMPLE("usb3-port-0", 76),4074	TEGRA_WAKE_SIMPLE("usb3-port-1", 77),4075	TEGRA_WAKE_SIMPLE("usb3-port-2-3", 78),4076	TEGRA_WAKE_SIMPLE("usb2-port-0", 79),4077	TEGRA_WAKE_SIMPLE("usb2-port-1", 80),4078	TEGRA_WAKE_SIMPLE("usb2-port-2", 81),4079	TEGRA_WAKE_SIMPLE("usb2-port-3", 82),4080};4081 4082static const struct tegra_pmc_soc tegra194_pmc_soc = {4083	.supports_core_domain = false,4084	.num_powergates = 0,4085	.powergates = NULL,4086	.num_cpu_powergates = 0,4087	.cpu_powergates = NULL,4088	.has_tsense_reset = false,4089	.has_gpu_clamps = false,4090	.needs_mbist_war = false,4091	.has_impl_33v_pwr = true,4092	.maybe_tz_only = false,4093	.num_io_pads = ARRAY_SIZE(tegra194_io_pads),4094	.io_pads = tegra194_io_pads,4095	.num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),4096	.pin_descs = tegra194_pin_descs,4097	.regs = &tegra194_pmc_regs,4098	.init = tegra186_pmc_init,4099	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,4100	.set_wake_filters = tegra186_pmc_set_wake_filters,4101	.irq_set_wake = tegra186_pmc_irq_set_wake,4102	.irq_set_type = tegra186_pmc_irq_set_type,4103	.reset_sources = tegra194_reset_sources,4104	.num_reset_sources = ARRAY_SIZE(tegra194_reset_sources),4105	.reset_levels = tegra186_reset_levels,4106	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),4107	.num_wake_events = ARRAY_SIZE(tegra194_wake_events),4108	.wake_events = tegra194_wake_events,4109	.max_wake_events = 96,4110	.max_wake_vectors = 3,4111	.pmc_clks_data = NULL,4112	.num_pmc_clks = 0,4113	.has_blink_output = false,4114	.has_usb_sleepwalk = false,4115	.has_single_mmio_aperture = false,4116};4117 4118static const struct tegra_io_pad_soc tegra234_io_pads[] = {4119	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, "csia"),4120	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, "csib"),4121	TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, "hdmi-dp0"),4122	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, "csic"),4123	TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, "csid"),4124	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, "csie"),4125	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, "csif"),4126	TEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, "ufs"),4127	TEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, "edp"),4128	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, "sdmmc1-hv"),4129	TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, "sdmmc3-hv"),4130	TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, "audio-hv"),4131	TEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, "ao-hv"),4132	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, "csig"),4133	TEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, "csih"),4134};4135 4136static const struct pinctrl_pin_desc tegra234_pin_descs[] = {4137	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"),4138	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"),4139	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, "hdmi-dp0"),4140	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"),4141	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"),4142	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"),4143	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"),4144	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, "ufs"),4145	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, "edp"),4146	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, "sdmmc1-hv"),4147	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3_HV, "sdmmc3-hv"),4148	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"),4149	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AO_HV, "ao-hv"),4150	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, "csig"),4151	TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, "csih"),4152};4153 4154static const struct tegra_pmc_regs tegra234_pmc_regs = {4155	.scratch0 = 0x2000,4156	.rst_status = 0x70,4157	.rst_source_shift = 0x2,4158	.rst_source_mask = 0xfc,4159	.rst_level_shift = 0x0,4160	.rst_level_mask = 0x3,4161};4162 4163static const char * const tegra234_reset_sources[] = {4164	"SYS_RESET_N",	/* 0x0 */4165	"AOWDT",4166	"BCCPLEXWDT",4167	"BPMPWDT",4168	"SCEWDT",4169	"SPEWDT",4170	"APEWDT",4171	"LCCPLEXWDT",4172	"SENSOR",	/* 0x8 */4173	NULL,4174	NULL,4175	"MAINSWRST",4176	"SC7",4177	"HSM",4178	NULL,4179	"RCEWDT",4180	NULL,		/* 0x10 */4181	NULL,4182	NULL,4183	"BPMPBOOT",4184	"FUSECRC",4185	"DCEWDT",4186	"PSCWDT",4187	"PSC",4188	"CSITE_SW",	/* 0x18 */4189	"POD",4190	"SCPM",4191	"VREFRO_POWERBAD",4192	"VMON",4193	"FMON",4194	"FSI_R5WDT",4195	"FSI_THERM",4196	"FSI_R52C0WDT",	/* 0x20 */4197	"FSI_R52C1WDT",4198	"FSI_R52C2WDT",4199	"FSI_R52C3WDT",4200	"FSI_FMON",4201	"FSI_VMON",	/* 0x25 */4202};4203 4204static const struct tegra_wake_event tegra234_wake_events[] = {4205	TEGRA_WAKE_GPIO("sd-wake", 8, 0, TEGRA234_MAIN_GPIO(G, 7)),4206	TEGRA_WAKE_GPIO("eqos", 20, 0, TEGRA234_MAIN_GPIO(G, 4)),4207	TEGRA_WAKE_IRQ("pmu", 24, 209),4208	TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)),4209	TEGRA_WAKE_GPIO("mgbe", 56, 0, TEGRA234_MAIN_GPIO(Y, 3)),4210	TEGRA_WAKE_IRQ("rtc", 73, 10),4211	TEGRA_WAKE_IRQ("sw-wake", SW_WAKE_ID, 179),4212};4213 4214static const struct tegra_pmc_soc tegra234_pmc_soc = {4215	.supports_core_domain = false,4216	.num_powergates = 0,4217	.powergates = NULL,4218	.num_cpu_powergates = 0,4219	.cpu_powergates = NULL,4220	.has_tsense_reset = false,4221	.has_gpu_clamps = false,4222	.needs_mbist_war = false,4223	.has_impl_33v_pwr = true,4224	.maybe_tz_only = false,4225	.num_io_pads = ARRAY_SIZE(tegra234_io_pads),4226	.io_pads = tegra234_io_pads,4227	.num_pin_descs = ARRAY_SIZE(tegra234_pin_descs),4228	.pin_descs = tegra234_pin_descs,4229	.regs = &tegra234_pmc_regs,4230	.init = tegra186_pmc_init,4231	.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,4232	.set_wake_filters = tegra186_pmc_set_wake_filters,4233	.irq_set_wake = tegra186_pmc_irq_set_wake,4234	.irq_set_type = tegra186_pmc_irq_set_type,4235	.reset_sources = tegra234_reset_sources,4236	.num_reset_sources = ARRAY_SIZE(tegra234_reset_sources),4237	.reset_levels = tegra186_reset_levels,4238	.num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),4239	.num_wake_events = ARRAY_SIZE(tegra234_wake_events),4240	.wake_events = tegra234_wake_events,4241	.max_wake_events = 96,4242	.max_wake_vectors = 3,4243	.pmc_clks_data = NULL,4244	.num_pmc_clks = 0,4245	.has_blink_output = false,4246	.has_single_mmio_aperture = false,4247};4248 4249static const struct of_device_id tegra_pmc_match[] = {4250	{ .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },4251	{ .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },4252	{ .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },4253	{ .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },4254	{ .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },4255	{ .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },4256	{ .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },4257	{ .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },4258	{ .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },4259	{ }4260};4261 4262static void tegra_pmc_sync_state(struct device *dev)4263{4264	int err;4265 4266	/*4267	 * Newer device-trees have power domains, but we need to prepare all4268	 * device drivers with runtime PM and OPP support first, otherwise4269	 * state syncing is unsafe.4270	 */4271	if (!pmc->soc->supports_core_domain)4272		return;4273 4274	/*4275	 * Older device-trees don't have core PD, and thus, there are4276	 * no dependencies that will block the state syncing. We shouldn't4277	 * mark the domain as synced in this case.4278	 */4279	if (!pmc->core_domain_registered)4280		return;4281 4282	pmc->core_domain_state_synced = true;4283 4284	/* this is a no-op if core regulator isn't used */4285	mutex_lock(&pmc->powergates_lock);4286	err = dev_pm_opp_sync_regulators(dev);4287	mutex_unlock(&pmc->powergates_lock);4288 4289	if (err)4290		dev_err(dev, "failed to sync regulators: %d\n", err);4291}4292 4293static struct platform_driver tegra_pmc_driver = {4294	.driver = {4295		.name = "tegra-pmc",4296		.suppress_bind_attrs = true,4297		.of_match_table = tegra_pmc_match,4298#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)4299		.pm = &tegra_pmc_pm_ops,4300#endif4301		.sync_state = tegra_pmc_sync_state,4302	},4303	.probe = tegra_pmc_probe,4304};4305builtin_platform_driver(tegra_pmc_driver);4306 4307static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)4308{4309	u32 value, saved;4310 4311	saved = readl(pmc->base + pmc->soc->regs->scratch0);4312	value = saved ^ 0xffffffff;4313 4314	if (value == 0xffffffff)4315		value = 0xdeadbeef;4316 4317	/* write pattern and read it back */4318	writel(value, pmc->base + pmc->soc->regs->scratch0);4319	value = readl(pmc->base + pmc->soc->regs->scratch0);4320 4321	/* if we read all-zeroes, access is restricted to TZ only */4322	if (value == 0) {4323		pr_info("access to PMC is restricted to TZ\n");4324		return true;4325	}4326 4327	/* restore original value */4328	writel(saved, pmc->base + pmc->soc->regs->scratch0);4329 4330	return false;4331}4332 4333/*4334 * Early initialization to allow access to registers in the very early boot4335 * process.4336 */4337static int __init tegra_pmc_early_init(void)4338{4339	const struct of_device_id *match;4340	struct device_node *np;4341	struct resource regs;4342	unsigned int i;4343	bool invert;4344 4345	mutex_init(&pmc->powergates_lock);4346 4347	np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);4348	if (!np) {4349		/*4350		 * Fall back to legacy initialization for 32-bit ARM only. All4351		 * 64-bit ARM device tree files for Tegra are required to have4352		 * a PMC node.4353		 *4354		 * This is for backwards-compatibility with old device trees4355		 * that didn't contain a PMC node. Note that in this case the4356		 * SoC data can't be matched and therefore powergating is4357		 * disabled.4358		 */4359		if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {4360			pr_warn("DT node not found, powergating disabled\n");4361 4362			regs.start = 0x7000e400;4363			regs.end = 0x7000e7ff;4364			regs.flags = IORESOURCE_MEM;4365 4366			pr_warn("Using memory region %pR\n", &regs);4367		} else {4368			/*4369			 * At this point we're not running on Tegra, so play4370			 * nice with multi-platform kernels.4371			 */4372			return 0;4373		}4374	} else {4375		/*4376		 * Extract information from the device tree if we've found a4377		 * matching node.4378		 */4379		if (of_address_to_resource(np, 0, &regs) < 0) {4380			pr_err("failed to get PMC registers\n");4381			of_node_put(np);4382			return -ENXIO;4383		}4384	}4385 4386	pmc->base = ioremap(regs.start, resource_size(&regs));4387	if (!pmc->base) {4388		pr_err("failed to map PMC registers\n");4389		of_node_put(np);4390		return -ENXIO;4391	}4392 4393	if (of_device_is_available(np)) {4394		pmc->soc = match->data;4395 4396		if (pmc->soc->maybe_tz_only)4397			pmc->tz_only = tegra_pmc_detect_tz_only(pmc);4398 4399		/* Create a bitmap of the available and valid partitions */4400		for (i = 0; i < pmc->soc->num_powergates; i++)4401			if (pmc->soc->powergates[i])4402				set_bit(i, pmc->powergates_available);4403 4404		/*4405		 * Invert the interrupt polarity if a PMC device tree node4406		 * exists and contains the nvidia,invert-interrupt property.4407		 */4408		invert = of_property_read_bool(np, "nvidia,invert-interrupt");4409 4410		pmc->soc->setup_irq_polarity(pmc, np, invert);4411 4412		of_node_put(np);4413	}4414 4415	return 0;4416}4417early_initcall(tegra_pmc_early_init);4418