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1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)2/*3 * SoundWire AMD Manager driver4 *5 * Copyright 2023-24 Advanced Micro Devices, Inc.6 */7 8#include <linux/completion.h>9#include <linux/cleanup.h>10#include <linux/device.h>11#include <linux/io.h>12#include <linux/jiffies.h>13#include <linux/kernel.h>14#include <linux/module.h>15#include <linux/slab.h>16#include <linux/soundwire/sdw.h>17#include <linux/soundwire/sdw_registers.h>18#include <linux/pm_runtime.h>19#include <linux/wait.h>20#include <sound/pcm_params.h>21#include <sound/soc.h>22#include "bus.h"23#include "amd_init.h"24#include "amd_manager.h"25 26#define DRV_NAME "amd_sdw_manager"27 28#define to_amd_sdw(b) container_of(b, struct amd_sdw_manager, bus)29 30static int amd_init_sdw_manager(struct amd_sdw_manager *amd_manager)31{32 u32 val;33 int ret;34 35 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);36 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US,37 AMD_SDW_TIMEOUT);38 if (ret)39 return ret;40 41 /* SoundWire manager bus reset */42 writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);43 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val,44 (val & AMD_SDW_BUS_RESET_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT);45 if (ret)46 return ret;47 48 writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);49 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val,50 ACP_DELAY_US, AMD_SDW_TIMEOUT);51 if (ret) {52 dev_err(amd_manager->dev, "Failed to reset SoundWire manager instance%d\n",53 amd_manager->instance);54 return ret;55 }56 57 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN);58 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US,59 AMD_SDW_TIMEOUT);60}61 62static int amd_enable_sdw_manager(struct amd_sdw_manager *amd_manager)63{64 u32 val;65 66 writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);67 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US,68 AMD_SDW_TIMEOUT);69}70 71static int amd_disable_sdw_manager(struct amd_sdw_manager *amd_manager)72{73 u32 val;74 75 writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN);76 /*77 * After invoking manager disable sequence, check whether78 * manager has executed clock stop sequence. In this case,79 * manager should ignore checking enable status register.80 */81 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);82 if (val)83 return 0;84 return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US,85 AMD_SDW_TIMEOUT);86}87 88static void amd_enable_sdw_interrupts(struct amd_sdw_manager *amd_manager)89{90 u32 val;91 92 mutex_lock(amd_manager->acp_sdw_lock);93 val = sdw_manager_reg_mask_array[amd_manager->instance];94 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance), val, val);95 mutex_unlock(amd_manager->acp_sdw_lock);96 97 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio +98 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);99 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio +100 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);101 writel(AMD_SDW_IRQ_ERROR_MASK, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK);102}103 104static void amd_disable_sdw_interrupts(struct amd_sdw_manager *amd_manager)105{106 u32 irq_mask;107 108 mutex_lock(amd_manager->acp_sdw_lock);109 irq_mask = sdw_manager_reg_mask_array[amd_manager->instance];110 amd_updatel(amd_manager->acp_mmio, ACP_EXTERNAL_INTR_CNTL(amd_manager->instance),111 irq_mask, 0);112 mutex_unlock(amd_manager->acp_sdw_lock);113 114 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);115 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);116 writel(0x00, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK);117}118 119static int amd_deinit_sdw_manager(struct amd_sdw_manager *amd_manager)120{121 amd_disable_sdw_interrupts(amd_manager);122 return amd_disable_sdw_manager(amd_manager);123}124 125static void amd_sdw_set_frameshape(struct amd_sdw_manager *amd_manager)126{127 u32 frame_size;128 129 frame_size = (amd_manager->rows_index << 3) | amd_manager->cols_index;130 writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE);131}132 133static void amd_sdw_wake_enable(struct amd_sdw_manager *amd_manager, bool enable)134{135 u32 wake_ctrl;136 137 wake_ctrl = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);138 if (enable)139 wake_ctrl |= AMD_SDW_WAKE_INTR_MASK;140 else141 wake_ctrl &= ~AMD_SDW_WAKE_INTR_MASK;142 143 writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);144}145 146static void amd_sdw_ctl_word_prep(u32 *lower_word, u32 *upper_word, struct sdw_msg *msg,147 int cmd_offset)148{149 u32 upper_data;150 u32 lower_data = 0;151 u16 addr;152 u8 upper_addr, lower_addr;153 u8 data = 0;154 155 addr = msg->addr + cmd_offset;156 upper_addr = (addr & 0xFF00) >> 8;157 lower_addr = addr & 0xFF;158 159 if (msg->flags == SDW_MSG_FLAG_WRITE)160 data = msg->buf[cmd_offset];161 162 upper_data = FIELD_PREP(AMD_SDW_MCP_CMD_DEV_ADDR, msg->dev_num);163 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_COMMAND, msg->flags + 2);164 upper_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_HIGH, upper_addr);165 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_ADDR_LOW, lower_addr);166 lower_data |= FIELD_PREP(AMD_SDW_MCP_CMD_REG_DATA, data);167 168 *upper_word = upper_data;169 *lower_word = lower_data;170}171 172static u64 amd_sdw_send_cmd_get_resp(struct amd_sdw_manager *amd_manager, u32 lower_data,173 u32 upper_data)174{175 u64 resp;176 u32 lower_resp, upper_resp;177 u32 sts;178 int ret;179 180 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,181 !(sts & AMD_SDW_IMM_CMD_BUSY), ACP_DELAY_US, AMD_SDW_TIMEOUT);182 if (ret) {183 dev_err(amd_manager->dev, "SDW%x previous cmd status clear failed\n",184 amd_manager->instance);185 return ret;186 }187 188 if (sts & AMD_SDW_IMM_RES_VALID) {189 dev_err(amd_manager->dev, "SDW%x manager is in bad state\n", amd_manager->instance);190 writel(0x00, amd_manager->mmio + ACP_SW_IMM_CMD_STS);191 }192 writel(upper_data, amd_manager->mmio + ACP_SW_IMM_CMD_UPPER_WORD);193 writel(lower_data, amd_manager->mmio + ACP_SW_IMM_CMD_LOWER_QWORD);194 195 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,196 (sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT);197 if (ret) {198 dev_err(amd_manager->dev, "SDW%x cmd response timeout occurred\n",199 amd_manager->instance);200 return ret;201 }202 upper_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_UPPER_WORD);203 lower_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_LOWER_QWORD);204 205 writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS);206 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,207 !(sts & AMD_SDW_IMM_RES_VALID), ACP_DELAY_US, AMD_SDW_TIMEOUT);208 if (ret) {209 dev_err(amd_manager->dev, "SDW%x cmd status retry failed\n",210 amd_manager->instance);211 return ret;212 }213 resp = upper_resp;214 resp = (resp << 32) | lower_resp;215 return resp;216}217 218static enum sdw_command_response219amd_program_scp_addr(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg)220{221 struct sdw_msg scp_msg = {0};222 u64 response_buf[2] = {0};223 u32 upper_data = 0, lower_data = 0;224 int index;225 226 scp_msg.dev_num = msg->dev_num;227 scp_msg.addr = SDW_SCP_ADDRPAGE1;228 scp_msg.buf = &msg->addr_page1;229 scp_msg.flags = SDW_MSG_FLAG_WRITE;230 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0);231 response_buf[0] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data);232 scp_msg.addr = SDW_SCP_ADDRPAGE2;233 scp_msg.buf = &msg->addr_page2;234 amd_sdw_ctl_word_prep(&lower_data, &upper_data, &scp_msg, 0);235 response_buf[1] = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data);236 237 for (index = 0; index < 2; index++) {238 if (response_buf[index] == -ETIMEDOUT) {239 dev_err_ratelimited(amd_manager->dev,240 "SCP_addrpage command timeout for Slave %d\n",241 msg->dev_num);242 return SDW_CMD_TIMEOUT;243 } else if (!(response_buf[index] & AMD_SDW_MCP_RESP_ACK)) {244 if (response_buf[index] & AMD_SDW_MCP_RESP_NACK) {245 dev_err_ratelimited(amd_manager->dev,246 "SCP_addrpage NACKed for Slave %d\n",247 msg->dev_num);248 return SDW_CMD_FAIL;249 }250 dev_dbg_ratelimited(amd_manager->dev, "SCP_addrpage ignored for Slave %d\n",251 msg->dev_num);252 return SDW_CMD_IGNORED;253 }254 }255 return SDW_CMD_OK;256}257 258static int amd_prep_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg)259{260 int ret;261 262 if (msg->page) {263 ret = amd_program_scp_addr(amd_manager, msg);264 if (ret) {265 msg->len = 0;266 return ret;267 }268 }269 switch (msg->flags) {270 case SDW_MSG_FLAG_READ:271 case SDW_MSG_FLAG_WRITE:272 break;273 default:274 dev_err(amd_manager->dev, "Invalid msg cmd: %d\n", msg->flags);275 return -EINVAL;276 }277 return 0;278}279 280static enum sdw_command_response amd_sdw_fill_msg_resp(struct amd_sdw_manager *amd_manager,281 struct sdw_msg *msg, u64 response,282 int offset)283{284 if (response & AMD_SDW_MCP_RESP_ACK) {285 if (msg->flags == SDW_MSG_FLAG_READ)286 msg->buf[offset] = FIELD_GET(AMD_SDW_MCP_RESP_RDATA, response);287 } else {288 if (response == -ETIMEDOUT) {289 dev_err_ratelimited(amd_manager->dev, "command timeout for Slave %d\n",290 msg->dev_num);291 return SDW_CMD_TIMEOUT;292 } else if (response & AMD_SDW_MCP_RESP_NACK) {293 dev_err_ratelimited(amd_manager->dev,294 "command response NACK received for Slave %d\n",295 msg->dev_num);296 return SDW_CMD_FAIL;297 }298 dev_err_ratelimited(amd_manager->dev, "command is ignored for Slave %d\n",299 msg->dev_num);300 return SDW_CMD_IGNORED;301 }302 return SDW_CMD_OK;303}304 305static unsigned int _amd_sdw_xfer_msg(struct amd_sdw_manager *amd_manager, struct sdw_msg *msg,306 int cmd_offset)307{308 u64 response;309 u32 upper_data = 0, lower_data = 0;310 311 amd_sdw_ctl_word_prep(&lower_data, &upper_data, msg, cmd_offset);312 response = amd_sdw_send_cmd_get_resp(amd_manager, lower_data, upper_data);313 return amd_sdw_fill_msg_resp(amd_manager, msg, response, cmd_offset);314}315 316static enum sdw_command_response amd_sdw_xfer_msg(struct sdw_bus *bus, struct sdw_msg *msg)317{318 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);319 int ret, i;320 321 ret = amd_prep_msg(amd_manager, msg);322 if (ret)323 return SDW_CMD_FAIL_OTHER;324 for (i = 0; i < msg->len; i++) {325 ret = _amd_sdw_xfer_msg(amd_manager, msg, i);326 if (ret)327 return ret;328 }329 return SDW_CMD_OK;330}331 332static void amd_sdw_fill_slave_status(struct amd_sdw_manager *amd_manager, u16 index, u32 status)333{334 switch (status) {335 case SDW_SLAVE_ATTACHED:336 case SDW_SLAVE_UNATTACHED:337 case SDW_SLAVE_ALERT:338 amd_manager->status[index] = status;339 break;340 default:341 amd_manager->status[index] = SDW_SLAVE_RESERVED;342 break;343 }344}345 346static void amd_sdw_process_ping_status(u64 response, struct amd_sdw_manager *amd_manager)347{348 u64 slave_stat;349 u32 val;350 u16 dev_index;351 352 /* slave status response */353 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response);354 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8;355 dev_dbg(amd_manager->dev, "slave_stat:0x%llx\n", slave_stat);356 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) {357 val = (slave_stat >> (dev_index * 2)) & AMD_SDW_MCP_SLAVE_STATUS_MASK;358 dev_dbg(amd_manager->dev, "val:0x%x\n", val);359 amd_sdw_fill_slave_status(amd_manager, dev_index, val);360 }361}362 363static void amd_sdw_read_and_process_ping_status(struct amd_sdw_manager *amd_manager)364{365 u64 response;366 367 mutex_lock(&amd_manager->bus.msg_lock);368 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0);369 mutex_unlock(&amd_manager->bus.msg_lock);370 amd_sdw_process_ping_status(response, amd_manager);371}372 373static u32 amd_sdw_read_ping_status(struct sdw_bus *bus)374{375 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);376 u64 response;377 u32 slave_stat;378 379 response = amd_sdw_send_cmd_get_resp(amd_manager, 0, 0);380 /* slave status from ping response */381 slave_stat = FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_0_3, response);382 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STAT_4_11, response) << 8;383 dev_dbg(amd_manager->dev, "slave_stat:0x%x\n", slave_stat);384 return slave_stat;385}386 387static int amd_sdw_compute_params(struct sdw_bus *bus)388{389 struct sdw_transport_data t_data = {0};390 struct sdw_master_runtime *m_rt;391 struct sdw_port_runtime *p_rt;392 struct sdw_bus_params *b_params = &bus->params;393 int port_bo, hstart, hstop, sample_int;394 unsigned int rate, bps;395 396 port_bo = 0;397 hstart = 1;398 hstop = bus->params.col - 1;399 t_data.hstop = hstop;400 t_data.hstart = hstart;401 402 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {403 rate = m_rt->stream->params.rate;404 bps = m_rt->stream->params.bps;405 sample_int = (bus->params.curr_dr_freq / rate);406 list_for_each_entry(p_rt, &m_rt->port_list, port_node) {407 port_bo = (p_rt->num * 64) + 1;408 dev_dbg(bus->dev, "p_rt->num=%d hstart=%d hstop=%d port_bo=%d\n",409 p_rt->num, hstart, hstop, port_bo);410 sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,411 false, SDW_BLK_GRP_CNT_1, sample_int,412 port_bo, port_bo >> 8, hstart, hstop,413 SDW_BLK_PKG_PER_PORT, 0x0);414 415 sdw_fill_port_params(&p_rt->port_params,416 p_rt->num, bps,417 SDW_PORT_FLOW_MODE_ISOCH,418 b_params->m_data_mode);419 t_data.hstart = hstart;420 t_data.hstop = hstop;421 t_data.block_offset = port_bo;422 t_data.sub_block_offset = 0;423 }424 sdw_compute_slave_ports(m_rt, &t_data);425 }426 return 0;427}428 429static int amd_sdw_port_params(struct sdw_bus *bus, struct sdw_port_params *p_params,430 unsigned int bank)431{432 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);433 u32 frame_fmt_reg, dpn_frame_fmt;434 435 dev_dbg(amd_manager->dev, "p_params->num:0x%x\n", p_params->num);436 switch (amd_manager->instance) {437 case ACP_SDW0:438 frame_fmt_reg = sdw0_manager_dp_reg[p_params->num].frame_fmt_reg;439 break;440 case ACP_SDW1:441 frame_fmt_reg = sdw1_manager_dp_reg[p_params->num].frame_fmt_reg;442 break;443 default:444 return -EINVAL;445 }446 447 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg);448 u32p_replace_bits(&dpn_frame_fmt, p_params->flow_mode, AMD_DPN_FRAME_FMT_PFM);449 u32p_replace_bits(&dpn_frame_fmt, p_params->data_mode, AMD_DPN_FRAME_FMT_PDM);450 u32p_replace_bits(&dpn_frame_fmt, p_params->bps - 1, AMD_DPN_FRAME_FMT_WORD_LEN);451 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg);452 return 0;453}454 455static int amd_sdw_transport_params(struct sdw_bus *bus,456 struct sdw_transport_params *params,457 enum sdw_reg_bank bank)458{459 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);460 u32 dpn_frame_fmt;461 u32 dpn_sampleinterval;462 u32 dpn_hctrl;463 u32 dpn_offsetctrl;464 u32 dpn_lanectrl;465 u32 frame_fmt_reg, sample_int_reg, hctrl_dp0_reg;466 u32 offset_reg, lane_ctrl_ch_en_reg;467 468 switch (amd_manager->instance) {469 case ACP_SDW0:470 frame_fmt_reg = sdw0_manager_dp_reg[params->port_num].frame_fmt_reg;471 sample_int_reg = sdw0_manager_dp_reg[params->port_num].sample_int_reg;472 hctrl_dp0_reg = sdw0_manager_dp_reg[params->port_num].hctrl_dp0_reg;473 offset_reg = sdw0_manager_dp_reg[params->port_num].offset_reg;474 lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;475 break;476 case ACP_SDW1:477 frame_fmt_reg = sdw1_manager_dp_reg[params->port_num].frame_fmt_reg;478 sample_int_reg = sdw1_manager_dp_reg[params->port_num].sample_int_reg;479 hctrl_dp0_reg = sdw1_manager_dp_reg[params->port_num].hctrl_dp0_reg;480 offset_reg = sdw1_manager_dp_reg[params->port_num].offset_reg;481 lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;482 break;483 default:484 return -EINVAL;485 }486 writel(AMD_SDW_SSP_COUNTER_VAL, amd_manager->mmio + ACP_SW_SSP_COUNTER);487 488 dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg);489 u32p_replace_bits(&dpn_frame_fmt, params->blk_pkg_mode, AMD_DPN_FRAME_FMT_BLK_PKG_MODE);490 u32p_replace_bits(&dpn_frame_fmt, params->blk_grp_ctrl, AMD_DPN_FRAME_FMT_BLK_GRP_CTRL);491 u32p_replace_bits(&dpn_frame_fmt, SDW_STREAM_PCM, AMD_DPN_FRAME_FMT_PCM_OR_PDM);492 writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg);493 494 dpn_sampleinterval = params->sample_interval - 1;495 writel(dpn_sampleinterval, amd_manager->mmio + sample_int_reg);496 497 dpn_hctrl = FIELD_PREP(AMD_DPN_HCTRL_HSTOP, params->hstop);498 dpn_hctrl |= FIELD_PREP(AMD_DPN_HCTRL_HSTART, params->hstart);499 writel(dpn_hctrl, amd_manager->mmio + hctrl_dp0_reg);500 501 dpn_offsetctrl = FIELD_PREP(AMD_DPN_OFFSET_CTRL_1, params->offset1);502 dpn_offsetctrl |= FIELD_PREP(AMD_DPN_OFFSET_CTRL_2, params->offset2);503 writel(dpn_offsetctrl, amd_manager->mmio + offset_reg);504 505 /*506 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask507 * parameters.508 */509 dpn_lanectrl = readl(amd_manager->mmio + lane_ctrl_ch_en_reg);510 u32p_replace_bits(&dpn_lanectrl, params->lane_ctrl, AMD_DPN_CH_EN_LCTRL);511 writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg);512 return 0;513}514 515static int amd_sdw_port_enable(struct sdw_bus *bus,516 struct sdw_enable_ch *enable_ch,517 unsigned int bank)518{519 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);520 u32 dpn_ch_enable;521 u32 lane_ctrl_ch_en_reg;522 523 switch (amd_manager->instance) {524 case ACP_SDW0:525 lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;526 break;527 case ACP_SDW1:528 lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[enable_ch->port_num].lane_ctrl_ch_en_reg;529 break;530 default:531 return -EINVAL;532 }533 534 /*535 * lane_ctrl_ch_en_reg will be used to program lane_ctrl and ch_mask536 * parameters.537 */538 dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg);539 u32p_replace_bits(&dpn_ch_enable, enable_ch->ch_mask, AMD_DPN_CH_EN_CHMASK);540 if (enable_ch->enable)541 writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg);542 else543 writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg);544 return 0;545}546 547static int sdw_master_read_amd_prop(struct sdw_bus *bus)548{549 struct amd_sdw_manager *amd_manager = to_amd_sdw(bus);550 struct fwnode_handle *link;551 struct sdw_master_prop *prop;552 u32 quirk_mask = 0;553 u32 wake_en_mask = 0;554 u32 power_mode_mask = 0;555 char name[32];556 557 prop = &bus->prop;558 /* Find manager handle */559 snprintf(name, sizeof(name), "mipi-sdw-link-%d-subproperties", bus->link_id);560 link = device_get_named_child_node(bus->dev, name);561 if (!link) {562 dev_err(bus->dev, "Manager node %s not found\n", name);563 return -EIO;564 }565 fwnode_property_read_u32(link, "amd-sdw-enable", &quirk_mask);566 if (!(quirk_mask & AMD_SDW_QUIRK_MASK_BUS_ENABLE))567 prop->hw_disabled = true;568 prop->quirks = SDW_MASTER_QUIRKS_CLEAR_INITIAL_CLASH |569 SDW_MASTER_QUIRKS_CLEAR_INITIAL_PARITY;570 571 fwnode_property_read_u32(link, "amd-sdw-wakeup-enable", &wake_en_mask);572 amd_manager->wake_en_mask = wake_en_mask;573 fwnode_property_read_u32(link, "amd-sdw-power-mode", &power_mode_mask);574 amd_manager->power_mode_mask = power_mode_mask;575 576 fwnode_handle_put(link);577 578 return 0;579}580 581static int amd_prop_read(struct sdw_bus *bus)582{583 sdw_master_read_prop(bus);584 sdw_master_read_amd_prop(bus);585 return 0;586}587 588static const struct sdw_master_port_ops amd_sdw_port_ops = {589 .dpn_set_port_params = amd_sdw_port_params,590 .dpn_set_port_transport_params = amd_sdw_transport_params,591 .dpn_port_enable_ch = amd_sdw_port_enable,592};593 594static const struct sdw_master_ops amd_sdw_ops = {595 .read_prop = amd_prop_read,596 .xfer_msg = amd_sdw_xfer_msg,597 .read_ping_status = amd_sdw_read_ping_status,598};599 600static int amd_sdw_hw_params(struct snd_pcm_substream *substream,601 struct snd_pcm_hw_params *params,602 struct snd_soc_dai *dai)603{604 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);605 struct sdw_amd_dai_runtime *dai_runtime;606 struct sdw_stream_config sconfig;607 int ch, dir;608 int ret;609 610 dai_runtime = amd_manager->dai_runtime_array[dai->id];611 if (!dai_runtime)612 return -EIO;613 614 ch = params_channels(params);615 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)616 dir = SDW_DATA_DIR_RX;617 else618 dir = SDW_DATA_DIR_TX;619 dev_dbg(amd_manager->dev, "dir:%d dai->id:0x%x\n", dir, dai->id);620 621 sconfig.direction = dir;622 sconfig.ch_count = ch;623 sconfig.frame_rate = params_rate(params);624 sconfig.type = dai_runtime->stream_type;625 626 sconfig.bps = snd_pcm_format_width(params_format(params));627 628 /* Port configuration */629 struct sdw_port_config *pconfig __free(kfree) = kzalloc(sizeof(*pconfig),630 GFP_KERNEL);631 if (!pconfig)632 return -ENOMEM;633 634 pconfig->num = dai->id;635 pconfig->ch_mask = (1 << ch) - 1;636 ret = sdw_stream_add_master(&amd_manager->bus, &sconfig,637 pconfig, 1, dai_runtime->stream);638 if (ret)639 dev_err(amd_manager->dev, "add manager to stream failed:%d\n", ret);640 641 return ret;642}643 644static int amd_sdw_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)645{646 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);647 struct sdw_amd_dai_runtime *dai_runtime;648 int ret;649 650 dai_runtime = amd_manager->dai_runtime_array[dai->id];651 if (!dai_runtime)652 return -EIO;653 654 ret = sdw_stream_remove_master(&amd_manager->bus, dai_runtime->stream);655 if (ret < 0)656 dev_err(dai->dev, "remove manager from stream %s failed: %d\n",657 dai_runtime->stream->name, ret);658 return ret;659}660 661static int amd_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction)662{663 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);664 struct sdw_amd_dai_runtime *dai_runtime;665 666 dai_runtime = amd_manager->dai_runtime_array[dai->id];667 if (stream) {668 /* first paranoia check */669 if (dai_runtime) {670 dev_err(dai->dev, "dai_runtime already allocated for dai %s\n", dai->name);671 return -EINVAL;672 }673 674 /* allocate and set dai_runtime info */675 dai_runtime = kzalloc(sizeof(*dai_runtime), GFP_KERNEL);676 if (!dai_runtime)677 return -ENOMEM;678 679 dai_runtime->stream_type = SDW_STREAM_PCM;680 dai_runtime->bus = &amd_manager->bus;681 dai_runtime->stream = stream;682 amd_manager->dai_runtime_array[dai->id] = dai_runtime;683 } else {684 /* second paranoia check */685 if (!dai_runtime) {686 dev_err(dai->dev, "dai_runtime not allocated for dai %s\n", dai->name);687 return -EINVAL;688 }689 690 /* for NULL stream we release allocated dai_runtime */691 kfree(dai_runtime);692 amd_manager->dai_runtime_array[dai->id] = NULL;693 }694 return 0;695}696 697static int amd_pcm_set_sdw_stream(struct snd_soc_dai *dai, void *stream, int direction)698{699 return amd_set_sdw_stream(dai, stream, direction);700}701 702static void *amd_get_sdw_stream(struct snd_soc_dai *dai, int direction)703{704 struct amd_sdw_manager *amd_manager = snd_soc_dai_get_drvdata(dai);705 struct sdw_amd_dai_runtime *dai_runtime;706 707 dai_runtime = amd_manager->dai_runtime_array[dai->id];708 if (!dai_runtime)709 return ERR_PTR(-EINVAL);710 711 return dai_runtime->stream;712}713 714static const struct snd_soc_dai_ops amd_sdw_dai_ops = {715 .hw_params = amd_sdw_hw_params,716 .hw_free = amd_sdw_hw_free,717 .set_stream = amd_pcm_set_sdw_stream,718 .get_stream = amd_get_sdw_stream,719};720 721static const struct snd_soc_component_driver amd_sdw_dai_component = {722 .name = "soundwire",723};724 725static int amd_sdw_register_dais(struct amd_sdw_manager *amd_manager)726{727 struct sdw_amd_dai_runtime **dai_runtime_array;728 struct snd_soc_dai_driver *dais;729 struct snd_soc_pcm_stream *stream;730 struct device *dev;731 int i, num_dais;732 733 dev = amd_manager->dev;734 num_dais = amd_manager->num_dout_ports + amd_manager->num_din_ports;735 dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);736 if (!dais)737 return -ENOMEM;738 739 dai_runtime_array = devm_kcalloc(dev, num_dais,740 sizeof(struct sdw_amd_dai_runtime *),741 GFP_KERNEL);742 if (!dai_runtime_array)743 return -ENOMEM;744 amd_manager->dai_runtime_array = dai_runtime_array;745 for (i = 0; i < num_dais; i++) {746 dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW%d Pin%d", amd_manager->instance,747 i);748 if (!dais[i].name)749 return -ENOMEM;750 if (i < amd_manager->num_dout_ports)751 stream = &dais[i].playback;752 else753 stream = &dais[i].capture;754 755 stream->channels_min = 2;756 stream->channels_max = 2;757 stream->rates = SNDRV_PCM_RATE_48000;758 stream->formats = SNDRV_PCM_FMTBIT_S16_LE;759 760 dais[i].ops = &amd_sdw_dai_ops;761 dais[i].id = i;762 }763 764 return devm_snd_soc_register_component(dev, &amd_sdw_dai_component,765 dais, num_dais);766}767 768static void amd_sdw_update_slave_status_work(struct work_struct *work)769{770 struct amd_sdw_manager *amd_manager =771 container_of(work, struct amd_sdw_manager, amd_sdw_work);772 int retry_count = 0;773 774 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) {775 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);776 writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);777 }778 779update_status:780 sdw_handle_slave_status(&amd_manager->bus, amd_manager->status);781 /*782 * During the peripheral enumeration sequence, the SoundWire manager interrupts783 * are masked. Once the device number programming is done for all peripherals,784 * interrupts will be unmasked. Read the peripheral device status from ping command785 * and process the response. This sequence will ensure all peripheral devices enumerated786 * and initialized properly.787 */788 if (amd_manager->status[0] == SDW_SLAVE_ATTACHED) {789 if (retry_count++ < SDW_MAX_DEVICES) {790 writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio +791 ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);792 writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio +793 ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);794 amd_sdw_read_and_process_ping_status(amd_manager);795 goto update_status;796 } else {797 dev_err_ratelimited(amd_manager->dev,798 "Device0 detected after %d iterations\n",799 retry_count);800 }801 }802}803 804static void amd_sdw_update_slave_status(u32 status_change_0to7, u32 status_change_8to11,805 struct amd_sdw_manager *amd_manager)806{807 u64 slave_stat;808 u32 val;809 int dev_index;810 811 if (status_change_0to7 == AMD_SDW_SLAVE_0_ATTACHED)812 memset(amd_manager->status, 0, sizeof(amd_manager->status));813 slave_stat = status_change_0to7;814 slave_stat |= FIELD_GET(AMD_SDW_MCP_SLAVE_STATUS_8TO_11, status_change_8to11) << 32;815 dev_dbg(amd_manager->dev, "status_change_0to7:0x%x status_change_8to11:0x%x\n",816 status_change_0to7, status_change_8to11);817 if (slave_stat) {818 for (dev_index = 0; dev_index <= SDW_MAX_DEVICES; ++dev_index) {819 if (slave_stat & AMD_SDW_MCP_SLAVE_STATUS_VALID_MASK(dev_index)) {820 val = (slave_stat >> AMD_SDW_MCP_SLAVE_STAT_SHIFT_MASK(dev_index)) &821 AMD_SDW_MCP_SLAVE_STATUS_MASK;822 amd_sdw_fill_slave_status(amd_manager, dev_index, val);823 }824 }825 }826}827 828static void amd_sdw_process_wake_event(struct amd_sdw_manager *amd_manager)829{830 pm_request_resume(amd_manager->dev);831 writel(0x00, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));832 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);833}834 835static void amd_sdw_irq_thread(struct work_struct *work)836{837 struct amd_sdw_manager *amd_manager =838 container_of(work, struct amd_sdw_manager, amd_sdw_irq_thread);839 u32 status_change_8to11;840 u32 status_change_0to7;841 842 status_change_8to11 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);843 status_change_0to7 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7);844 dev_dbg(amd_manager->dev, "[SDW%d] SDW INT: 0to7=0x%x, 8to11=0x%x\n",845 amd_manager->instance, status_change_0to7, status_change_8to11);846 if (status_change_8to11 & AMD_SDW_WAKE_STAT_MASK)847 return amd_sdw_process_wake_event(amd_manager);848 849 if (status_change_8to11 & AMD_SDW_PREQ_INTR_STAT) {850 amd_sdw_read_and_process_ping_status(amd_manager);851 } else {852 /* Check for the updated status on peripheral device */853 amd_sdw_update_slave_status(status_change_0to7, status_change_8to11, amd_manager);854 }855 if (status_change_8to11 || status_change_0to7)856 schedule_work(&amd_manager->amd_sdw_work);857 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);858 writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7);859}860 861int amd_sdw_manager_start(struct amd_sdw_manager *amd_manager)862{863 struct sdw_master_prop *prop;864 int ret;865 866 prop = &amd_manager->bus.prop;867 if (!prop->hw_disabled) {868 ret = amd_init_sdw_manager(amd_manager);869 if (ret)870 return ret;871 amd_enable_sdw_interrupts(amd_manager);872 ret = amd_enable_sdw_manager(amd_manager);873 if (ret)874 return ret;875 amd_sdw_set_frameshape(amd_manager);876 }877 /* Enable runtime PM */878 pm_runtime_set_autosuspend_delay(amd_manager->dev, AMD_SDW_MASTER_SUSPEND_DELAY_MS);879 pm_runtime_use_autosuspend(amd_manager->dev);880 pm_runtime_mark_last_busy(amd_manager->dev);881 pm_runtime_set_active(amd_manager->dev);882 pm_runtime_enable(amd_manager->dev);883 return 0;884}885 886static int amd_sdw_manager_probe(struct platform_device *pdev)887{888 const struct acp_sdw_pdata *pdata = pdev->dev.platform_data;889 struct resource *res;890 struct device *dev = &pdev->dev;891 struct sdw_master_prop *prop;892 struct sdw_bus_params *params;893 struct amd_sdw_manager *amd_manager;894 int ret;895 896 amd_manager = devm_kzalloc(dev, sizeof(struct amd_sdw_manager), GFP_KERNEL);897 if (!amd_manager)898 return -ENOMEM;899 900 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);901 if (!res)902 return -ENOMEM;903 904 amd_manager->acp_mmio = devm_ioremap(dev, res->start, resource_size(res));905 if (!amd_manager->acp_mmio) {906 dev_err(dev, "mmio not found\n");907 return -ENOMEM;908 }909 amd_manager->instance = pdata->instance;910 amd_manager->mmio = amd_manager->acp_mmio +911 (amd_manager->instance * SDW_MANAGER_REG_OFFSET);912 amd_manager->acp_sdw_lock = pdata->acp_sdw_lock;913 amd_manager->cols_index = sdw_find_col_index(AMD_SDW_DEFAULT_COLUMNS);914 amd_manager->rows_index = sdw_find_row_index(AMD_SDW_DEFAULT_ROWS);915 amd_manager->dev = dev;916 amd_manager->bus.ops = &amd_sdw_ops;917 amd_manager->bus.port_ops = &amd_sdw_port_ops;918 amd_manager->bus.compute_params = &amd_sdw_compute_params;919 amd_manager->bus.clk_stop_timeout = 200;920 amd_manager->bus.link_id = amd_manager->instance;921 922 /*923 * Due to BIOS compatibility, the two links are exposed within924 * the scope of a single controller. If this changes, the925 * controller_id will have to be updated with drv_data926 * information.927 */928 amd_manager->bus.controller_id = 0;929 930 switch (amd_manager->instance) {931 case ACP_SDW0:932 amd_manager->num_dout_ports = AMD_SDW0_MAX_TX_PORTS;933 amd_manager->num_din_ports = AMD_SDW0_MAX_RX_PORTS;934 break;935 case ACP_SDW1:936 amd_manager->num_dout_ports = AMD_SDW1_MAX_TX_PORTS;937 amd_manager->num_din_ports = AMD_SDW1_MAX_RX_PORTS;938 break;939 default:940 return -EINVAL;941 }942 943 params = &amd_manager->bus.params;944 945 params->col = AMD_SDW_DEFAULT_COLUMNS;946 params->row = AMD_SDW_DEFAULT_ROWS;947 prop = &amd_manager->bus.prop;948 prop->clk_freq = &amd_sdw_freq_tbl[0];949 prop->mclk_freq = AMD_SDW_BUS_BASE_FREQ;950 prop->max_clk_freq = AMD_SDW_DEFAULT_CLK_FREQ;951 952 ret = sdw_bus_master_add(&amd_manager->bus, dev, dev->fwnode);953 if (ret) {954 dev_err(dev, "Failed to register SoundWire manager(%d)\n", ret);955 return ret;956 }957 ret = amd_sdw_register_dais(amd_manager);958 if (ret) {959 dev_err(dev, "CPU DAI registration failed\n");960 sdw_bus_master_delete(&amd_manager->bus);961 return ret;962 }963 dev_set_drvdata(dev, amd_manager);964 INIT_WORK(&amd_manager->amd_sdw_irq_thread, amd_sdw_irq_thread);965 INIT_WORK(&amd_manager->amd_sdw_work, amd_sdw_update_slave_status_work);966 return 0;967}968 969static void amd_sdw_manager_remove(struct platform_device *pdev)970{971 struct amd_sdw_manager *amd_manager = dev_get_drvdata(&pdev->dev);972 int ret;973 974 pm_runtime_disable(&pdev->dev);975 amd_disable_sdw_interrupts(amd_manager);976 sdw_bus_master_delete(&amd_manager->bus);977 ret = amd_disable_sdw_manager(amd_manager);978 if (ret)979 dev_err(&pdev->dev, "Failed to disable device (%pe)\n", ERR_PTR(ret));980}981 982static int amd_sdw_clock_stop(struct amd_sdw_manager *amd_manager)983{984 u32 val;985 int ret;986 987 ret = sdw_bus_prep_clk_stop(&amd_manager->bus);988 if (ret < 0 && ret != -ENODATA) {989 dev_err(amd_manager->dev, "prepare clock stop failed %d", ret);990 return 0;991 }992 ret = sdw_bus_clk_stop(&amd_manager->bus);993 if (ret < 0 && ret != -ENODATA) {994 dev_err(amd_manager->dev, "bus clock stop failed %d", ret);995 return 0;996 }997 998 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,999 (val & AMD_SDW_CLK_STOP_DONE), ACP_DELAY_US, AMD_SDW_TIMEOUT);1000 if (ret) {1001 dev_err(amd_manager->dev, "SDW%x clock stop failed\n", amd_manager->instance);1002 return 0;1003 }1004 1005 amd_manager->clk_stopped = true;1006 if (amd_manager->wake_en_mask)1007 writel(0x01, amd_manager->acp_mmio + ACP_SW_WAKE_EN(amd_manager->instance));1008 1009 dev_dbg(amd_manager->dev, "SDW%x clock stop successful\n", amd_manager->instance);1010 return 0;1011}1012 1013static int amd_sdw_clock_stop_exit(struct amd_sdw_manager *amd_manager)1014{1015 int ret;1016 u32 val;1017 1018 if (amd_manager->clk_stopped) {1019 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);1020 val |= AMD_SDW_CLK_RESUME_REQ;1021 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);1022 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,1023 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US,1024 AMD_SDW_TIMEOUT);1025 if (val & AMD_SDW_CLK_RESUME_DONE) {1026 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);1027 ret = sdw_bus_exit_clk_stop(&amd_manager->bus);1028 if (ret < 0)1029 dev_err(amd_manager->dev, "bus failed to exit clock stop %d\n",1030 ret);1031 amd_manager->clk_stopped = false;1032 }1033 }1034 if (amd_manager->clk_stopped) {1035 dev_err(amd_manager->dev, "SDW%x clock stop exit failed\n", amd_manager->instance);1036 return 0;1037 }1038 dev_dbg(amd_manager->dev, "SDW%x clock stop exit successful\n", amd_manager->instance);1039 return 0;1040}1041 1042static int amd_resume_child_device(struct device *dev, void *data)1043{1044 struct sdw_slave *slave = dev_to_sdw_dev(dev);1045 int ret;1046 1047 if (!slave->probed) {1048 dev_dbg(dev, "skipping device, no probed driver\n");1049 return 0;1050 }1051 if (!slave->dev_num_sticky) {1052 dev_dbg(dev, "skipping device, never detected on bus\n");1053 return 0;1054 }1055 ret = pm_request_resume(dev);1056 if (ret < 0) {1057 dev_err(dev, "pm_request_resume failed: %d\n", ret);1058 return ret;1059 }1060 return 0;1061}1062 1063static int __maybe_unused amd_pm_prepare(struct device *dev)1064{1065 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);1066 struct sdw_bus *bus = &amd_manager->bus;1067 int ret;1068 1069 if (bus->prop.hw_disabled) {1070 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n",1071 bus->link_id);1072 return 0;1073 }1074 /*1075 * When multiple peripheral devices connected over the same link, if SoundWire manager1076 * device is not in runtime suspend state, observed that device alerts are missing1077 * without pm_prepare on AMD platforms in clockstop mode0.1078 */1079 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {1080 ret = pm_request_resume(dev);1081 if (ret < 0) {1082 dev_err(bus->dev, "pm_request_resume failed: %d\n", ret);1083 return 0;1084 }1085 }1086 /* To force peripheral devices to system level suspend state, resume the devices1087 * from runtime suspend state first. Without that unable to dispatch the alert1088 * status to peripheral driver during system level resume as they are in runtime1089 * suspend state.1090 */1091 ret = device_for_each_child(bus->dev, NULL, amd_resume_child_device);1092 if (ret < 0)1093 dev_err(dev, "amd_resume_child_device failed: %d\n", ret);1094 return 0;1095}1096 1097static int __maybe_unused amd_suspend(struct device *dev)1098{1099 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);1100 struct sdw_bus *bus = &amd_manager->bus;1101 int ret;1102 1103 if (bus->prop.hw_disabled) {1104 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n",1105 bus->link_id);1106 return 0;1107 }1108 1109 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {1110 amd_sdw_wake_enable(amd_manager, false);1111 return amd_sdw_clock_stop(amd_manager);1112 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {1113 /*1114 * As per hardware programming sequence on AMD platforms,1115 * clock stop should be invoked first before powering-off1116 */1117 ret = amd_sdw_clock_stop(amd_manager);1118 if (ret)1119 return ret;1120 return amd_deinit_sdw_manager(amd_manager);1121 }1122 return 0;1123}1124 1125static int __maybe_unused amd_suspend_runtime(struct device *dev)1126{1127 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);1128 struct sdw_bus *bus = &amd_manager->bus;1129 int ret;1130 1131 if (bus->prop.hw_disabled) {1132 dev_dbg(bus->dev, "SoundWire manager %d is disabled,\n",1133 bus->link_id);1134 return 0;1135 }1136 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {1137 amd_sdw_wake_enable(amd_manager, true);1138 return amd_sdw_clock_stop(amd_manager);1139 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {1140 ret = amd_sdw_clock_stop(amd_manager);1141 if (ret)1142 return ret;1143 return amd_deinit_sdw_manager(amd_manager);1144 }1145 return 0;1146}1147 1148static int __maybe_unused amd_resume_runtime(struct device *dev)1149{1150 struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);1151 struct sdw_bus *bus = &amd_manager->bus;1152 int ret;1153 u32 val;1154 1155 if (bus->prop.hw_disabled) {1156 dev_dbg(bus->dev, "SoundWire manager %d is disabled, ignoring\n",1157 bus->link_id);1158 return 0;1159 }1160 1161 if (amd_manager->power_mode_mask & AMD_SDW_CLK_STOP_MODE) {1162 return amd_sdw_clock_stop_exit(amd_manager);1163 } else if (amd_manager->power_mode_mask & AMD_SDW_POWER_OFF_MODE) {1164 val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);1165 if (val) {1166 val |= AMD_SDW_CLK_RESUME_REQ;1167 writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);1168 ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,1169 (val & AMD_SDW_CLK_RESUME_DONE), ACP_DELAY_US,1170 AMD_SDW_TIMEOUT);1171 if (val & AMD_SDW_CLK_RESUME_DONE) {1172 writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);1173 amd_manager->clk_stopped = false;1174 }1175 }1176 sdw_clear_slave_status(bus, SDW_UNATTACH_REQUEST_MASTER_RESET);1177 amd_init_sdw_manager(amd_manager);1178 amd_enable_sdw_interrupts(amd_manager);1179 ret = amd_enable_sdw_manager(amd_manager);1180 if (ret)1181 return ret;1182 amd_sdw_set_frameshape(amd_manager);1183 }1184 return 0;1185}1186 1187static const struct dev_pm_ops amd_pm = {1188 .prepare = amd_pm_prepare,1189 SET_SYSTEM_SLEEP_PM_OPS(amd_suspend, amd_resume_runtime)1190 SET_RUNTIME_PM_OPS(amd_suspend_runtime, amd_resume_runtime, NULL)1191};1192 1193static struct platform_driver amd_sdw_driver = {1194 .probe = &amd_sdw_manager_probe,1195 .remove_new = &amd_sdw_manager_remove,1196 .driver = {1197 .name = "amd_sdw_manager",1198 .pm = &amd_pm,1199 }1200};1201module_platform_driver(amd_sdw_driver);1202 1203MODULE_AUTHOR("Vijendar.Mukunda@amd.com");1204MODULE_DESCRIPTION("AMD SoundWire driver");1205MODULE_LICENSE("Dual BSD/GPL");1206MODULE_ALIAS("platform:" DRV_NAME);1207