252 lines · c
1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */2/*3 * Copyright (C) 2023-24 Advanced Micro Devices, Inc. All rights reserved.4 */5 6#ifndef __AMD_MANAGER_H7#define __AMD_MANAGER_H8 9#include <linux/soundwire/sdw_amd.h>10 11#define SDW_MANAGER_REG_OFFSET 0xc0012#define AMD_SDW_DEFAULT_ROWS 5013#define AMD_SDW_DEFAULT_COLUMNS 1014#define ACP_PAD_PULLDOWN_CTRL 0x000144815#define ACP_SW_PAD_KEEPER_EN 0x000145416#define ACP_SW0_WAKE_EN 0x000145817#define ACP_EXTERNAL_INTR_CNTL0 0x0001a0418#define ACP_EXTERNAL_INTR_STAT0 0x0001a0c19#define ACP_EXTERNAL_INTR_CNTL(i) (ACP_EXTERNAL_INTR_CNTL0 + ((i) * 4))20#define ACP_EXTERNAL_INTR_STAT(i) (ACP_EXTERNAL_INTR_STAT0 + ((i) * 4))21#define ACP_SW_WAKE_EN(i) (ACP_SW0_WAKE_EN + ((i) * 8))22 23#define ACP_SW_EN 0x000300024#define ACP_SW_EN_STATUS 0x000300425#define ACP_SW_FRAMESIZE 0x000300826#define ACP_SW_SSP_COUNTER 0x000300c27#define ACP_SW_AUDIO0_TX_EN 0x000301028#define ACP_SW_AUDIO0_TX_EN_STATUS 0x000301429#define ACP_SW_AUDIO0_TX_FRAME_FORMAT 0x000301830#define ACP_SW_AUDIO0_TX_SAMPLEINTERVAL 0x000301c31#define ACP_SW_AUDIO0_TX_HCTRL_DP0 0x000302032#define ACP_SW_AUDIO0_TX_HCTRL_DP1 0x000302433#define ACP_SW_AUDIO0_TX_HCTRL_DP2 0x000302834#define ACP_SW_AUDIO0_TX_HCTRL_DP3 0x000302c35#define ACP_SW_AUDIO0_TX_OFFSET_DP0 0x000303036#define ACP_SW_AUDIO0_TX_OFFSET_DP1 0x000303437#define ACP_SW_AUDIO0_TX_OFFSET_DP2 0x000303838#define ACP_SW_AUDIO0_TX_OFFSET_DP3 0x000303c39#define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP0 0x000304040#define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP1 0x000304441#define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP2 0x000304842#define ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP3 0x000304c43#define ACP_SW_AUDIO1_TX_EN 0x000305044#define ACP_SW_AUDIO1_TX_EN_STATUS 0x000305445#define ACP_SW_AUDIO1_TX_FRAME_FORMAT 0x000305846#define ACP_SW_AUDIO1_TX_SAMPLEINTERVAL 0x000305c47#define ACP_SW_AUDIO1_TX_HCTRL 0x000306048#define ACP_SW_AUDIO1_TX_OFFSET 0x000306449#define ACP_SW_AUDIO1_TX_CHANNEL_ENABLE_DP0 0x000306850#define ACP_SW_AUDIO2_TX_EN 0x000306c51#define ACP_SW_AUDIO2_TX_EN_STATUS 0x000307052#define ACP_SW_AUDIO2_TX_FRAME_FORMAT 0x000307453#define ACP_SW_AUDIO2_TX_SAMPLEINTERVAL 0x000307854#define ACP_SW_AUDIO2_TX_HCTRL 0x000307c55#define ACP_SW_AUDIO2_TX_OFFSET 0x000308056#define ACP_SW_AUDIO2_TX_CHANNEL_ENABLE_DP0 0x000308457#define ACP_SW_AUDIO0_RX_EN 0x000308858#define ACP_SW_AUDIO0_RX_EN_STATUS 0x000308c59#define ACP_SW_AUDIO0_RX_FRAME_FORMAT 0x000309060#define ACP_SW_AUDIO0_RX_SAMPLEINTERVAL 0x000309461#define ACP_SW_AUDIO0_RX_HCTRL_DP0 0x000309862#define ACP_SW_AUDIO0_RX_HCTRL_DP1 0x000309c63#define ACP_SW_AUDIO0_RX_HCTRL_DP2 0x000310064#define ACP_SW_AUDIO0_RX_HCTRL_DP3 0x000310465#define ACP_SW_AUDIO0_RX_OFFSET_DP0 0x000310866#define ACP_SW_AUDIO0_RX_OFFSET_DP1 0x000310c67#define ACP_SW_AUDIO0_RX_OFFSET_DP2 0x000311068#define ACP_SW_AUDIO0_RX_OFFSET_DP3 0x000311469#define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP0 0x000311870#define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP1 0x000311c71#define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP2 0x000312072#define ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP3 0x000312473#define ACP_SW_AUDIO1_RX_EN 0x000312874#define ACP_SW_AUDIO1_RX_EN_STATUS 0x000312c75#define ACP_SW_AUDIO1_RX_FRAME_FORMAT 0x000313076#define ACP_SW_AUDIO1_RX_SAMPLEINTERVAL 0x000313477#define ACP_SW_AUDIO1_RX_HCTRL 0x000313878#define ACP_SW_AUDIO1_RX_OFFSET 0x000313c79#define ACP_SW_AUDIO1_RX_CHANNEL_ENABLE_DP0 0x000314080#define ACP_SW_AUDIO2_RX_EN 0x000314481#define ACP_SW_AUDIO2_RX_EN_STATUS 0x000314882#define ACP_SW_AUDIO2_RX_FRAME_FORMAT 0x000314c83#define ACP_SW_AUDIO2_RX_SAMPLEINTERVAL 0x000315084#define ACP_SW_AUDIO2_RX_HCTRL 0x000315485#define ACP_SW_AUDIO2_RX_OFFSET 0x000315886#define ACP_SW_AUDIO2_RX_CHANNEL_ENABLE_DP0 0x000315c87#define ACP_SW_BPT_PORT_EN 0x000316088#define ACP_SW_BPT_PORT_EN_STATUS 0x000316489#define ACP_SW_BPT_PORT_FRAME_FORMAT 0x000316890#define ACP_SW_BPT_PORT_SAMPLEINTERVAL 0x000316c91#define ACP_SW_BPT_PORT_HCTRL 0x000317092#define ACP_SW_BPT_PORT_OFFSET 0x000317493#define ACP_SW_BPT_PORT_CHANNEL_ENABLE 0x000317894#define ACP_SW_BPT_PORT_FIRST_BYTE_ADDR 0x000317c95#define ACP_SW_CLK_RESUME_CTRL 0x000318096#define ACP_SW_CLK_RESUME_DELAY_CNTR 0x000318497#define ACP_SW_BUS_RESET_CTRL 0x000318898#define ACP_SW_PRBS_ERR_STATUS 0x000318c99#define ACP_SW_IMM_CMD_UPPER_WORD 0x0003230100#define ACP_SW_IMM_CMD_LOWER_QWORD 0x0003234101#define ACP_SW_IMM_RESP_UPPER_WORD 0x0003238102#define ACP_SW_IMM_RESP_LOWER_QWORD 0x000323c103#define ACP_SW_IMM_CMD_STS 0x0003240104#define ACP_SW_BRA_BASE_ADDRESS 0x0003244105#define ACP_SW_BRA_TRANSFER_SIZE 0x0003248106#define ACP_SW_BRA_DMA_BUSY 0x000324c107#define ACP_SW_BRA_RESP 0x0003250108#define ACP_SW_BRA_RESP_FRAME_ADDR 0x0003254109#define ACP_SW_BRA_CURRENT_TRANSFER_SIZE 0x0003258110#define ACP_SW_STATE_CHANGE_STATUS_0TO7 0x000325c111#define ACP_SW_STATE_CHANGE_STATUS_8TO11 0x0003260112#define ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7 0x0003264113#define ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11 0x0003268114#define ACP_SW_CLK_FREQUENCY_CTRL 0x000326c115#define ACP_SW_ERROR_INTR_MASK 0x0003270116#define ACP_SW_PHY_TEST_MODE_DATA_OFF 0x0003274117 118#define ACP_DELAY_US 10119#define AMD_SDW_TIMEOUT 1000120#define AMD_SDW_DEFAULT_CLK_FREQ 12000000121 122#define AMD_SDW_MCP_RESP_ACK BIT(0)123#define AMD_SDW_MCP_RESP_NACK BIT(1)124#define AMD_SDW_MCP_RESP_RDATA GENMASK(14, 7)125 126#define AMD_SDW_MCP_CMD_SSP_TAG BIT(31)127#define AMD_SDW_MCP_CMD_COMMAND GENMASK(14, 12)128#define AMD_SDW_MCP_CMD_DEV_ADDR GENMASK(11, 8)129#define AMD_SDW_MCP_CMD_REG_ADDR_HIGH GENMASK(7, 0)130#define AMD_SDW_MCP_CMD_REG_ADDR_LOW GENMASK(31, 24)131#define AMD_SDW_MCP_CMD_REG_DATA GENMASK(14, 7)132#define AMD_SDW_MCP_SLAVE_STAT_0_3 GENMASK(14, 7)133#define AMD_SDW_MCP_SLAVE_STAT_4_11 GENMASK_ULL(39, 24)134#define AMD_SDW_MCP_SLAVE_STATUS_MASK GENMASK(1, 0)135#define AMD_SDW_MCP_SLAVE_STATUS_BITS GENMASK(3, 2)136#define AMD_SDW_MCP_SLAVE_STATUS_8TO_11 GENMASK_ULL(15, 0)137#define AMD_SDW_MCP_SLAVE_STATUS_VALID_MASK(x) BIT(((x) * 4))138#define AMD_SDW_MCP_SLAVE_STAT_SHIFT_MASK(x) (((x) * 4) + 1)139 140#define AMD_SDW_MASTER_SUSPEND_DELAY_MS 2000141#define AMD_SDW_QUIRK_MASK_BUS_ENABLE BIT(0)142 143#define AMD_SDW_IMM_RES_VALID 1144#define AMD_SDW_IMM_CMD_BUSY 2145#define AMD_SDW_ENABLE 1146#define AMD_SDW_DISABLE 0147#define AMD_SDW_BUS_RESET_CLEAR_REQ 0148#define AMD_SDW_BUS_RESET_REQ 1149#define AMD_SDW_BUS_RESET_DONE 2150#define AMD_SDW_BUS_BASE_FREQ 24000000151 152#define AMD_SDW0_EXT_INTR_MASK 0x200000153#define AMD_SDW1_EXT_INTR_MASK 4154#define AMD_SDW_IRQ_MASK_0TO7 0x77777777155#define AMD_SDW_IRQ_MASK_8TO11 0x000c7777156#define AMD_SDW_IRQ_ERROR_MASK 0xff157#define AMD_SDW_MAX_FREQ_NUM 1158#define AMD_SDW0_MAX_TX_PORTS 3159#define AMD_SDW0_MAX_RX_PORTS 3160#define AMD_SDW1_MAX_TX_PORTS 1161#define AMD_SDW1_MAX_RX_PORTS 1162#define AMD_SDW0_MAX_DAI 6163#define AMD_SDW1_MAX_DAI 2164#define AMD_SDW_SLAVE_0_ATTACHED 5165#define AMD_SDW_SSP_COUNTER_VAL 3166 167#define AMD_DPN_FRAME_FMT_PFM GENMASK(1, 0)168#define AMD_DPN_FRAME_FMT_PDM GENMASK(3, 2)169#define AMD_DPN_FRAME_FMT_BLK_PKG_MODE BIT(4)170#define AMD_DPN_FRAME_FMT_BLK_GRP_CTRL GENMASK(6, 5)171#define AMD_DPN_FRAME_FMT_WORD_LEN GENMASK(12, 7)172#define AMD_DPN_FRAME_FMT_PCM_OR_PDM BIT(13)173#define AMD_DPN_HCTRL_HSTOP GENMASK(3, 0)174#define AMD_DPN_HCTRL_HSTART GENMASK(7, 4)175#define AMD_DPN_OFFSET_CTRL_1 GENMASK(7, 0)176#define AMD_DPN_OFFSET_CTRL_2 GENMASK(15, 8)177#define AMD_DPN_CH_EN_LCTRL GENMASK(2, 0)178#define AMD_DPN_CH_EN_CHMASK GENMASK(10, 3)179#define AMD_SDW_STAT_MAX_RETRY_COUNT 100180#define AMD_SDW0_PAD_PULLDOWN_CTRL_ENABLE_MASK 0x7f9f181#define AMD_SDW1_PAD_PULLDOWN_CTRL_ENABLE_MASK 0x7ffa182#define AMD_SDW0_PAD_PULLDOWN_CTRL_DISABLE_MASK 0x60183#define AMD_SDW1_PAD_PULLDOWN_CTRL_DISABLE_MASK 5184#define AMD_SDW0_PAD_KEEPER_EN_MASK 1185#define AMD_SDW1_PAD_KEEPER_EN_MASK 0x10186#define AMD_SDW0_PAD_KEEPER_DISABLE_MASK 0x1e187#define AMD_SDW1_PAD_KEEPER_DISABLE_MASK 0xf188#define AMD_SDW_PREQ_INTR_STAT BIT(19)189#define AMD_SDW_CLK_STOP_DONE 1190#define AMD_SDW_CLK_RESUME_REQ 2191#define AMD_SDW_CLK_RESUME_DONE 3192#define AMD_SDW_WAKE_STAT_MASK BIT(16)193#define AMD_SDW_WAKE_INTR_MASK BIT(16)194 195static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = {196 AMD_SDW_DEFAULT_CLK_FREQ,197};198 199struct sdw_manager_dp_reg {200 u32 frame_fmt_reg;201 u32 sample_int_reg;202 u32 hctrl_dp0_reg;203 u32 offset_reg;204 u32 lane_ctrl_ch_en_reg;205};206 207/*208 * SDW0 Manager instance registers 6 CPU DAI (3 TX & 3 RX Ports)209 * whereas SDW1 Manager Instance registers 2 CPU DAI (one TX & one RX port)210 * Below is the CPU DAI <->Manager port number mapping211 * i.e SDW0 Pin0 -> port number 0 -> AUDIO0 TX212 * SDW0 Pin1 -> Port number 1 -> AUDIO1 TX213 * SDW0 Pin2 -> Port number 2 -> AUDIO2 TX214 * SDW0 Pin3 -> port number 3 -> AUDIO0 RX215 * SDW0 Pin4 -> Port number 4 -> AUDIO1 RX216 * SDW0 Pin5 -> Port number 5 -> AUDIO2 RX217 * Whereas for SDW1 instance218 * SDW1 Pin0 -> port number 0 -> AUDIO1 TX219 * SDW1 Pin1 -> Port number 1 -> AUDIO1 RX220 * Same mapping should be used for programming DMA controller registers in SoundWire DMA driver.221 * i.e if AUDIO0 TX channel is selected then we need to use AUDIO0 TX registers for DMA programming222 * in SoundWire DMA driver.223 */224 225static struct sdw_manager_dp_reg sdw0_manager_dp_reg[AMD_SDW0_MAX_DAI] = {226 {ACP_SW_AUDIO0_TX_FRAME_FORMAT, ACP_SW_AUDIO0_TX_SAMPLEINTERVAL, ACP_SW_AUDIO0_TX_HCTRL_DP0,227 ACP_SW_AUDIO0_TX_OFFSET_DP0, ACP_SW_AUDIO0_TX_CHANNEL_ENABLE_DP0},228 {ACP_SW_AUDIO1_TX_FRAME_FORMAT, ACP_SW_AUDIO1_TX_SAMPLEINTERVAL, ACP_SW_AUDIO1_TX_HCTRL,229 ACP_SW_AUDIO1_TX_OFFSET, ACP_SW_AUDIO1_TX_CHANNEL_ENABLE_DP0},230 {ACP_SW_AUDIO2_TX_FRAME_FORMAT, ACP_SW_AUDIO2_TX_SAMPLEINTERVAL, ACP_SW_AUDIO2_TX_HCTRL,231 ACP_SW_AUDIO2_TX_OFFSET, ACP_SW_AUDIO2_TX_CHANNEL_ENABLE_DP0},232 {ACP_SW_AUDIO0_RX_FRAME_FORMAT, ACP_SW_AUDIO0_RX_SAMPLEINTERVAL, ACP_SW_AUDIO0_RX_HCTRL_DP0,233 ACP_SW_AUDIO0_RX_OFFSET_DP0, ACP_SW_AUDIO0_RX_CHANNEL_ENABLE_DP0},234 {ACP_SW_AUDIO1_RX_FRAME_FORMAT, ACP_SW_AUDIO1_RX_SAMPLEINTERVAL, ACP_SW_AUDIO1_RX_HCTRL,235 ACP_SW_AUDIO1_RX_OFFSET, ACP_SW_AUDIO1_RX_CHANNEL_ENABLE_DP0},236 {ACP_SW_AUDIO2_RX_FRAME_FORMAT, ACP_SW_AUDIO2_RX_SAMPLEINTERVAL, ACP_SW_AUDIO2_RX_HCTRL,237 ACP_SW_AUDIO2_RX_OFFSET, ACP_SW_AUDIO2_RX_CHANNEL_ENABLE_DP0},238};239 240static struct sdw_manager_dp_reg sdw1_manager_dp_reg[AMD_SDW1_MAX_DAI] = {241 {ACP_SW_AUDIO1_TX_FRAME_FORMAT, ACP_SW_AUDIO1_TX_SAMPLEINTERVAL, ACP_SW_AUDIO1_TX_HCTRL,242 ACP_SW_AUDIO1_TX_OFFSET, ACP_SW_AUDIO1_TX_CHANNEL_ENABLE_DP0},243 {ACP_SW_AUDIO1_RX_FRAME_FORMAT, ACP_SW_AUDIO1_RX_SAMPLEINTERVAL, ACP_SW_AUDIO1_RX_HCTRL,244 ACP_SW_AUDIO1_RX_OFFSET, ACP_SW_AUDIO1_RX_CHANNEL_ENABLE_DP0}245};246 247static u32 sdw_manager_reg_mask_array[AMD_SDW_MAX_MANAGER_COUNT] = {248 AMD_SDW0_EXT_INTR_MASK,249 AMD_SDW1_EXT_INTR_MASK250};251#endif252