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1// SPDX-License-Identifier: GPL-2.02/*3 * Driver for Atmel QSPI Controller4 *5 * Copyright (C) 2015 Atmel Corporation6 * Copyright (C) 2018 Cryptera A/S7 *8 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>9 * Author: Piotr Bugalski <bugalski.piotr@gmail.com>10 *11 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.12 */13 14#include <linux/clk.h>15#include <linux/delay.h>16#include <linux/err.h>17#include <linux/interrupt.h>18#include <linux/io.h>19#include <linux/kernel.h>20#include <linux/module.h>21#include <linux/of.h>22#include <linux/of_platform.h>23#include <linux/platform_device.h>24#include <linux/pm_runtime.h>25#include <linux/spi/spi-mem.h>26 27/* QSPI register offsets */28#define QSPI_CR 0x0000 /* Control Register */29#define QSPI_MR 0x0004 /* Mode Register */30#define QSPI_RD 0x0008 /* Receive Data Register */31#define QSPI_TD 0x000c /* Transmit Data Register */32#define QSPI_SR 0x0010 /* Status Register */33#define QSPI_IER 0x0014 /* Interrupt Enable Register */34#define QSPI_IDR 0x0018 /* Interrupt Disable Register */35#define QSPI_IMR 0x001c /* Interrupt Mask Register */36#define QSPI_SCR 0x0020 /* Serial Clock Register */37 38#define QSPI_IAR 0x0030 /* Instruction Address Register */39#define QSPI_ICR 0x0034 /* Instruction Code Register */40#define QSPI_WICR 0x0034 /* Write Instruction Code Register */41#define QSPI_IFR 0x0038 /* Instruction Frame Register */42#define QSPI_RICR 0x003C /* Read Instruction Code Register */43 44#define QSPI_SMR 0x0040 /* Scrambling Mode Register */45#define QSPI_SKR 0x0044 /* Scrambling Key Register */46 47#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */48#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */49 50#define QSPI_VERSION 0x00FC /* Version Register */51 52 53/* Bitfields in QSPI_CR (Control Register) */54#define QSPI_CR_QSPIEN BIT(0)55#define QSPI_CR_QSPIDIS BIT(1)56#define QSPI_CR_SWRST BIT(7)57#define QSPI_CR_LASTXFER BIT(24)58 59/* Bitfields in QSPI_MR (Mode Register) */60#define QSPI_MR_SMM BIT(0)61#define QSPI_MR_LLB BIT(1)62#define QSPI_MR_WDRBT BIT(2)63#define QSPI_MR_SMRM BIT(3)64#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)65#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)66#define QSPI_MR_CSMODE_LASTXFER (1 << 4)67#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)68#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)69#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)70#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)71#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)72#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)73#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)74 75/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */76#define QSPI_SR_RDRF BIT(0)77#define QSPI_SR_TDRE BIT(1)78#define QSPI_SR_TXEMPTY BIT(2)79#define QSPI_SR_OVRES BIT(3)80#define QSPI_SR_CSR BIT(8)81#define QSPI_SR_CSS BIT(9)82#define QSPI_SR_INSTRE BIT(10)83#define QSPI_SR_QSPIENS BIT(24)84 85#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)86 87/* Bitfields in QSPI_SCR (Serial Clock Register) */88#define QSPI_SCR_CPOL BIT(0)89#define QSPI_SCR_CPHA BIT(1)90#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)91#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)92#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)93#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)94 95/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */96#define QSPI_ICR_INST_MASK GENMASK(7, 0)97#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)98#define QSPI_ICR_OPT_MASK GENMASK(23, 16)99#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)100 101/* Bitfields in QSPI_IFR (Instruction Frame Register) */102#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)103#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)104#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)105#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)106#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)107#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)108#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)109#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)110#define QSPI_IFR_INSTEN BIT(4)111#define QSPI_IFR_ADDREN BIT(5)112#define QSPI_IFR_OPTEN BIT(6)113#define QSPI_IFR_DATAEN BIT(7)114#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)115#define QSPI_IFR_OPTL_1BIT (0 << 8)116#define QSPI_IFR_OPTL_2BIT (1 << 8)117#define QSPI_IFR_OPTL_4BIT (2 << 8)118#define QSPI_IFR_OPTL_8BIT (3 << 8)119#define QSPI_IFR_ADDRL BIT(10)120#define QSPI_IFR_TFRTYP_MEM BIT(12)121#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)122#define QSPI_IFR_CRM BIT(14)123#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)124#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)125#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */126 127/* Bitfields in QSPI_SMR (Scrambling Mode Register) */128#define QSPI_SMR_SCREN BIT(0)129#define QSPI_SMR_RVDIS BIT(1)130 131/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */132#define QSPI_WPMR_WPEN BIT(0)133#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)134#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)135 136/* Bitfields in QSPI_WPSR (Write Protection Status Register) */137#define QSPI_WPSR_WPVS BIT(0)138#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)139#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)140 141struct atmel_qspi_caps {142 bool has_qspick;143 bool has_ricr;144};145 146struct atmel_qspi {147 void __iomem *regs;148 void __iomem *mem;149 struct clk *pclk;150 struct clk *qspick;151 struct platform_device *pdev;152 const struct atmel_qspi_caps *caps;153 resource_size_t mmap_size;154 u32 pending;155 u32 mr;156 u32 scr;157 struct completion cmd_completion;158};159 160struct atmel_qspi_mode {161 u8 cmd_buswidth;162 u8 addr_buswidth;163 u8 data_buswidth;164 u32 config;165};166 167static const struct atmel_qspi_mode atmel_qspi_modes[] = {168 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },169 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },170 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },171 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },172 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },173 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },174 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },175};176 177#ifdef VERBOSE_DEBUG178static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)179{180 switch (offset) {181 case QSPI_CR:182 return "CR";183 case QSPI_MR:184 return "MR";185 case QSPI_RD:186 return "MR";187 case QSPI_TD:188 return "TD";189 case QSPI_SR:190 return "SR";191 case QSPI_IER:192 return "IER";193 case QSPI_IDR:194 return "IDR";195 case QSPI_IMR:196 return "IMR";197 case QSPI_SCR:198 return "SCR";199 case QSPI_IAR:200 return "IAR";201 case QSPI_ICR:202 return "ICR/WICR";203 case QSPI_IFR:204 return "IFR";205 case QSPI_RICR:206 return "RICR";207 case QSPI_SMR:208 return "SMR";209 case QSPI_SKR:210 return "SKR";211 case QSPI_WPMR:212 return "WPMR";213 case QSPI_WPSR:214 return "WPSR";215 case QSPI_VERSION:216 return "VERSION";217 default:218 snprintf(tmp, sz, "0x%02x", offset);219 break;220 }221 222 return tmp;223}224#endif /* VERBOSE_DEBUG */225 226static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)227{228 u32 value = readl_relaxed(aq->regs + offset);229 230#ifdef VERBOSE_DEBUG231 char tmp[8];232 233 dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,234 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));235#endif /* VERBOSE_DEBUG */236 237 return value;238}239 240static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)241{242#ifdef VERBOSE_DEBUG243 char tmp[8];244 245 dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,246 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));247#endif /* VERBOSE_DEBUG */248 249 writel_relaxed(value, aq->regs + offset);250}251 252static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,253 const struct atmel_qspi_mode *mode)254{255 if (op->cmd.buswidth != mode->cmd_buswidth)256 return false;257 258 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)259 return false;260 261 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)262 return false;263 264 return true;265}266 267static int atmel_qspi_find_mode(const struct spi_mem_op *op)268{269 u32 i;270 271 for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)272 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))273 return i;274 275 return -EOPNOTSUPP;276}277 278static bool atmel_qspi_supports_op(struct spi_mem *mem,279 const struct spi_mem_op *op)280{281 if (!spi_mem_default_supports_op(mem, op))282 return false;283 284 if (atmel_qspi_find_mode(op) < 0)285 return false;286 287 /* special case not supported by hardware */288 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&289 op->dummy.nbytes == 0)290 return false;291 292 return true;293}294 295static int atmel_qspi_set_cfg(struct atmel_qspi *aq,296 const struct spi_mem_op *op, u32 *offset)297{298 u32 iar, icr, ifr;299 u32 dummy_cycles = 0;300 int mode;301 302 iar = 0;303 icr = QSPI_ICR_INST(op->cmd.opcode);304 ifr = QSPI_IFR_INSTEN;305 306 mode = atmel_qspi_find_mode(op);307 if (mode < 0)308 return mode;309 ifr |= atmel_qspi_modes[mode].config;310 311 if (op->dummy.nbytes)312 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;313 314 /*315 * The controller allows 24 and 32-bit addressing while NAND-flash316 * requires 16-bit long. Handling 8-bit long addresses is done using317 * the option field. For the 16-bit addresses, the workaround depends318 * of the number of requested dummy bits. If there are 8 or more dummy319 * cycles, the address is shifted and sent with the first dummy byte.320 * Otherwise opcode is disabled and the first byte of the address321 * contains the command opcode (works only if the opcode and address322 * use the same buswidth). The limitation is when the 16-bit address is323 * used without enough dummy cycles and the opcode is using a different324 * buswidth than the address.325 */326 if (op->addr.buswidth) {327 switch (op->addr.nbytes) {328 case 0:329 break;330 case 1:331 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;332 icr |= QSPI_ICR_OPT(op->addr.val & 0xff);333 break;334 case 2:335 if (dummy_cycles < 8 / op->addr.buswidth) {336 ifr &= ~QSPI_IFR_INSTEN;337 ifr |= QSPI_IFR_ADDREN;338 iar = (op->cmd.opcode << 16) |339 (op->addr.val & 0xffff);340 } else {341 ifr |= QSPI_IFR_ADDREN;342 iar = (op->addr.val << 8) & 0xffffff;343 dummy_cycles -= 8 / op->addr.buswidth;344 }345 break;346 case 3:347 ifr |= QSPI_IFR_ADDREN;348 iar = op->addr.val & 0xffffff;349 break;350 case 4:351 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;352 iar = op->addr.val & 0x7ffffff;353 break;354 default:355 return -ENOTSUPP;356 }357 }358 359 /* offset of the data access in the QSPI memory space */360 *offset = iar;361 362 /* Set number of dummy cycles */363 if (dummy_cycles)364 ifr |= QSPI_IFR_NBDUM(dummy_cycles);365 366 /* Set data enable and data transfer type. */367 if (op->data.nbytes) {368 ifr |= QSPI_IFR_DATAEN;369 370 if (op->addr.nbytes)371 ifr |= QSPI_IFR_TFRTYP_MEM;372 }373 374 /*375 * If the QSPI controller is set in regular SPI mode, set it in376 * Serial Memory Mode (SMM).377 */378 if (!(aq->mr & QSPI_MR_SMM)) {379 aq->mr |= QSPI_MR_SMM;380 atmel_qspi_write(aq->mr, aq, QSPI_MR);381 }382 383 /* Clear pending interrupts */384 (void)atmel_qspi_read(aq, QSPI_SR);385 386 /* Set QSPI Instruction Frame registers. */387 if (op->addr.nbytes && !op->data.nbytes)388 atmel_qspi_write(iar, aq, QSPI_IAR);389 390 if (aq->caps->has_ricr) {391 if (op->data.dir == SPI_MEM_DATA_IN)392 atmel_qspi_write(icr, aq, QSPI_RICR);393 else394 atmel_qspi_write(icr, aq, QSPI_WICR);395 } else {396 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)397 ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;398 399 atmel_qspi_write(icr, aq, QSPI_ICR);400 }401 402 atmel_qspi_write(ifr, aq, QSPI_IFR);403 404 return 0;405}406 407static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)408{409 struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller);410 u32 sr, offset;411 int err;412 413 /*414 * Check if the address exceeds the MMIO window size. An improvement415 * would be to add support for regular SPI mode and fall back to it416 * when the flash memories overrun the controller's memory space.417 */418 if (op->addr.val + op->data.nbytes > aq->mmap_size)419 return -ENOTSUPP;420 421 err = pm_runtime_resume_and_get(&aq->pdev->dev);422 if (err < 0)423 return err;424 425 err = atmel_qspi_set_cfg(aq, op, &offset);426 if (err)427 goto pm_runtime_put;428 429 /* Skip to the final steps if there is no data */430 if (op->data.nbytes) {431 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */432 (void)atmel_qspi_read(aq, QSPI_IFR);433 434 /* Send/Receive data */435 if (op->data.dir == SPI_MEM_DATA_IN)436 memcpy_fromio(op->data.buf.in, aq->mem + offset,437 op->data.nbytes);438 else439 memcpy_toio(aq->mem + offset, op->data.buf.out,440 op->data.nbytes);441 442 /* Release the chip-select */443 atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);444 }445 446 /* Poll INSTRuction End status */447 sr = atmel_qspi_read(aq, QSPI_SR);448 if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)449 goto pm_runtime_put;450 451 /* Wait for INSTRuction End interrupt */452 reinit_completion(&aq->cmd_completion);453 aq->pending = sr & QSPI_SR_CMD_COMPLETED;454 atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER);455 if (!wait_for_completion_timeout(&aq->cmd_completion,456 msecs_to_jiffies(1000)))457 err = -ETIMEDOUT;458 atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR);459 460pm_runtime_put:461 pm_runtime_mark_last_busy(&aq->pdev->dev);462 pm_runtime_put_autosuspend(&aq->pdev->dev);463 return err;464}465 466static const char *atmel_qspi_get_name(struct spi_mem *spimem)467{468 return dev_name(spimem->spi->dev.parent);469}470 471static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {472 .supports_op = atmel_qspi_supports_op,473 .exec_op = atmel_qspi_exec_op,474 .get_name = atmel_qspi_get_name475};476 477static int atmel_qspi_setup(struct spi_device *spi)478{479 struct spi_controller *ctrl = spi->controller;480 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);481 unsigned long src_rate;482 u32 scbr;483 int ret;484 485 if (ctrl->busy)486 return -EBUSY;487 488 if (!spi->max_speed_hz)489 return -EINVAL;490 491 src_rate = clk_get_rate(aq->pclk);492 if (!src_rate)493 return -EINVAL;494 495 /* Compute the QSPI baudrate */496 scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);497 if (scbr > 0)498 scbr--;499 500 ret = pm_runtime_resume_and_get(ctrl->dev.parent);501 if (ret < 0)502 return ret;503 504 aq->scr &= ~QSPI_SCR_SCBR_MASK;505 aq->scr |= QSPI_SCR_SCBR(scbr);506 atmel_qspi_write(aq->scr, aq, QSPI_SCR);507 508 pm_runtime_mark_last_busy(ctrl->dev.parent);509 pm_runtime_put_autosuspend(ctrl->dev.parent);510 511 return 0;512}513 514static int atmel_qspi_set_cs_timing(struct spi_device *spi)515{516 struct spi_controller *ctrl = spi->controller;517 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);518 unsigned long clk_rate;519 u32 cs_setup;520 int delay;521 int ret;522 523 delay = spi_delay_to_ns(&spi->cs_setup, NULL);524 if (delay <= 0)525 return delay;526 527 clk_rate = clk_get_rate(aq->pclk);528 if (!clk_rate)529 return -EINVAL;530 531 cs_setup = DIV_ROUND_UP((delay * DIV_ROUND_UP(clk_rate, 1000000)),532 1000);533 534 ret = pm_runtime_resume_and_get(ctrl->dev.parent);535 if (ret < 0)536 return ret;537 538 aq->scr &= ~QSPI_SCR_DLYBS_MASK;539 aq->scr |= QSPI_SCR_DLYBS(cs_setup);540 atmel_qspi_write(aq->scr, aq, QSPI_SCR);541 542 pm_runtime_mark_last_busy(ctrl->dev.parent);543 pm_runtime_put_autosuspend(ctrl->dev.parent);544 545 return 0;546}547 548static void atmel_qspi_init(struct atmel_qspi *aq)549{550 /* Reset the QSPI controller */551 atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);552 553 /* Set the QSPI controller by default in Serial Memory Mode */554 aq->mr |= QSPI_MR_SMM;555 atmel_qspi_write(aq->mr, aq, QSPI_MR);556 557 /* Enable the QSPI controller */558 atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);559}560 561static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)562{563 struct atmel_qspi *aq = dev_id;564 u32 status, mask, pending;565 566 status = atmel_qspi_read(aq, QSPI_SR);567 mask = atmel_qspi_read(aq, QSPI_IMR);568 pending = status & mask;569 570 if (!pending)571 return IRQ_NONE;572 573 aq->pending |= pending;574 if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)575 complete(&aq->cmd_completion);576 577 return IRQ_HANDLED;578}579 580static int atmel_qspi_probe(struct platform_device *pdev)581{582 struct spi_controller *ctrl;583 struct atmel_qspi *aq;584 struct resource *res;585 int irq, err = 0;586 587 ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(*aq));588 if (!ctrl)589 return -ENOMEM;590 591 ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;592 ctrl->setup = atmel_qspi_setup;593 ctrl->set_cs_timing = atmel_qspi_set_cs_timing;594 ctrl->bus_num = -1;595 ctrl->mem_ops = &atmel_qspi_mem_ops;596 ctrl->num_chipselect = 1;597 ctrl->dev.of_node = pdev->dev.of_node;598 platform_set_drvdata(pdev, ctrl);599 600 aq = spi_controller_get_devdata(ctrl);601 602 init_completion(&aq->cmd_completion);603 aq->pdev = pdev;604 605 /* Map the registers */606 aq->regs = devm_platform_ioremap_resource_byname(pdev, "qspi_base");607 if (IS_ERR(aq->regs))608 return dev_err_probe(&pdev->dev, PTR_ERR(aq->regs),609 "missing registers\n");610 611 /* Map the AHB memory */612 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");613 aq->mem = devm_ioremap_resource(&pdev->dev, res);614 if (IS_ERR(aq->mem))615 return dev_err_probe(&pdev->dev, PTR_ERR(aq->mem),616 "missing AHB memory\n");617 618 aq->mmap_size = resource_size(res);619 620 /* Get the peripheral clock */621 aq->pclk = devm_clk_get(&pdev->dev, "pclk");622 if (IS_ERR(aq->pclk))623 aq->pclk = devm_clk_get(&pdev->dev, NULL);624 625 if (IS_ERR(aq->pclk))626 return dev_err_probe(&pdev->dev, PTR_ERR(aq->pclk),627 "missing peripheral clock\n");628 629 /* Enable the peripheral clock */630 err = clk_prepare_enable(aq->pclk);631 if (err)632 return dev_err_probe(&pdev->dev, err,633 "failed to enable the peripheral clock\n");634 635 aq->caps = of_device_get_match_data(&pdev->dev);636 if (!aq->caps) {637 dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");638 err = -EINVAL;639 goto disable_pclk;640 }641 642 if (aq->caps->has_qspick) {643 /* Get the QSPI system clock */644 aq->qspick = devm_clk_get(&pdev->dev, "qspick");645 if (IS_ERR(aq->qspick)) {646 dev_err(&pdev->dev, "missing system clock\n");647 err = PTR_ERR(aq->qspick);648 goto disable_pclk;649 }650 651 /* Enable the QSPI system clock */652 err = clk_prepare_enable(aq->qspick);653 if (err) {654 dev_err(&pdev->dev,655 "failed to enable the QSPI system clock\n");656 goto disable_pclk;657 }658 }659 660 /* Request the IRQ */661 irq = platform_get_irq(pdev, 0);662 if (irq < 0) {663 err = irq;664 goto disable_qspick;665 }666 err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,667 0, dev_name(&pdev->dev), aq);668 if (err)669 goto disable_qspick;670 671 pm_runtime_set_autosuspend_delay(&pdev->dev, 500);672 pm_runtime_use_autosuspend(&pdev->dev);673 pm_runtime_set_active(&pdev->dev);674 pm_runtime_enable(&pdev->dev);675 pm_runtime_get_noresume(&pdev->dev);676 677 atmel_qspi_init(aq);678 679 err = spi_register_controller(ctrl);680 if (err) {681 pm_runtime_put_noidle(&pdev->dev);682 pm_runtime_disable(&pdev->dev);683 pm_runtime_set_suspended(&pdev->dev);684 pm_runtime_dont_use_autosuspend(&pdev->dev);685 goto disable_qspick;686 }687 pm_runtime_mark_last_busy(&pdev->dev);688 pm_runtime_put_autosuspend(&pdev->dev);689 690 return 0;691 692disable_qspick:693 clk_disable_unprepare(aq->qspick);694disable_pclk:695 clk_disable_unprepare(aq->pclk);696 697 return err;698}699 700static void atmel_qspi_remove(struct platform_device *pdev)701{702 struct spi_controller *ctrl = platform_get_drvdata(pdev);703 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);704 int ret;705 706 spi_unregister_controller(ctrl);707 708 ret = pm_runtime_get_sync(&pdev->dev);709 if (ret >= 0) {710 atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);711 clk_disable(aq->qspick);712 clk_disable(aq->pclk);713 } else {714 /*715 * atmel_qspi_runtime_{suspend,resume} just disable and enable716 * the two clks respectively. So after resume failed these are717 * off, and we skip hardware access and disabling these clks again.718 */719 dev_warn(&pdev->dev, "Failed to resume device on remove\n");720 }721 722 clk_unprepare(aq->qspick);723 clk_unprepare(aq->pclk);724 725 pm_runtime_disable(&pdev->dev);726 pm_runtime_dont_use_autosuspend(&pdev->dev);727 pm_runtime_put_noidle(&pdev->dev);728}729 730static int __maybe_unused atmel_qspi_suspend(struct device *dev)731{732 struct spi_controller *ctrl = dev_get_drvdata(dev);733 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);734 int ret;735 736 ret = pm_runtime_resume_and_get(dev);737 if (ret < 0)738 return ret;739 740 atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);741 742 pm_runtime_mark_last_busy(dev);743 pm_runtime_force_suspend(dev);744 745 clk_unprepare(aq->qspick);746 clk_unprepare(aq->pclk);747 748 return 0;749}750 751static int __maybe_unused atmel_qspi_resume(struct device *dev)752{753 struct spi_controller *ctrl = dev_get_drvdata(dev);754 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);755 int ret;756 757 ret = clk_prepare(aq->pclk);758 if (ret)759 return ret;760 761 ret = clk_prepare(aq->qspick);762 if (ret) {763 clk_unprepare(aq->pclk);764 return ret;765 }766 767 ret = pm_runtime_force_resume(dev);768 if (ret < 0)769 return ret;770 771 atmel_qspi_init(aq);772 773 atmel_qspi_write(aq->scr, aq, QSPI_SCR);774 775 pm_runtime_mark_last_busy(dev);776 pm_runtime_put_autosuspend(dev);777 778 return 0;779}780 781static int __maybe_unused atmel_qspi_runtime_suspend(struct device *dev)782{783 struct spi_controller *ctrl = dev_get_drvdata(dev);784 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);785 786 clk_disable(aq->qspick);787 clk_disable(aq->pclk);788 789 return 0;790}791 792static int __maybe_unused atmel_qspi_runtime_resume(struct device *dev)793{794 struct spi_controller *ctrl = dev_get_drvdata(dev);795 struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);796 int ret;797 798 ret = clk_enable(aq->pclk);799 if (ret)800 return ret;801 802 ret = clk_enable(aq->qspick);803 if (ret)804 clk_disable(aq->pclk);805 806 return ret;807}808 809static const struct dev_pm_ops __maybe_unused atmel_qspi_pm_ops = {810 SET_SYSTEM_SLEEP_PM_OPS(atmel_qspi_suspend, atmel_qspi_resume)811 SET_RUNTIME_PM_OPS(atmel_qspi_runtime_suspend,812 atmel_qspi_runtime_resume, NULL)813};814 815static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};816 817static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {818 .has_qspick = true,819 .has_ricr = true,820};821 822static const struct of_device_id atmel_qspi_dt_ids[] = {823 {824 .compatible = "atmel,sama5d2-qspi",825 .data = &atmel_sama5d2_qspi_caps,826 },827 {828 .compatible = "microchip,sam9x60-qspi",829 .data = &atmel_sam9x60_qspi_caps,830 },831 { /* sentinel */ }832};833 834MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);835 836static struct platform_driver atmel_qspi_driver = {837 .driver = {838 .name = "atmel_qspi",839 .of_match_table = atmel_qspi_dt_ids,840 .pm = pm_ptr(&atmel_qspi_pm_ops),841 },842 .probe = atmel_qspi_probe,843 .remove_new = atmel_qspi_remove,844};845module_platform_driver(atmel_qspi_driver);846 847MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");848MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");849MODULE_DESCRIPTION("Atmel QSPI Controller driver");850MODULE_LICENSE("GPL v2");851