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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Driver for Broadcom BCM2835 auxiliary SPI Controllers4 *5 * the driver does not rely on the native chipselects at all6 * but only uses the gpio type chipselects7 *8 * Based on: spi-bcm2835.c9 *10 * Copyright (C) 2015 Martin Sperl11 */12 13#include <linux/clk.h>14#include <linux/completion.h>15#include <linux/debugfs.h>16#include <linux/delay.h>17#include <linux/err.h>18#include <linux/interrupt.h>19#include <linux/io.h>20#include <linux/kernel.h>21#include <linux/module.h>22#include <linux/of.h>23#include <linux/platform_device.h>24#include <linux/regmap.h>25#include <linux/spi/spi.h>26#include <linux/spinlock.h>27 28/* define polling limits */29static unsigned int polling_limit_us = 30;30module_param(polling_limit_us, uint, 0664);31MODULE_PARM_DESC(polling_limit_us,32 "time in us to run a transfer in polling mode - if zero no polling is used\n");33 34/*35 * spi register defines36 *37 * note there is garbage in the "official" documentation,38 * so some data is taken from the file:39 * brcm_usrlib/dag/vmcsx/vcinclude/bcm2708_chip/aux_io.h40 * inside of:41 * http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz42 */43 44/* SPI register offsets */45#define BCM2835_AUX_SPI_CNTL0 0x0046#define BCM2835_AUX_SPI_CNTL1 0x0447#define BCM2835_AUX_SPI_STAT 0x0848#define BCM2835_AUX_SPI_PEEK 0x0C49#define BCM2835_AUX_SPI_IO 0x2050#define BCM2835_AUX_SPI_TXHOLD 0x3051 52/* Bitfields in CNTL0 */53#define BCM2835_AUX_SPI_CNTL0_SPEED 0xFFF0000054#define BCM2835_AUX_SPI_CNTL0_SPEED_MAX 0xFFF55#define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT 2056#define BCM2835_AUX_SPI_CNTL0_CS 0x000E000057#define BCM2835_AUX_SPI_CNTL0_POSTINPUT 0x0001000058#define BCM2835_AUX_SPI_CNTL0_VAR_CS 0x0000800059#define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH 0x0000400060#define BCM2835_AUX_SPI_CNTL0_DOUTHOLD 0x0000300061#define BCM2835_AUX_SPI_CNTL0_ENABLE 0x0000080062#define BCM2835_AUX_SPI_CNTL0_IN_RISING 0x0000040063#define BCM2835_AUX_SPI_CNTL0_CLEARFIFO 0x0000020064#define BCM2835_AUX_SPI_CNTL0_OUT_RISING 0x0000010065#define BCM2835_AUX_SPI_CNTL0_CPOL 0x0000008066#define BCM2835_AUX_SPI_CNTL0_MSBF_OUT 0x0000004067#define BCM2835_AUX_SPI_CNTL0_SHIFTLEN 0x0000003F68 69/* Bitfields in CNTL1 */70#define BCM2835_AUX_SPI_CNTL1_CSHIGH 0x0000070071#define BCM2835_AUX_SPI_CNTL1_TXEMPTY 0x0000008072#define BCM2835_AUX_SPI_CNTL1_IDLE 0x0000004073#define BCM2835_AUX_SPI_CNTL1_MSBF_IN 0x0000000274#define BCM2835_AUX_SPI_CNTL1_KEEP_IN 0x0000000175 76/* Bitfields in STAT */77#define BCM2835_AUX_SPI_STAT_TX_LVL 0xFF00000078#define BCM2835_AUX_SPI_STAT_RX_LVL 0x00FF000079#define BCM2835_AUX_SPI_STAT_TX_FULL 0x0000040080#define BCM2835_AUX_SPI_STAT_TX_EMPTY 0x0000020081#define BCM2835_AUX_SPI_STAT_RX_FULL 0x0000010082#define BCM2835_AUX_SPI_STAT_RX_EMPTY 0x0000008083#define BCM2835_AUX_SPI_STAT_BUSY 0x0000004084#define BCM2835_AUX_SPI_STAT_BITCOUNT 0x0000003F85 86struct bcm2835aux_spi {87 void __iomem *regs;88 struct clk *clk;89 int irq;90 u32 cntl[2];91 const u8 *tx_buf;92 u8 *rx_buf;93 int tx_len;94 int rx_len;95 int pending;96 97 u64 count_transfer_polling;98 u64 count_transfer_irq;99 u64 count_transfer_irq_after_poll;100 101 struct dentry *debugfs_dir;102};103 104#if defined(CONFIG_DEBUG_FS)105static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,106 const char *dname)107{108 char name[64];109 struct dentry *dir;110 111 /* get full name */112 snprintf(name, sizeof(name), "spi-bcm2835aux-%s", dname);113 114 /* the base directory */115 dir = debugfs_create_dir(name, NULL);116 bs->debugfs_dir = dir;117 118 /* the counters */119 debugfs_create_u64("count_transfer_polling", 0444, dir,120 &bs->count_transfer_polling);121 debugfs_create_u64("count_transfer_irq", 0444, dir,122 &bs->count_transfer_irq);123 debugfs_create_u64("count_transfer_irq_after_poll", 0444, dir,124 &bs->count_transfer_irq_after_poll);125}126 127static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)128{129 debugfs_remove_recursive(bs->debugfs_dir);130 bs->debugfs_dir = NULL;131}132#else133static void bcm2835aux_debugfs_create(struct bcm2835aux_spi *bs,134 const char *dname)135{136}137 138static void bcm2835aux_debugfs_remove(struct bcm2835aux_spi *bs)139{140}141#endif /* CONFIG_DEBUG_FS */142 143static inline u32 bcm2835aux_rd(struct bcm2835aux_spi *bs, unsigned int reg)144{145 return readl(bs->regs + reg);146}147 148static inline void bcm2835aux_wr(struct bcm2835aux_spi *bs, unsigned int reg,149 u32 val)150{151 writel(val, bs->regs + reg);152}153 154static inline void bcm2835aux_rd_fifo(struct bcm2835aux_spi *bs)155{156 u32 data;157 int count = min(bs->rx_len, 3);158 159 data = bcm2835aux_rd(bs, BCM2835_AUX_SPI_IO);160 if (bs->rx_buf) {161 switch (count) {162 case 3:163 *bs->rx_buf++ = (data >> 16) & 0xff;164 fallthrough;165 case 2:166 *bs->rx_buf++ = (data >> 8) & 0xff;167 fallthrough;168 case 1:169 *bs->rx_buf++ = (data >> 0) & 0xff;170 /* fallthrough - no default */171 }172 }173 bs->rx_len -= count;174 bs->pending -= count;175}176 177static inline void bcm2835aux_wr_fifo(struct bcm2835aux_spi *bs)178{179 u32 data;180 u8 byte;181 int count;182 int i;183 184 /* gather up to 3 bytes to write to the FIFO */185 count = min(bs->tx_len, 3);186 data = 0;187 for (i = 0; i < count; i++) {188 byte = bs->tx_buf ? *bs->tx_buf++ : 0;189 data |= byte << (8 * (2 - i));190 }191 192 /* and set the variable bit-length */193 data |= (count * 8) << 24;194 195 /* and decrement length */196 bs->tx_len -= count;197 bs->pending += count;198 199 /* write to the correct TX-register */200 if (bs->tx_len)201 bcm2835aux_wr(bs, BCM2835_AUX_SPI_TXHOLD, data);202 else203 bcm2835aux_wr(bs, BCM2835_AUX_SPI_IO, data);204}205 206static void bcm2835aux_spi_reset_hw(struct bcm2835aux_spi *bs)207{208 /* disable spi clearing fifo and interrupts */209 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, 0);210 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0,211 BCM2835_AUX_SPI_CNTL0_CLEARFIFO);212}213 214static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)215{216 u32 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT);217 218 /* check if we have data to read */219 for (; bs->rx_len && (stat & BCM2835_AUX_SPI_STAT_RX_LVL);220 stat = bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT))221 bcm2835aux_rd_fifo(bs);222 223 /* check if we have data to write */224 while (bs->tx_len &&225 (bs->pending < 12) &&226 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &227 BCM2835_AUX_SPI_STAT_TX_FULL))) {228 bcm2835aux_wr_fifo(bs);229 }230}231 232static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)233{234 struct spi_controller *host = dev_id;235 struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);236 237 /* IRQ may be shared, so return if our interrupts are disabled */238 if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &239 (BCM2835_AUX_SPI_CNTL1_TXEMPTY | BCM2835_AUX_SPI_CNTL1_IDLE)))240 return IRQ_NONE;241 242 /* do common fifo handling */243 bcm2835aux_spi_transfer_helper(bs);244 245 if (!bs->tx_len) {246 /* disable tx fifo empty interrupt */247 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |248 BCM2835_AUX_SPI_CNTL1_IDLE);249 }250 251 /* and if rx_len is 0 then disable interrupts and wake up completion */252 if (!bs->rx_len) {253 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);254 spi_finalize_current_transfer(host);255 }256 257 return IRQ_HANDLED;258}259 260static int __bcm2835aux_spi_transfer_one_irq(struct spi_controller *host,261 struct spi_device *spi,262 struct spi_transfer *tfr)263{264 struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);265 266 /* enable interrupts */267 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |268 BCM2835_AUX_SPI_CNTL1_TXEMPTY |269 BCM2835_AUX_SPI_CNTL1_IDLE);270 271 /* and wait for finish... */272 return 1;273}274 275static int bcm2835aux_spi_transfer_one_irq(struct spi_controller *host,276 struct spi_device *spi,277 struct spi_transfer *tfr)278{279 struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);280 281 /* update statistics */282 bs->count_transfer_irq++;283 284 /* fill in registers and fifos before enabling interrupts */285 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);286 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);287 288 /* fill in tx fifo with data before enabling interrupts */289 while ((bs->tx_len) &&290 (bs->pending < 12) &&291 (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_STAT) &292 BCM2835_AUX_SPI_STAT_TX_FULL))) {293 bcm2835aux_wr_fifo(bs);294 }295 296 /* now run the interrupt mode */297 return __bcm2835aux_spi_transfer_one_irq(host, spi, tfr);298}299 300static int bcm2835aux_spi_transfer_one_poll(struct spi_controller *host,301 struct spi_device *spi,302 struct spi_transfer *tfr)303{304 struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);305 unsigned long timeout;306 307 /* update statistics */308 bs->count_transfer_polling++;309 310 /* configure spi */311 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);312 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);313 314 /* set the timeout to at least 2 jiffies */315 timeout = jiffies + 2 + HZ * polling_limit_us / 1000000;316 317 /* loop until finished the transfer */318 while (bs->rx_len) {319 320 /* do common fifo handling */321 bcm2835aux_spi_transfer_helper(bs);322 323 /* there is still data pending to read check the timeout */324 if (bs->rx_len && time_after(jiffies, timeout)) {325 dev_dbg_ratelimited(&spi->dev,326 "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n",327 jiffies - timeout,328 bs->tx_len, bs->rx_len);329 /* forward to interrupt handler */330 bs->count_transfer_irq_after_poll++;331 return __bcm2835aux_spi_transfer_one_irq(host,332 spi, tfr);333 }334 }335 336 /* and return without waiting for completion */337 return 0;338}339 340static int bcm2835aux_spi_transfer_one(struct spi_controller *host,341 struct spi_device *spi,342 struct spi_transfer *tfr)343{344 struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);345 unsigned long spi_hz, clk_hz, speed;346 unsigned long hz_per_byte, byte_limit;347 348 /* calculate the registers to handle349 *350 * note that we use the variable data mode, which351 * is not optimal for longer transfers as we waste registers352 * resulting (potentially) in more interrupts when transferring353 * more than 12 bytes354 */355 356 /* set clock */357 spi_hz = tfr->speed_hz;358 clk_hz = clk_get_rate(bs->clk);359 360 if (spi_hz >= clk_hz / 2) {361 speed = 0;362 } else if (spi_hz) {363 speed = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;364 if (speed > BCM2835_AUX_SPI_CNTL0_SPEED_MAX)365 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;366 } else { /* the slowest we can go */367 speed = BCM2835_AUX_SPI_CNTL0_SPEED_MAX;368 }369 /* mask out old speed from previous spi_transfer */370 bs->cntl[0] &= ~(BCM2835_AUX_SPI_CNTL0_SPEED);371 /* set the new speed */372 bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT;373 374 tfr->effective_speed_hz = clk_hz / (2 * (speed + 1));375 376 /* set transmit buffers and length */377 bs->tx_buf = tfr->tx_buf;378 bs->rx_buf = tfr->rx_buf;379 bs->tx_len = tfr->len;380 bs->rx_len = tfr->len;381 bs->pending = 0;382 383 /* Calculate the estimated time in us the transfer runs. Note that384 * there are 2 idle clocks cycles after each chunk getting385 * transferred - in our case the chunk size is 3 bytes, so we386 * approximate this by 9 cycles/byte. This is used to find the number387 * of Hz per byte per polling limit. E.g., we can transfer 1 byte in388 * 30 µs per 300,000 Hz of bus clock.389 */390 hz_per_byte = polling_limit_us ? (9 * 1000000) / polling_limit_us : 0;391 byte_limit = hz_per_byte ? tfr->effective_speed_hz / hz_per_byte : 1;392 393 /* run in polling mode for short transfers */394 if (tfr->len < byte_limit)395 return bcm2835aux_spi_transfer_one_poll(host, spi, tfr);396 397 /* run in interrupt mode for all others */398 return bcm2835aux_spi_transfer_one_irq(host, spi, tfr);399}400 401static int bcm2835aux_spi_prepare_message(struct spi_controller *host,402 struct spi_message *msg)403{404 struct spi_device *spi = msg->spi;405 struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);406 407 bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |408 BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |409 BCM2835_AUX_SPI_CNTL0_MSBF_OUT;410 bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN;411 412 /* handle all the modes */413 if (spi->mode & SPI_CPOL) {414 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL;415 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_OUT_RISING;416 } else {417 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_IN_RISING;418 }419 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);420 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]);421 422 return 0;423}424 425static int bcm2835aux_spi_unprepare_message(struct spi_controller *host,426 struct spi_message *msg)427{428 struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);429 430 bcm2835aux_spi_reset_hw(bs);431 432 return 0;433}434 435static void bcm2835aux_spi_handle_err(struct spi_controller *host,436 struct spi_message *msg)437{438 struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);439 440 bcm2835aux_spi_reset_hw(bs);441}442 443static int bcm2835aux_spi_setup(struct spi_device *spi)444{445 /* sanity check for native cs */446 if (spi->mode & SPI_NO_CS)447 return 0;448 449 if (spi_get_csgpiod(spi, 0))450 return 0;451 452 /* for dt-backwards compatibility: only support native on CS0453 * known things not supported with broken native CS:454 * * multiple chip-selects: cs0-cs2 are all455 * simultaniously asserted whenever there is a transfer456 * this even includes SPI_NO_CS457 * * SPI_CS_HIGH: cs are always asserted low458 * * cs_change: cs is deasserted after each spi_transfer459 * * cs_delay_usec: cs is always deasserted one SCK cycle460 * after the last transfer461 * probably more...462 */463 dev_warn(&spi->dev,464 "Native CS is not supported - please configure cs-gpio in device-tree\n");465 466 if (spi_get_chipselect(spi, 0) == 0)467 return 0;468 469 dev_warn(&spi->dev, "Native CS is not working for cs > 0\n");470 471 return -EINVAL;472}473 474static int bcm2835aux_spi_probe(struct platform_device *pdev)475{476 struct spi_controller *host;477 struct bcm2835aux_spi *bs;478 unsigned long clk_hz;479 int err;480 481 host = devm_spi_alloc_host(&pdev->dev, sizeof(*bs));482 if (!host)483 return -ENOMEM;484 485 platform_set_drvdata(pdev, host);486 host->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);487 host->bits_per_word_mask = SPI_BPW_MASK(8);488 /* even though the driver never officially supported native CS489 * allow a single native CS for legacy DT support purposes when490 * no cs-gpio is configured.491 * Known limitations for native cs are:492 * * multiple chip-selects: cs0-cs2 are all simultaniously asserted493 * whenever there is a transfer - this even includes SPI_NO_CS494 * * SPI_CS_HIGH: is ignores - cs are always asserted low495 * * cs_change: cs is deasserted after each spi_transfer496 * * cs_delay_usec: cs is always deasserted one SCK cycle after497 * a spi_transfer498 */499 host->num_chipselect = 1;500 host->setup = bcm2835aux_spi_setup;501 host->transfer_one = bcm2835aux_spi_transfer_one;502 host->handle_err = bcm2835aux_spi_handle_err;503 host->prepare_message = bcm2835aux_spi_prepare_message;504 host->unprepare_message = bcm2835aux_spi_unprepare_message;505 host->dev.of_node = pdev->dev.of_node;506 host->use_gpio_descriptors = true;507 508 bs = spi_controller_get_devdata(host);509 510 /* the main area */511 bs->regs = devm_platform_ioremap_resource(pdev, 0);512 if (IS_ERR(bs->regs))513 return PTR_ERR(bs->regs);514 515 bs->clk = devm_clk_get_enabled(&pdev->dev, NULL);516 if (IS_ERR(bs->clk)) {517 err = PTR_ERR(bs->clk);518 dev_err(&pdev->dev, "could not get clk: %d\n", err);519 return err;520 }521 522 bs->irq = platform_get_irq(pdev, 0);523 if (bs->irq < 0)524 return bs->irq;525 526 /* just checking if the clock returns a sane value */527 clk_hz = clk_get_rate(bs->clk);528 if (!clk_hz) {529 dev_err(&pdev->dev, "clock returns 0 Hz\n");530 return -ENODEV;531 }532 533 /* reset SPI-HW block */534 bcm2835aux_spi_reset_hw(bs);535 536 err = devm_request_irq(&pdev->dev, bs->irq,537 bcm2835aux_spi_interrupt,538 IRQF_SHARED,539 dev_name(&pdev->dev), host);540 if (err) {541 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);542 return err;543 }544 545 err = spi_register_controller(host);546 if (err) {547 dev_err(&pdev->dev, "could not register SPI host: %d\n", err);548 return err;549 }550 551 bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev));552 553 return 0;554}555 556static void bcm2835aux_spi_remove(struct platform_device *pdev)557{558 struct spi_controller *host = platform_get_drvdata(pdev);559 struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);560 561 bcm2835aux_debugfs_remove(bs);562 563 spi_unregister_controller(host);564 565 bcm2835aux_spi_reset_hw(bs);566}567 568static const struct of_device_id bcm2835aux_spi_match[] = {569 { .compatible = "brcm,bcm2835-aux-spi", },570 {}571};572MODULE_DEVICE_TABLE(of, bcm2835aux_spi_match);573 574static struct platform_driver bcm2835aux_spi_driver = {575 .driver = {576 .name = "spi-bcm2835aux",577 .of_match_table = bcm2835aux_spi_match,578 },579 .probe = bcm2835aux_spi_probe,580 .remove_new = bcm2835aux_spi_remove,581};582module_platform_driver(bcm2835aux_spi_driver);583 584MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835 aux");585MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>");586MODULE_LICENSE("GPL");587