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1// SPDX-License-Identifier: GPL-2.02//3// CS42L43 SPI Controller Driver4//5// Copyright (C) 2022-2023 Cirrus Logic, Inc. and6// Cirrus Logic International Semiconductor Ltd.7 8#include <linux/acpi.h>9#include <linux/array_size.h>10#include <linux/bits.h>11#include <linux/bitfield.h>12#include <linux/cleanup.h>13#include <linux/device.h>14#include <linux/errno.h>15#include <linux/gpio/machine.h>16#include <linux/gpio/property.h>17#include <linux/mfd/cs42l43.h>18#include <linux/mfd/cs42l43-regs.h>19#include <linux/mod_devicetable.h>20#include <linux/module.h>21#include <linux/of.h>22#include <linux/platform_device.h>23#include <linux/pm_runtime.h>24#include <linux/property.h>25#include <linux/regmap.h>26#include <linux/spi/spi.h>27#include <linux/units.h>28 29#define CS42L43_FIFO_SIZE 1630#define CS42L43_SPI_ROOT_HZ 4915200031#define CS42L43_SPI_MAX_LENGTH 6553232 33enum cs42l43_spi_cmd {34 CS42L43_WRITE,35 CS42L43_READ36};37 38struct cs42l43_spi {39 struct device *dev;40 struct regmap *regmap;41 struct spi_controller *ctlr;42};43 44static const unsigned int cs42l43_clock_divs[] = {45 2, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 3046};47 48static struct spi_board_info amp_info_template = {49 .modalias = "cs35l56",50 .max_speed_hz = 11 * HZ_PER_MHZ,51 .mode = SPI_MODE_0,52};53 54static const struct software_node cs42l43_gpiochip_swnode = {55 .name = "cs42l43-pinctrl",56};57 58static const struct software_node_ref_args cs42l43_cs_refs[] = {59 SOFTWARE_NODE_REFERENCE(&cs42l43_gpiochip_swnode, 0, GPIO_ACTIVE_LOW),60 SOFTWARE_NODE_REFERENCE(&swnode_gpio_undefined),61};62 63static const struct property_entry cs42l43_cs_props[] = {64 PROPERTY_ENTRY_REF_ARRAY("cs-gpios", cs42l43_cs_refs),65 {}66};67 68static int cs42l43_spi_tx(struct regmap *regmap, const u8 *buf, unsigned int len)69{70 const u8 *end = buf + len;71 u32 val = 0;72 int ret;73 74 while (buf < end) {75 const u8 *block = min(buf + CS42L43_FIFO_SIZE, end);76 77 while (buf < block) {78 const u8 *word = min(buf + sizeof(u32), block);79 int pad = (buf + sizeof(u32)) - word;80 81 while (buf < word) {82 val >>= BITS_PER_BYTE;83 val |= FIELD_PREP(GENMASK(31, 24), *buf);84 85 buf++;86 }87 88 val >>= pad * BITS_PER_BYTE;89 90 regmap_write(regmap, CS42L43_TX_DATA, val);91 }92 93 regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_TX_DONE_MASK);94 95 ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,96 val, (val & CS42L43_SPI_TX_REQUEST_MASK),97 1000, 5000);98 if (ret)99 return ret;100 }101 102 return 0;103}104 105static int cs42l43_spi_rx(struct regmap *regmap, u8 *buf, unsigned int len)106{107 u8 *end = buf + len;108 u32 val;109 int ret;110 111 while (buf < end) {112 u8 *block = min(buf + CS42L43_FIFO_SIZE, end);113 114 ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,115 val, (val & CS42L43_SPI_RX_REQUEST_MASK),116 1000, 5000);117 if (ret)118 return ret;119 120 while (buf < block) {121 u8 *word = min(buf + sizeof(u32), block);122 123 ret = regmap_read(regmap, CS42L43_RX_DATA, &val);124 if (ret)125 return ret;126 127 while (buf < word) {128 *buf = FIELD_GET(GENMASK(7, 0), val);129 130 val >>= BITS_PER_BYTE;131 buf++;132 }133 }134 135 regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_RX_DONE_MASK);136 }137 138 return 0;139}140 141static int cs42l43_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,142 struct spi_transfer *tfr)143{144 struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);145 int i, ret = -EINVAL;146 147 for (i = 0; i < ARRAY_SIZE(cs42l43_clock_divs); i++) {148 if (CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[i] <= tfr->speed_hz)149 break;150 }151 152 if (i == ARRAY_SIZE(cs42l43_clock_divs))153 return -EINVAL;154 155 regmap_write(priv->regmap, CS42L43_SPI_CLK_CONFIG1, i);156 157 if (tfr->tx_buf) {158 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_WRITE);159 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG4, tfr->len - 1);160 } else if (tfr->rx_buf) {161 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_READ);162 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG5, tfr->len - 1);163 }164 165 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG1, CS42L43_SPI_START_MASK);166 167 if (tfr->tx_buf)168 ret = cs42l43_spi_tx(priv->regmap, (const u8 *)tfr->tx_buf, tfr->len);169 else if (tfr->rx_buf)170 ret = cs42l43_spi_rx(priv->regmap, (u8 *)tfr->rx_buf, tfr->len);171 172 return ret;173}174 175static void cs42l43_set_cs(struct spi_device *spi, bool is_high)176{177 struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);178 179 regmap_write(priv->regmap, CS42L43_SPI_CONFIG2, !is_high);180}181 182static int cs42l43_prepare_message(struct spi_controller *ctlr, struct spi_message *msg)183{184 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);185 struct spi_device *spi = msg->spi;186 unsigned int spi_config1 = 0;187 188 /* select another internal CS, which doesn't exist, so CS 0 is not used */189 if (spi_get_csgpiod(spi, 0))190 spi_config1 |= 1 << CS42L43_SPI_SS_SEL_SHIFT;191 if (spi->mode & SPI_CPOL)192 spi_config1 |= CS42L43_SPI_CPOL_MASK;193 if (spi->mode & SPI_CPHA)194 spi_config1 |= CS42L43_SPI_CPHA_MASK;195 if (spi->mode & SPI_3WIRE)196 spi_config1 |= CS42L43_SPI_THREE_WIRE_MASK;197 198 regmap_write(priv->regmap, CS42L43_SPI_CONFIG1, spi_config1);199 200 return 0;201}202 203static int cs42l43_prepare_transfer_hardware(struct spi_controller *ctlr)204{205 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);206 int ret;207 208 ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, CS42L43_SPI_MSTR_EN_MASK);209 if (ret)210 dev_err(priv->dev, "Failed to enable SPI controller: %d\n", ret);211 212 return ret;213}214 215static int cs42l43_unprepare_transfer_hardware(struct spi_controller *ctlr)216{217 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);218 int ret;219 220 ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, 0);221 if (ret)222 dev_err(priv->dev, "Failed to disable SPI controller: %d\n", ret);223 224 return ret;225}226 227static size_t cs42l43_spi_max_length(struct spi_device *spi)228{229 return CS42L43_SPI_MAX_LENGTH;230}231 232static struct fwnode_handle *cs42l43_find_xu_node(struct fwnode_handle *fwnode)233{234 static const u32 func_smart_amp = 0x1;235 struct fwnode_handle *child_fwnode, *ext_fwnode;236 u32 function;237 int ret;238 239 fwnode_for_each_child_node(fwnode, child_fwnode) {240 acpi_handle handle = ACPI_HANDLE_FWNODE(child_fwnode);241 242 ret = acpi_get_local_address(handle, &function);243 if (ret || function != func_smart_amp)244 continue;245 246 ext_fwnode = fwnode_get_named_child_node(child_fwnode,247 "mipi-sdca-function-expansion-subproperties");248 if (!ext_fwnode)249 continue;250 251 fwnode_handle_put(child_fwnode);252 253 return ext_fwnode;254 }255 256 return NULL;257}258 259static struct spi_board_info *cs42l43_create_bridge_amp(struct cs42l43_spi *priv,260 const char * const name,261 int cs, int spkid)262{263 struct property_entry *props = NULL;264 struct software_node *swnode;265 struct spi_board_info *info;266 267 if (spkid >= 0) {268 props = devm_kmalloc(priv->dev, sizeof(*props), GFP_KERNEL);269 if (!props)270 return NULL;271 272 *props = PROPERTY_ENTRY_U32("cirrus,speaker-id", spkid);273 }274 275 swnode = devm_kmalloc(priv->dev, sizeof(*swnode), GFP_KERNEL);276 if (!swnode)277 return NULL;278 279 *swnode = SOFTWARE_NODE(name, props, NULL);280 281 info = devm_kmemdup(priv->dev, &_info_template,282 sizeof(amp_info_template), GFP_KERNEL);283 if (!info)284 return NULL;285 286 info->chip_select = cs;287 info->swnode = swnode;288 289 return info;290}291 292static void cs42l43_release_of_node(void *data)293{294 fwnode_handle_put(data);295}296 297static void cs42l43_release_sw_node(void *data)298{299 software_node_unregister(&cs42l43_gpiochip_swnode);300}301 302static int cs42l43_spi_probe(struct platform_device *pdev)303{304 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);305 struct cs42l43_spi *priv;306 struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev);307 struct fwnode_handle *xu_fwnode __free(fwnode_handle) = cs42l43_find_xu_node(fwnode);308 int nsidecars = 0;309 int ret;310 311 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);312 if (!priv)313 return -ENOMEM;314 315 priv->ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*priv->ctlr));316 if (!priv->ctlr)317 return -ENOMEM;318 319 spi_controller_set_devdata(priv->ctlr, priv);320 321 priv->dev = &pdev->dev;322 priv->regmap = cs42l43->regmap;323 324 priv->ctlr->prepare_message = cs42l43_prepare_message;325 priv->ctlr->prepare_transfer_hardware = cs42l43_prepare_transfer_hardware;326 priv->ctlr->unprepare_transfer_hardware = cs42l43_unprepare_transfer_hardware;327 priv->ctlr->transfer_one = cs42l43_transfer_one;328 priv->ctlr->set_cs = cs42l43_set_cs;329 priv->ctlr->max_transfer_size = cs42l43_spi_max_length;330 priv->ctlr->mode_bits = SPI_3WIRE | SPI_MODE_X_MASK;331 priv->ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;332 priv->ctlr->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |333 SPI_BPW_MASK(32);334 priv->ctlr->min_speed_hz = CS42L43_SPI_ROOT_HZ /335 cs42l43_clock_divs[ARRAY_SIZE(cs42l43_clock_divs) - 1];336 priv->ctlr->max_speed_hz = CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[0];337 priv->ctlr->use_gpio_descriptors = true;338 priv->ctlr->auto_runtime_pm = true;339 340 ret = devm_pm_runtime_enable(priv->dev);341 if (ret)342 return ret;343 344 pm_runtime_idle(priv->dev);345 346 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG6, CS42L43_FIFO_SIZE - 1);347 regmap_write(priv->regmap, CS42L43_TRAN_CONFIG7, CS42L43_FIFO_SIZE - 1);348 349 // Disable Watchdog timer and enable stall350 regmap_write(priv->regmap, CS42L43_SPI_CONFIG3, 0);351 regmap_write(priv->regmap, CS42L43_SPI_CONFIG4, CS42L43_SPI_STALL_ENA_MASK);352 353 if (is_of_node(fwnode)) {354 fwnode = fwnode_get_named_child_node(fwnode, "spi");355 ret = devm_add_action_or_reset(priv->dev, cs42l43_release_of_node, fwnode);356 if (ret)357 return ret;358 }359 360 fwnode_property_read_u32(xu_fwnode, "01fa-sidecar-instances", &nsidecars);361 362 if (nsidecars) {363 ret = software_node_register(&cs42l43_gpiochip_swnode);364 if (ret)365 return dev_err_probe(priv->dev, ret,366 "Failed to register gpio swnode\n");367 368 ret = devm_add_action_or_reset(priv->dev, cs42l43_release_sw_node, NULL);369 if (ret)370 return ret;371 372 ret = device_create_managed_software_node(&priv->ctlr->dev,373 cs42l43_cs_props, NULL);374 if (ret)375 return dev_err_probe(priv->dev, ret, "Failed to add swnode\n");376 } else {377 device_set_node(&priv->ctlr->dev, fwnode);378 }379 380 ret = devm_spi_register_controller(priv->dev, priv->ctlr);381 if (ret)382 return dev_err_probe(priv->dev, ret,383 "Failed to register SPI controller\n");384 385 if (nsidecars) {386 struct spi_board_info *ampl_info;387 struct spi_board_info *ampr_info;388 int spkid = -EINVAL;389 390 fwnode_property_read_u32(xu_fwnode, "01fa-spk-id-val", &spkid);391 392 dev_dbg(priv->dev, "Found speaker ID %d\n", spkid);393 394 ampl_info = cs42l43_create_bridge_amp(priv, "cs35l56-left", 0, spkid);395 if (!ampl_info)396 return -ENOMEM;397 398 ampr_info = cs42l43_create_bridge_amp(priv, "cs35l56-right", 1, spkid);399 if (!ampr_info)400 return -ENOMEM;401 402 if (!spi_new_device(priv->ctlr, ampl_info))403 return dev_err_probe(priv->dev, -ENODEV,404 "Failed to create left amp slave\n");405 406 if (!spi_new_device(priv->ctlr, ampr_info))407 return dev_err_probe(priv->dev, -ENODEV,408 "Failed to create right amp slave\n");409 }410 411 return 0;412}413 414static const struct platform_device_id cs42l43_spi_id_table[] = {415 { "cs42l43-spi", },416 {}417};418MODULE_DEVICE_TABLE(platform, cs42l43_spi_id_table);419 420static struct platform_driver cs42l43_spi_driver = {421 .driver = {422 .name = "cs42l43-spi",423 },424 .probe = cs42l43_spi_probe,425 .id_table = cs42l43_spi_id_table,426};427module_platform_driver(cs42l43_spi_driver);428 429MODULE_IMPORT_NS(GPIO_SWNODE);430MODULE_DESCRIPTION("CS42L43 SPI Driver");431MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");432MODULE_AUTHOR("Maciej Strozek <mstrozek@opensource.cirrus.com>");433MODULE_LICENSE("GPL");434