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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Copyright (C) 2009 Texas Instruments.4 * Copyright (C) 2010 EF Johnson Technologies5 */6 7#include <linux/interrupt.h>8#include <linux/io.h>9#include <linux/gpio/consumer.h>10#include <linux/module.h>11#include <linux/delay.h>12#include <linux/platform_device.h>13#include <linux/err.h>14#include <linux/clk.h>15#include <linux/dmaengine.h>16#include <linux/dma-mapping.h>17#include <linux/of.h>18#include <linux/spi/spi.h>19#include <linux/spi/spi_bitbang.h>20#include <linux/slab.h>21 22#include <linux/platform_data/spi-davinci.h>23 24#define CS_DEFAULT 0xFF25 26#define SPIFMT_PHASE_MASK BIT(16)27#define SPIFMT_POLARITY_MASK BIT(17)28#define SPIFMT_DISTIMER_MASK BIT(18)29#define SPIFMT_SHIFTDIR_MASK BIT(20)30#define SPIFMT_WAITENA_MASK BIT(21)31#define SPIFMT_PARITYENA_MASK BIT(22)32#define SPIFMT_ODD_PARITY_MASK BIT(23)33#define SPIFMT_WDELAY_MASK 0x3f000000u34#define SPIFMT_WDELAY_SHIFT 2435#define SPIFMT_PRESCALE_SHIFT 836 37/* SPIPC0 */38#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */39#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */40#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */41#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */42 43#define SPIINT_MASKALL 0x0101035F44#define SPIINT_MASKINT 0x0000015F45#define SPI_INTLVL_1 0x000001FF46#define SPI_INTLVL_0 0x0000000047 48/* SPIDAT1 (upper 16 bit defines) */49#define SPIDAT1_CSHOLD_MASK BIT(12)50#define SPIDAT1_WDEL BIT(10)51 52/* SPIGCR1 */53#define SPIGCR1_CLKMOD_MASK BIT(1)54#define SPIGCR1_MASTER_MASK BIT(0)55#define SPIGCR1_POWERDOWN_MASK BIT(8)56#define SPIGCR1_LOOPBACK_MASK BIT(16)57#define SPIGCR1_SPIENA_MASK BIT(24)58 59/* SPIBUF */60#define SPIBUF_TXFULL_MASK BIT(29)61#define SPIBUF_RXEMPTY_MASK BIT(31)62 63/* SPIDELAY */64#define SPIDELAY_C2TDELAY_SHIFT 2465#define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)66#define SPIDELAY_T2CDELAY_SHIFT 1667#define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)68#define SPIDELAY_T2EDELAY_SHIFT 869#define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)70#define SPIDELAY_C2EDELAY_SHIFT 071#define SPIDELAY_C2EDELAY_MASK 0xFF72 73/* Error Masks */74#define SPIFLG_DLEN_ERR_MASK BIT(0)75#define SPIFLG_TIMEOUT_MASK BIT(1)76#define SPIFLG_PARERR_MASK BIT(2)77#define SPIFLG_DESYNC_MASK BIT(3)78#define SPIFLG_BITERR_MASK BIT(4)79#define SPIFLG_OVRRUN_MASK BIT(6)80#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)81#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \82 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \83 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \84 | SPIFLG_OVRRUN_MASK)85 86#define SPIINT_DMA_REQ_EN BIT(16)87 88/* SPI Controller registers */89#define SPIGCR0 0x0090#define SPIGCR1 0x0491#define SPIINT 0x0892#define SPILVL 0x0c93#define SPIFLG 0x1094#define SPIPC0 0x1495#define SPIDAT1 0x3c96#define SPIBUF 0x4097#define SPIDELAY 0x4898#define SPIDEF 0x4c99#define SPIFMT0 0x50100 101#define DMA_MIN_BYTES 16102 103/* SPI Controller driver's private data. */104struct davinci_spi {105 struct spi_bitbang bitbang;106 struct clk *clk;107 108 u8 version;109 resource_size_t pbase;110 void __iomem *base;111 u32 irq;112 struct completion done;113 114 const void *tx;115 void *rx;116 int rcount;117 int wcount;118 119 struct dma_chan *dma_rx;120 struct dma_chan *dma_tx;121 122 struct davinci_spi_platform_data pdata;123 124 void (*get_rx)(u32 rx_data, struct davinci_spi *);125 u32 (*get_tx)(struct davinci_spi *);126 127 u8 *bytes_per_word;128 129 u8 prescaler_limit;130};131 132static struct davinci_spi_config davinci_spi_default_cfg;133 134static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)135{136 if (dspi->rx) {137 u8 *rx = dspi->rx;138 *rx++ = (u8)data;139 dspi->rx = rx;140 }141}142 143static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)144{145 if (dspi->rx) {146 u16 *rx = dspi->rx;147 *rx++ = (u16)data;148 dspi->rx = rx;149 }150}151 152static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)153{154 u32 data = 0;155 156 if (dspi->tx) {157 const u8 *tx = dspi->tx;158 159 data = *tx++;160 dspi->tx = tx;161 }162 return data;163}164 165static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)166{167 u32 data = 0;168 169 if (dspi->tx) {170 const u16 *tx = dspi->tx;171 172 data = *tx++;173 dspi->tx = tx;174 }175 return data;176}177 178static inline void set_io_bits(void __iomem *addr, u32 bits)179{180 u32 v = ioread32(addr);181 182 v |= bits;183 iowrite32(v, addr);184}185 186static inline void clear_io_bits(void __iomem *addr, u32 bits)187{188 u32 v = ioread32(addr);189 190 v &= ~bits;191 iowrite32(v, addr);192}193 194/*195 * Interface to control the chip select signal196 */197static void davinci_spi_chipselect(struct spi_device *spi, int value)198{199 struct davinci_spi *dspi;200 struct davinci_spi_config *spicfg = spi->controller_data;201 u8 chip_sel = spi_get_chipselect(spi, 0);202 u16 spidat1 = CS_DEFAULT;203 204 dspi = spi_controller_get_devdata(spi->controller);205 206 /* program delay transfers if tx_delay is non zero */207 if (spicfg && spicfg->wdelay)208 spidat1 |= SPIDAT1_WDEL;209 210 /*211 * Board specific chip select logic decides the polarity and cs212 * line for the controller213 */214 if (spi_get_csgpiod(spi, 0)) {215 if (value == BITBANG_CS_ACTIVE)216 gpiod_set_value(spi_get_csgpiod(spi, 0), 1);217 else218 gpiod_set_value(spi_get_csgpiod(spi, 0), 0);219 } else {220 if (value == BITBANG_CS_ACTIVE) {221 if (!(spi->mode & SPI_CS_WORD))222 spidat1 |= SPIDAT1_CSHOLD_MASK;223 spidat1 &= ~(0x1 << chip_sel);224 }225 }226 227 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);228}229 230/**231 * davinci_spi_get_prescale - Calculates the correct prescale value232 * @dspi: the controller data233 * @max_speed_hz: the maximum rate the SPI clock can run at234 *235 * This function calculates the prescale value that generates a clock rate236 * less than or equal to the specified maximum.237 *238 * Returns: calculated prescale value for easy programming into SPI registers239 * or negative error number if valid prescalar cannot be updated.240 */241static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,242 u32 max_speed_hz)243{244 int ret;245 246 /* Subtract 1 to match what will be programmed into SPI register. */247 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;248 249 if (ret < dspi->prescaler_limit || ret > 255)250 return -EINVAL;251 252 return ret;253}254 255/**256 * davinci_spi_setup_transfer - This functions will determine transfer method257 * @spi: spi device on which data transfer to be done258 * @t: spi transfer in which transfer info is filled259 *260 * This function determines data transfer method (8/16/32 bit transfer).261 * It will also set the SPI Clock Control register according to262 * SPI slave device freq.263 */264static int davinci_spi_setup_transfer(struct spi_device *spi,265 struct spi_transfer *t)266{267 268 struct davinci_spi *dspi;269 struct davinci_spi_config *spicfg;270 u8 bits_per_word = 0;271 u32 hz = 0, spifmt = 0;272 int prescale;273 274 dspi = spi_controller_get_devdata(spi->controller);275 spicfg = spi->controller_data;276 if (!spicfg)277 spicfg = &davinci_spi_default_cfg;278 279 if (t) {280 bits_per_word = t->bits_per_word;281 hz = t->speed_hz;282 }283 284 /* if bits_per_word is not set then set it default */285 if (!bits_per_word)286 bits_per_word = spi->bits_per_word;287 288 /*289 * Assign function pointer to appropriate transfer method290 * 8bit, 16bit or 32bit transfer291 */292 if (bits_per_word <= 8) {293 dspi->get_rx = davinci_spi_rx_buf_u8;294 dspi->get_tx = davinci_spi_tx_buf_u8;295 dspi->bytes_per_word[spi_get_chipselect(spi, 0)] = 1;296 } else {297 dspi->get_rx = davinci_spi_rx_buf_u16;298 dspi->get_tx = davinci_spi_tx_buf_u16;299 dspi->bytes_per_word[spi_get_chipselect(spi, 0)] = 2;300 }301 302 if (!hz)303 hz = spi->max_speed_hz;304 305 /* Set up SPIFMTn register, unique to this chipselect. */306 307 prescale = davinci_spi_get_prescale(dspi, hz);308 if (prescale < 0)309 return prescale;310 311 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);312 313 if (spi->mode & SPI_LSB_FIRST)314 spifmt |= SPIFMT_SHIFTDIR_MASK;315 316 if (spi->mode & SPI_CPOL)317 spifmt |= SPIFMT_POLARITY_MASK;318 319 if (!(spi->mode & SPI_CPHA))320 spifmt |= SPIFMT_PHASE_MASK;321 322 /*323 * Assume wdelay is used only on SPI peripherals that has this field324 * in SPIFMTn register and when it's configured from board file or DT.325 */326 if (spicfg->wdelay)327 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)328 & SPIFMT_WDELAY_MASK);329 330 /*331 * Version 1 hardware supports two basic SPI modes:332 * - Standard SPI mode uses 4 pins, with chipselect333 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)334 * (distinct from SPI_3WIRE, with just one data wire;335 * or similar variants without MOSI or without MISO)336 *337 * Version 2 hardware supports an optional handshaking signal,338 * so it can support two more modes:339 * - 5 pin SPI variant is standard SPI plus SPI_READY340 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)341 */342 343 if (dspi->version == SPI_VERSION_2) {344 345 u32 delay = 0;346 347 if (spicfg->odd_parity)348 spifmt |= SPIFMT_ODD_PARITY_MASK;349 350 if (spicfg->parity_enable)351 spifmt |= SPIFMT_PARITYENA_MASK;352 353 if (spicfg->timer_disable) {354 spifmt |= SPIFMT_DISTIMER_MASK;355 } else {356 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)357 & SPIDELAY_C2TDELAY_MASK;358 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)359 & SPIDELAY_T2CDELAY_MASK;360 }361 362 if (spi->mode & SPI_READY) {363 spifmt |= SPIFMT_WAITENA_MASK;364 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)365 & SPIDELAY_T2EDELAY_MASK;366 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)367 & SPIDELAY_C2EDELAY_MASK;368 }369 370 iowrite32(delay, dspi->base + SPIDELAY);371 }372 373 iowrite32(spifmt, dspi->base + SPIFMT0);374 375 return 0;376}377 378static int davinci_spi_of_setup(struct spi_device *spi)379{380 struct davinci_spi_config *spicfg = spi->controller_data;381 struct device_node *np = spi->dev.of_node;382 struct davinci_spi *dspi = spi_controller_get_devdata(spi->controller);383 u32 prop;384 385 if (spicfg == NULL && np) {386 spicfg = kzalloc(sizeof(*spicfg), GFP_KERNEL);387 if (!spicfg)388 return -ENOMEM;389 *spicfg = davinci_spi_default_cfg;390 /* override with dt configured values */391 if (!of_property_read_u32(np, "ti,spi-wdelay", &prop))392 spicfg->wdelay = (u8)prop;393 spi->controller_data = spicfg;394 395 if (dspi->dma_rx && dspi->dma_tx)396 spicfg->io_type = SPI_IO_TYPE_DMA;397 }398 399 return 0;400}401 402/**403 * davinci_spi_setup - This functions will set default transfer method404 * @spi: spi device on which data transfer to be done405 *406 * This functions sets the default transfer method.407 */408static int davinci_spi_setup(struct spi_device *spi)409{410 struct davinci_spi *dspi;411 struct device_node *np = spi->dev.of_node;412 bool internal_cs = true;413 414 dspi = spi_controller_get_devdata(spi->controller);415 416 if (!(spi->mode & SPI_NO_CS)) {417 if (np && spi_get_csgpiod(spi, 0))418 internal_cs = false;419 420 if (internal_cs)421 set_io_bits(dspi->base + SPIPC0, 1 << spi_get_chipselect(spi, 0));422 }423 424 if (spi->mode & SPI_READY)425 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);426 427 if (spi->mode & SPI_LOOP)428 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);429 else430 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);431 432 return davinci_spi_of_setup(spi);433}434 435static void davinci_spi_cleanup(struct spi_device *spi)436{437 struct davinci_spi_config *spicfg = spi->controller_data;438 439 spi->controller_data = NULL;440 if (spi->dev.of_node)441 kfree(spicfg);442}443 444static bool davinci_spi_can_dma(struct spi_controller *host,445 struct spi_device *spi,446 struct spi_transfer *xfer)447{448 struct davinci_spi_config *spicfg = spi->controller_data;449 bool can_dma = false;450 451 if (spicfg)452 can_dma = (spicfg->io_type == SPI_IO_TYPE_DMA) &&453 (xfer->len >= DMA_MIN_BYTES) &&454 !is_vmalloc_addr(xfer->rx_buf) &&455 !is_vmalloc_addr(xfer->tx_buf);456 457 return can_dma;458}459 460static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)461{462 struct device *sdev = dspi->bitbang.ctlr->dev.parent;463 464 if (int_status & SPIFLG_TIMEOUT_MASK) {465 dev_err(sdev, "SPI Time-out Error\n");466 return -ETIMEDOUT;467 }468 if (int_status & SPIFLG_DESYNC_MASK) {469 dev_err(sdev, "SPI Desynchronization Error\n");470 return -EIO;471 }472 if (int_status & SPIFLG_BITERR_MASK) {473 dev_err(sdev, "SPI Bit error\n");474 return -EIO;475 }476 477 if (dspi->version == SPI_VERSION_2) {478 if (int_status & SPIFLG_DLEN_ERR_MASK) {479 dev_err(sdev, "SPI Data Length Error\n");480 return -EIO;481 }482 if (int_status & SPIFLG_PARERR_MASK) {483 dev_err(sdev, "SPI Parity Error\n");484 return -EIO;485 }486 if (int_status & SPIFLG_OVRRUN_MASK) {487 dev_err(sdev, "SPI Data Overrun error\n");488 return -EIO;489 }490 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {491 dev_err(sdev, "SPI Buffer Init Active\n");492 return -EBUSY;493 }494 }495 496 return 0;497}498 499/**500 * davinci_spi_process_events - check for and handle any SPI controller events501 * @dspi: the controller data502 *503 * This function will check the SPIFLG register and handle any events that are504 * detected there505 */506static int davinci_spi_process_events(struct davinci_spi *dspi)507{508 u32 buf, status, errors = 0, spidat1;509 510 buf = ioread32(dspi->base + SPIBUF);511 512 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {513 dspi->get_rx(buf & 0xFFFF, dspi);514 dspi->rcount--;515 }516 517 status = ioread32(dspi->base + SPIFLG);518 519 if (unlikely(status & SPIFLG_ERROR_MASK)) {520 errors = status & SPIFLG_ERROR_MASK;521 goto out;522 }523 524 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {525 spidat1 = ioread32(dspi->base + SPIDAT1);526 dspi->wcount--;527 spidat1 &= ~0xFFFF;528 spidat1 |= 0xFFFF & dspi->get_tx(dspi);529 iowrite32(spidat1, dspi->base + SPIDAT1);530 }531 532out:533 return errors;534}535 536static void davinci_spi_dma_rx_callback(void *data)537{538 struct davinci_spi *dspi = (struct davinci_spi *)data;539 540 dspi->rcount = 0;541 542 if (!dspi->wcount && !dspi->rcount)543 complete(&dspi->done);544}545 546static void davinci_spi_dma_tx_callback(void *data)547{548 struct davinci_spi *dspi = (struct davinci_spi *)data;549 550 dspi->wcount = 0;551 552 if (!dspi->wcount && !dspi->rcount)553 complete(&dspi->done);554}555 556/**557 * davinci_spi_bufs - functions which will handle transfer data558 * @spi: spi device on which data transfer to be done559 * @t: spi transfer in which transfer info is filled560 *561 * This function will put data to be transferred into data register562 * of SPI controller and then wait until the completion will be marked563 * by the IRQ Handler.564 */565static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)566{567 struct davinci_spi *dspi;568 int data_type, ret = -ENOMEM;569 u32 tx_data, spidat1;570 u32 errors = 0;571 struct davinci_spi_config *spicfg;572 struct davinci_spi_platform_data *pdata;573 unsigned long timeout;574 575 dspi = spi_controller_get_devdata(spi->controller);576 pdata = &dspi->pdata;577 spicfg = (struct davinci_spi_config *)spi->controller_data;578 if (!spicfg)579 spicfg = &davinci_spi_default_cfg;580 581 /* convert len to words based on bits_per_word */582 data_type = dspi->bytes_per_word[spi_get_chipselect(spi, 0)];583 584 dspi->tx = t->tx_buf;585 dspi->rx = t->rx_buf;586 dspi->wcount = t->len / data_type;587 dspi->rcount = dspi->wcount;588 589 spidat1 = ioread32(dspi->base + SPIDAT1);590 591 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);592 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);593 594 reinit_completion(&dspi->done);595 596 if (!davinci_spi_can_dma(spi->controller, spi, t)) {597 if (spicfg->io_type != SPI_IO_TYPE_POLL)598 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);599 /* start the transfer */600 dspi->wcount--;601 tx_data = dspi->get_tx(dspi);602 spidat1 &= 0xFFFF0000;603 spidat1 |= tx_data & 0xFFFF;604 iowrite32(spidat1, dspi->base + SPIDAT1);605 } else {606 struct dma_slave_config dma_rx_conf = {607 .direction = DMA_DEV_TO_MEM,608 .src_addr = (unsigned long)dspi->pbase + SPIBUF,609 .src_addr_width = data_type,610 .src_maxburst = 1,611 };612 struct dma_slave_config dma_tx_conf = {613 .direction = DMA_MEM_TO_DEV,614 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,615 .dst_addr_width = data_type,616 .dst_maxburst = 1,617 };618 struct dma_async_tx_descriptor *rxdesc;619 struct dma_async_tx_descriptor *txdesc;620 621 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);622 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);623 624 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,625 t->rx_sg.sgl, t->rx_sg.nents, DMA_DEV_TO_MEM,626 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);627 if (!rxdesc)628 goto err_desc;629 630 if (!t->tx_buf) {631 /* To avoid errors when doing rx-only transfers with632 * many SG entries (> 20), use the rx buffer as the633 * dummy tx buffer so that dma reloads are done at the634 * same time for rx and tx.635 */636 t->tx_sg.sgl = t->rx_sg.sgl;637 t->tx_sg.nents = t->rx_sg.nents;638 }639 640 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,641 t->tx_sg.sgl, t->tx_sg.nents, DMA_MEM_TO_DEV,642 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);643 if (!txdesc)644 goto err_desc;645 646 rxdesc->callback = davinci_spi_dma_rx_callback;647 rxdesc->callback_param = (void *)dspi;648 txdesc->callback = davinci_spi_dma_tx_callback;649 txdesc->callback_param = (void *)dspi;650 651 if (pdata->cshold_bug)652 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);653 654 dmaengine_submit(rxdesc);655 dmaengine_submit(txdesc);656 657 dma_async_issue_pending(dspi->dma_rx);658 dma_async_issue_pending(dspi->dma_tx);659 660 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);661 }662 663 /* Wait for the transfer to complete */664 if (spicfg->io_type != SPI_IO_TYPE_POLL) {665 timeout = DIV_ROUND_UP(t->speed_hz, MSEC_PER_SEC);666 timeout = DIV_ROUND_UP(t->len * 8, timeout);667 /* Assume we are at most 2x slower than the nominal bus speed */668 timeout = 2 * msecs_to_jiffies(timeout);669 670 if (wait_for_completion_timeout(&dspi->done, timeout) == 0)671 errors = SPIFLG_TIMEOUT_MASK;672 } else {673 while (dspi->rcount > 0 || dspi->wcount > 0) {674 errors = davinci_spi_process_events(dspi);675 if (errors)676 break;677 cpu_relax();678 }679 }680 681 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);682 if (davinci_spi_can_dma(spi->controller, spi, t))683 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);684 685 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);686 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);687 688 /*689 * Check for bit error, desync error,parity error,timeout error and690 * receive overflow errors691 */692 if (errors) {693 ret = davinci_spi_check_error(dspi, errors);694 WARN(!ret, "%s: error reported but no error found!\n",695 dev_name(&spi->dev));696 return ret;697 }698 699 if (dspi->rcount != 0 || dspi->wcount != 0) {700 dev_err(&spi->dev, "SPI data transfer error\n");701 return -EIO;702 }703 704 return t->len;705 706err_desc:707 return ret;708}709 710/**711 * dummy_thread_fn - dummy thread function712 * @irq: IRQ number for this SPI Master713 * @data: structure for SPI Master controller davinci_spi714 *715 * This is to satisfy the request_threaded_irq() API so that the irq716 * handler is called in interrupt context.717 */718static irqreturn_t dummy_thread_fn(s32 irq, void *data)719{720 return IRQ_HANDLED;721}722 723/**724 * davinci_spi_irq - Interrupt handler for SPI Master Controller725 * @irq: IRQ number for this SPI Master726 * @data: structure for SPI Master controller davinci_spi727 *728 * ISR will determine that interrupt arrives either for READ or WRITE command.729 * According to command it will do the appropriate action. It will check730 * transfer length and if it is not zero then dispatch transfer command again.731 * If transfer length is zero then it will indicate the COMPLETION so that732 * davinci_spi_bufs function can go ahead.733 */734static irqreturn_t davinci_spi_irq(s32 irq, void *data)735{736 struct davinci_spi *dspi = data;737 int status;738 739 status = davinci_spi_process_events(dspi);740 if (unlikely(status != 0))741 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);742 743 if ((!dspi->rcount && !dspi->wcount) || status)744 complete(&dspi->done);745 746 return IRQ_HANDLED;747}748 749static int davinci_spi_request_dma(struct davinci_spi *dspi)750{751 struct device *sdev = dspi->bitbang.ctlr->dev.parent;752 753 dspi->dma_rx = dma_request_chan(sdev, "rx");754 if (IS_ERR(dspi->dma_rx))755 return PTR_ERR(dspi->dma_rx);756 757 dspi->dma_tx = dma_request_chan(sdev, "tx");758 if (IS_ERR(dspi->dma_tx)) {759 dma_release_channel(dspi->dma_rx);760 return PTR_ERR(dspi->dma_tx);761 }762 763 return 0;764}765 766#if defined(CONFIG_OF)767 768/* OF SPI data structure */769struct davinci_spi_of_data {770 u8 version;771 u8 prescaler_limit;772};773 774static const struct davinci_spi_of_data dm6441_spi_data = {775 .version = SPI_VERSION_1,776 .prescaler_limit = 2,777};778 779static const struct davinci_spi_of_data da830_spi_data = {780 .version = SPI_VERSION_2,781 .prescaler_limit = 2,782};783 784static const struct davinci_spi_of_data keystone_spi_data = {785 .version = SPI_VERSION_1,786 .prescaler_limit = 0,787};788 789static const struct of_device_id davinci_spi_of_match[] = {790 {791 .compatible = "ti,dm6441-spi",792 .data = &dm6441_spi_data,793 },794 {795 .compatible = "ti,da830-spi",796 .data = &da830_spi_data,797 },798 {799 .compatible = "ti,keystone-spi",800 .data = &keystone_spi_data,801 },802 { },803};804MODULE_DEVICE_TABLE(of, davinci_spi_of_match);805 806/**807 * spi_davinci_get_pdata - Get platform data from DTS binding808 * @pdev: ptr to platform data809 * @dspi: ptr to driver data810 *811 * Parses and populates pdata in dspi from device tree bindings.812 *813 * NOTE: Not all platform data params are supported currently.814 */815static int spi_davinci_get_pdata(struct platform_device *pdev,816 struct davinci_spi *dspi)817{818 struct device_node *node = pdev->dev.of_node;819 const struct davinci_spi_of_data *spi_data;820 struct davinci_spi_platform_data *pdata;821 unsigned int num_cs, intr_line = 0;822 823 pdata = &dspi->pdata;824 825 spi_data = device_get_match_data(&pdev->dev);826 827 pdata->version = spi_data->version;828 pdata->prescaler_limit = spi_data->prescaler_limit;829 /*830 * default num_cs is 1 and all chipsel are internal to the chip831 * indicated by chip_sel being NULL or cs_gpios being NULL or832 * set to -ENOENT. num-cs includes internal as well as gpios.833 * indicated by chip_sel being NULL. GPIO based CS is not834 * supported yet in DT bindings.835 */836 num_cs = 1;837 of_property_read_u32(node, "num-cs", &num_cs);838 pdata->num_chipselect = num_cs;839 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);840 pdata->intr_line = intr_line;841 return 0;842}843#else844static int spi_davinci_get_pdata(struct platform_device *pdev,845 struct davinci_spi *dspi)846{847 return -ENODEV;848}849#endif850 851/**852 * davinci_spi_probe - probe function for SPI Master Controller853 * @pdev: platform_device structure which contains plateform specific data854 *855 * According to Linux Device Model this function will be invoked by Linux856 * with platform_device struct which contains the device specific info.857 * This function will map the SPI controller's memory, register IRQ,858 * Reset SPI controller and setting its registers to default value.859 * It will invoke spi_bitbang_start to create work queue so that client driver860 * can register transfer method to work queue.861 */862static int davinci_spi_probe(struct platform_device *pdev)863{864 struct spi_controller *host;865 struct davinci_spi *dspi;866 struct davinci_spi_platform_data *pdata;867 struct resource *r;868 int ret = 0;869 u32 spipc0;870 871 host = spi_alloc_host(&pdev->dev, sizeof(struct davinci_spi));872 if (host == NULL) {873 ret = -ENOMEM;874 goto err;875 }876 877 platform_set_drvdata(pdev, host);878 879 dspi = spi_controller_get_devdata(host);880 881 if (dev_get_platdata(&pdev->dev)) {882 pdata = dev_get_platdata(&pdev->dev);883 dspi->pdata = *pdata;884 } else {885 /* update dspi pdata with that from the DT */886 ret = spi_davinci_get_pdata(pdev, dspi);887 if (ret < 0)888 goto free_host;889 }890 891 /* pdata in dspi is now updated and point pdata to that */892 pdata = &dspi->pdata;893 894 dspi->bytes_per_word = devm_kcalloc(&pdev->dev,895 pdata->num_chipselect,896 sizeof(*dspi->bytes_per_word),897 GFP_KERNEL);898 if (dspi->bytes_per_word == NULL) {899 ret = -ENOMEM;900 goto free_host;901 }902 903 dspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);904 if (IS_ERR(dspi->base)) {905 ret = PTR_ERR(dspi->base);906 goto free_host;907 }908 dspi->pbase = r->start;909 910 init_completion(&dspi->done);911 912 ret = platform_get_irq(pdev, 0);913 if (ret < 0)914 goto free_host;915 dspi->irq = ret;916 917 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,918 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);919 if (ret)920 goto free_host;921 922 dspi->bitbang.ctlr = host;923 924 dspi->clk = devm_clk_get_enabled(&pdev->dev, NULL);925 if (IS_ERR(dspi->clk)) {926 ret = -ENODEV;927 goto free_host;928 }929 930 host->use_gpio_descriptors = true;931 host->dev.of_node = pdev->dev.of_node;932 host->bus_num = pdev->id;933 host->num_chipselect = pdata->num_chipselect;934 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);935 host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_GPIO_SS;936 host->setup = davinci_spi_setup;937 host->cleanup = davinci_spi_cleanup;938 host->can_dma = davinci_spi_can_dma;939 940 dspi->bitbang.chipselect = davinci_spi_chipselect;941 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;942 dspi->prescaler_limit = pdata->prescaler_limit;943 dspi->version = pdata->version;944 945 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_WORD;946 if (dspi->version == SPI_VERSION_2)947 dspi->bitbang.flags |= SPI_READY;948 949 dspi->bitbang.txrx_bufs = davinci_spi_bufs;950 951 ret = davinci_spi_request_dma(dspi);952 if (ret == -EPROBE_DEFER) {953 goto free_host;954 } else if (ret) {955 dev_info(&pdev->dev, "DMA is not supported (%d)\n", ret);956 dspi->dma_rx = NULL;957 dspi->dma_tx = NULL;958 }959 960 dspi->get_rx = davinci_spi_rx_buf_u8;961 dspi->get_tx = davinci_spi_tx_buf_u8;962 963 /* Reset In/OUT SPI module */964 iowrite32(0, dspi->base + SPIGCR0);965 udelay(100);966 iowrite32(1, dspi->base + SPIGCR0);967 968 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */969 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;970 iowrite32(spipc0, dspi->base + SPIPC0);971 972 if (pdata->intr_line)973 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);974 else975 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);976 977 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);978 979 /* host mode default */980 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);981 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);982 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);983 984 ret = spi_bitbang_start(&dspi->bitbang);985 if (ret)986 goto free_dma;987 988 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);989 990 return ret;991 992free_dma:993 /* This bit needs to be cleared to disable dpsi->clk */994 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);995 996 if (dspi->dma_rx) {997 dma_release_channel(dspi->dma_rx);998 dma_release_channel(dspi->dma_tx);999 }1000free_host:1001 spi_controller_put(host);1002err:1003 return ret;1004}1005 1006/**1007 * davinci_spi_remove - remove function for SPI Master Controller1008 * @pdev: platform_device structure which contains plateform specific data1009 *1010 * This function will do the reverse action of davinci_spi_probe function1011 * It will free the IRQ and SPI controller's memory region.1012 * It will also call spi_bitbang_stop to destroy the work queue which was1013 * created by spi_bitbang_start.1014 */1015static void davinci_spi_remove(struct platform_device *pdev)1016{1017 struct davinci_spi *dspi;1018 struct spi_controller *host;1019 1020 host = platform_get_drvdata(pdev);1021 dspi = spi_controller_get_devdata(host);1022 1023 spi_bitbang_stop(&dspi->bitbang);1024 1025 /* This bit needs to be cleared to disable dpsi->clk */1026 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);1027 1028 if (dspi->dma_rx) {1029 dma_release_channel(dspi->dma_rx);1030 dma_release_channel(dspi->dma_tx);1031 }1032 1033 spi_controller_put(host);1034}1035 1036static struct platform_driver davinci_spi_driver = {1037 .driver = {1038 .name = "spi_davinci",1039 .of_match_table = of_match_ptr(davinci_spi_of_match),1040 },1041 .probe = davinci_spi_probe,1042 .remove_new = davinci_spi_remove,1043};1044module_platform_driver(davinci_spi_driver);1045 1046MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");1047MODULE_LICENSE("GPL");1048