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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Intel PCH/PCU SPI flash driver.4 *5 * Copyright (C) 2016 - 2022, Intel Corporation6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>7 */8 9#include <linux/iopoll.h>10#include <linux/module.h>11 12#include <linux/mtd/partitions.h>13#include <linux/mtd/spi-nor.h>14 15#include <linux/spi/flash.h>16#include <linux/spi/spi.h>17#include <linux/spi/spi-mem.h>18 19#include "spi-intel.h"20 21/* Offsets are from @ispi->base */22#define BFPREG 0x0023 24#define HSFSTS_CTL 0x0425#define HSFSTS_CTL_FSMIE BIT(31)26#define HSFSTS_CTL_FDBC_SHIFT 2427#define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT)28 29#define HSFSTS_CTL_FCYCLE_SHIFT 1730#define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)31/* HW sequencer opcodes */32#define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)33#define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)34#define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)35#define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)36#define HSFSTS_CTL_FCYCLE_RDSFDP (0x05 << HSFSTS_CTL_FCYCLE_SHIFT)37#define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)38#define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)39#define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)40 41#define HSFSTS_CTL_FGO BIT(16)42#define HSFSTS_CTL_FLOCKDN BIT(15)43#define HSFSTS_CTL_FDV BIT(14)44#define HSFSTS_CTL_SCIP BIT(5)45#define HSFSTS_CTL_AEL BIT(2)46#define HSFSTS_CTL_FCERR BIT(1)47#define HSFSTS_CTL_FDONE BIT(0)48 49#define FADDR 0x0850#define DLOCK 0x0c51#define FDATA(n) (0x10 + ((n) * 4))52 53#define FRACC 0x5054 55#define FREG(n) (0x54 + ((n) * 4))56#define FREG_BASE_MASK GENMASK(14, 0)57#define FREG_LIMIT_SHIFT 1658#define FREG_LIMIT_MASK GENMASK(30, 16)59 60/* Offset is from @ispi->pregs */61#define PR(n) ((n) * 4)62#define PR_WPE BIT(31)63#define PR_LIMIT_SHIFT 1664#define PR_LIMIT_MASK GENMASK(30, 16)65#define PR_RPE BIT(15)66#define PR_BASE_MASK GENMASK(14, 0)67 68/* Offsets are from @ispi->sregs */69#define SSFSTS_CTL 0x0070#define SSFSTS_CTL_FSMIE BIT(23)71#define SSFSTS_CTL_DS BIT(22)72#define SSFSTS_CTL_DBC_SHIFT 1673#define SSFSTS_CTL_SPOP BIT(11)74#define SSFSTS_CTL_ACS BIT(10)75#define SSFSTS_CTL_SCGO BIT(9)76#define SSFSTS_CTL_COP_SHIFT 1277#define SSFSTS_CTL_FRS BIT(7)78#define SSFSTS_CTL_DOFRS BIT(6)79#define SSFSTS_CTL_AEL BIT(4)80#define SSFSTS_CTL_FCERR BIT(3)81#define SSFSTS_CTL_FDONE BIT(2)82#define SSFSTS_CTL_SCIP BIT(0)83 84#define PREOP_OPTYPE 0x0485#define OPMENU0 0x0886#define OPMENU1 0x0c87 88#define OPTYPE_READ_NO_ADDR 089#define OPTYPE_WRITE_NO_ADDR 190#define OPTYPE_READ_WITH_ADDR 291#define OPTYPE_WRITE_WITH_ADDR 392 93/* CPU specifics */94#define BYT_PR 0x7495#define BYT_SSFSTS_CTL 0x9096#define BYT_FREG_NUM 597#define BYT_PR_NUM 598 99#define LPT_PR 0x74100#define LPT_SSFSTS_CTL 0x90101#define LPT_FREG_NUM 5102#define LPT_PR_NUM 5103 104#define BXT_PR 0x84105#define BXT_SSFSTS_CTL 0xa0106#define BXT_FREG_NUM 12107#define BXT_PR_NUM 5108 109#define CNL_PR 0x84110#define CNL_FREG_NUM 6111#define CNL_PR_NUM 5112 113#define LVSCC 0xc4114#define UVSCC 0xc8115#define ERASE_OPCODE_SHIFT 8116#define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)117#define ERASE_64K_OPCODE_SHIFT 16118#define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT)119 120/* Flash descriptor fields */121#define FLVALSIG_MAGIC 0x0ff0a55a122#define FLMAP0_NC_MASK GENMASK(9, 8)123#define FLMAP0_NC_SHIFT 8124#define FLMAP0_FCBA_MASK GENMASK(7, 0)125 126#define FLCOMP_C0DEN_MASK GENMASK(3, 0)127#define FLCOMP_C0DEN_512K 0x00128#define FLCOMP_C0DEN_1M 0x01129#define FLCOMP_C0DEN_2M 0x02130#define FLCOMP_C0DEN_4M 0x03131#define FLCOMP_C0DEN_8M 0x04132#define FLCOMP_C0DEN_16M 0x05133#define FLCOMP_C0DEN_32M 0x06134#define FLCOMP_C0DEN_64M 0x07135 136#define INTEL_SPI_TIMEOUT 5000 /* ms */137#define INTEL_SPI_FIFO_SZ 64138 139/**140 * struct intel_spi - Driver private data141 * @dev: Device pointer142 * @info: Pointer to board specific info143 * @base: Beginning of MMIO space144 * @pregs: Start of protection registers145 * @sregs: Start of software sequencer registers146 * @host: Pointer to the SPI controller structure147 * @nregions: Maximum number of regions148 * @pr_num: Maximum number of protected range registers149 * @chip0_size: Size of the first flash chip in bytes150 * @locked: Is SPI setting locked151 * @swseq_reg: Use SW sequencer in register reads/writes152 * @swseq_erase: Use SW sequencer in erase operation153 * @atomic_preopcode: Holds preopcode when atomic sequence is requested154 * @opcodes: Opcodes which are supported. This are programmed by BIOS155 * before it locks down the controller.156 * @mem_ops: Pointer to SPI MEM ops supported by the controller157 */158struct intel_spi {159 struct device *dev;160 const struct intel_spi_boardinfo *info;161 void __iomem *base;162 void __iomem *pregs;163 void __iomem *sregs;164 struct spi_controller *host;165 size_t nregions;166 size_t pr_num;167 size_t chip0_size;168 bool locked;169 bool swseq_reg;170 bool swseq_erase;171 u8 atomic_preopcode;172 u8 opcodes[8];173 const struct intel_spi_mem_op *mem_ops;174};175 176struct intel_spi_mem_op {177 struct spi_mem_op mem_op;178 u32 replacement_op;179 int (*exec_op)(struct intel_spi *ispi,180 const struct spi_mem *mem,181 const struct intel_spi_mem_op *iop,182 const struct spi_mem_op *op);183};184 185static bool writeable;186module_param(writeable, bool, 0);187MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");188 189static void intel_spi_dump_regs(struct intel_spi *ispi)190{191 u32 value;192 int i;193 194 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));195 196 value = readl(ispi->base + HSFSTS_CTL);197 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);198 if (value & HSFSTS_CTL_FLOCKDN)199 dev_dbg(ispi->dev, "-> Locked\n");200 201 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));202 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));203 204 for (i = 0; i < 16; i++)205 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",206 i, readl(ispi->base + FDATA(i)));207 208 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));209 210 for (i = 0; i < ispi->nregions; i++)211 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,212 readl(ispi->base + FREG(i)));213 for (i = 0; i < ispi->pr_num; i++)214 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,215 readl(ispi->pregs + PR(i)));216 217 if (ispi->sregs) {218 value = readl(ispi->sregs + SSFSTS_CTL);219 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);220 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",221 readl(ispi->sregs + PREOP_OPTYPE));222 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",223 readl(ispi->sregs + OPMENU0));224 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",225 readl(ispi->sregs + OPMENU1));226 }227 228 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));229 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));230 231 dev_dbg(ispi->dev, "Protected regions:\n");232 for (i = 0; i < ispi->pr_num; i++) {233 u32 base, limit;234 235 value = readl(ispi->pregs + PR(i));236 if (!(value & (PR_WPE | PR_RPE)))237 continue;238 239 limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;240 base = value & PR_BASE_MASK;241 242 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",243 i, base << 12, (limit << 12) | 0xfff,244 value & PR_WPE ? 'W' : '.', value & PR_RPE ? 'R' : '.');245 }246 247 dev_dbg(ispi->dev, "Flash regions:\n");248 for (i = 0; i < ispi->nregions; i++) {249 u32 region, base, limit;250 251 region = readl(ispi->base + FREG(i));252 base = region & FREG_BASE_MASK;253 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;254 255 if (base >= limit || (i > 0 && limit == 0))256 dev_dbg(ispi->dev, " %02d disabled\n", i);257 else258 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",259 i, base << 12, (limit << 12) | 0xfff);260 }261 262 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",263 ispi->swseq_reg ? 'S' : 'H');264 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",265 ispi->swseq_erase ? 'S' : 'H');266}267 268/* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */269static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)270{271 size_t bytes;272 int i = 0;273 274 if (size > INTEL_SPI_FIFO_SZ)275 return -EINVAL;276 277 while (size > 0) {278 bytes = min_t(size_t, size, 4);279 memcpy_fromio(buf, ispi->base + FDATA(i), bytes);280 size -= bytes;281 buf += bytes;282 i++;283 }284 285 return 0;286}287 288/* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */289static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,290 size_t size)291{292 size_t bytes;293 int i = 0;294 295 if (size > INTEL_SPI_FIFO_SZ)296 return -EINVAL;297 298 while (size > 0) {299 bytes = min_t(size_t, size, 4);300 memcpy_toio(ispi->base + FDATA(i), buf, bytes);301 size -= bytes;302 buf += bytes;303 i++;304 }305 306 return 0;307}308 309static int intel_spi_wait_hw_busy(struct intel_spi *ispi)310{311 u32 val;312 313 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,314 !(val & HSFSTS_CTL_SCIP), 0,315 INTEL_SPI_TIMEOUT * 1000);316}317 318static int intel_spi_wait_sw_busy(struct intel_spi *ispi)319{320 u32 val;321 322 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,323 !(val & SSFSTS_CTL_SCIP), 0,324 INTEL_SPI_TIMEOUT * 1000);325}326 327static bool intel_spi_set_writeable(struct intel_spi *ispi)328{329 if (!ispi->info->set_writeable)330 return false;331 332 return ispi->info->set_writeable(ispi->base, ispi->info->data);333}334 335static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)336{337 int i;338 int preop;339 340 if (ispi->locked) {341 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)342 if (ispi->opcodes[i] == opcode)343 return i;344 345 return -EINVAL;346 }347 348 /* The lock is off, so just use index 0 */349 writel(opcode, ispi->sregs + OPMENU0);350 preop = readw(ispi->sregs + PREOP_OPTYPE);351 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);352 353 return 0;354}355 356static int intel_spi_hw_cycle(struct intel_spi *ispi,357 const struct intel_spi_mem_op *iop, size_t len)358{359 u32 val, status;360 int ret;361 362 if (!iop->replacement_op)363 return -EINVAL;364 365 val = readl(ispi->base + HSFSTS_CTL);366 val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);367 val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;368 val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;369 val |= HSFSTS_CTL_FGO;370 val |= iop->replacement_op;371 writel(val, ispi->base + HSFSTS_CTL);372 373 ret = intel_spi_wait_hw_busy(ispi);374 if (ret)375 return ret;376 377 status = readl(ispi->base + HSFSTS_CTL);378 if (status & HSFSTS_CTL_FCERR)379 return -EIO;380 else if (status & HSFSTS_CTL_AEL)381 return -EACCES;382 383 return 0;384}385 386static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len,387 int optype)388{389 u32 val = 0, status;390 u8 atomic_preopcode;391 int ret;392 393 ret = intel_spi_opcode_index(ispi, opcode, optype);394 if (ret < 0)395 return ret;396 397 /*398 * Always clear it after each SW sequencer operation regardless399 * of whether it is successful or not.400 */401 atomic_preopcode = ispi->atomic_preopcode;402 ispi->atomic_preopcode = 0;403 404 /* Only mark 'Data Cycle' bit when there is data to be transferred */405 if (len > 0)406 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;407 val |= ret << SSFSTS_CTL_COP_SHIFT;408 val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;409 val |= SSFSTS_CTL_SCGO;410 if (atomic_preopcode) {411 u16 preop;412 413 switch (optype) {414 case OPTYPE_WRITE_NO_ADDR:415 case OPTYPE_WRITE_WITH_ADDR:416 /* Pick matching preopcode for the atomic sequence */417 preop = readw(ispi->sregs + PREOP_OPTYPE);418 if ((preop & 0xff) == atomic_preopcode)419 ; /* Do nothing */420 else if ((preop >> 8) == atomic_preopcode)421 val |= SSFSTS_CTL_SPOP;422 else423 return -EINVAL;424 425 /* Enable atomic sequence */426 val |= SSFSTS_CTL_ACS;427 break;428 429 default:430 return -EINVAL;431 }432 }433 writel(val, ispi->sregs + SSFSTS_CTL);434 435 ret = intel_spi_wait_sw_busy(ispi);436 if (ret)437 return ret;438 439 status = readl(ispi->sregs + SSFSTS_CTL);440 if (status & SSFSTS_CTL_FCERR)441 return -EIO;442 else if (status & SSFSTS_CTL_AEL)443 return -EACCES;444 445 return 0;446}447 448static u32 intel_spi_chip_addr(const struct intel_spi *ispi,449 const struct spi_mem *mem)450{451 /* Pick up the correct start address */452 if (!mem)453 return 0;454 return (spi_get_chipselect(mem->spi, 0) == 1) ? ispi->chip0_size : 0;455}456 457static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem,458 const struct intel_spi_mem_op *iop,459 const struct spi_mem_op *op)460{461 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;462 size_t nbytes = op->data.nbytes;463 u8 opcode = op->cmd.opcode;464 int ret;465 466 writel(addr, ispi->base + FADDR);467 468 if (ispi->swseq_reg)469 ret = intel_spi_sw_cycle(ispi, opcode, nbytes,470 OPTYPE_READ_NO_ADDR);471 else472 ret = intel_spi_hw_cycle(ispi, iop, nbytes);473 474 if (ret)475 return ret;476 477 return intel_spi_read_block(ispi, op->data.buf.in, nbytes);478}479 480static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem,481 const struct intel_spi_mem_op *iop,482 const struct spi_mem_op *op)483{484 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;485 size_t nbytes = op->data.nbytes;486 u8 opcode = op->cmd.opcode;487 int ret;488 489 /*490 * This is handled with atomic operation and preop code in Intel491 * controller so we only verify that it is available. If the492 * controller is not locked, program the opcode to the PREOP493 * register for later use.494 *495 * When hardware sequencer is used there is no need to program496 * any opcodes (it handles them automatically as part of a command).497 */498 if (opcode == SPINOR_OP_WREN) {499 u16 preop;500 501 if (!ispi->swseq_reg)502 return 0;503 504 preop = readw(ispi->sregs + PREOP_OPTYPE);505 if ((preop & 0xff) != opcode && (preop >> 8) != opcode) {506 if (ispi->locked)507 return -EINVAL;508 writel(opcode, ispi->sregs + PREOP_OPTYPE);509 }510 511 /*512 * This enables atomic sequence on next SW sycle. Will513 * be cleared after next operation.514 */515 ispi->atomic_preopcode = opcode;516 return 0;517 }518 519 /*520 * We hope that HW sequencer will do the right thing automatically and521 * with the SW sequencer we cannot use preopcode anyway, so just ignore522 * the Write Disable operation and pretend it was completed523 * successfully.524 */525 if (opcode == SPINOR_OP_WRDI)526 return 0;527 528 writel(addr, ispi->base + FADDR);529 530 /* Write the value beforehand */531 ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes);532 if (ret)533 return ret;534 535 if (ispi->swseq_reg)536 return intel_spi_sw_cycle(ispi, opcode, nbytes,537 OPTYPE_WRITE_NO_ADDR);538 return intel_spi_hw_cycle(ispi, iop, nbytes);539}540 541static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem,542 const struct intel_spi_mem_op *iop,543 const struct spi_mem_op *op)544{545 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;546 size_t block_size, nbytes = op->data.nbytes;547 void *read_buf = op->data.buf.in;548 u32 val, status;549 int ret;550 551 /*552 * Atomic sequence is not expected with HW sequencer reads. Make553 * sure it is cleared regardless.554 */555 if (WARN_ON_ONCE(ispi->atomic_preopcode))556 ispi->atomic_preopcode = 0;557 558 while (nbytes > 0) {559 block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ);560 561 /* Read cannot cross 4K boundary */562 block_size = min_t(loff_t, addr + block_size,563 round_up(addr + 1, SZ_4K)) - addr;564 565 writel(addr, ispi->base + FADDR);566 567 val = readl(ispi->base + HSFSTS_CTL);568 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);569 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;570 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;571 val |= HSFSTS_CTL_FCYCLE_READ;572 val |= HSFSTS_CTL_FGO;573 writel(val, ispi->base + HSFSTS_CTL);574 575 ret = intel_spi_wait_hw_busy(ispi);576 if (ret)577 return ret;578 579 status = readl(ispi->base + HSFSTS_CTL);580 if (status & HSFSTS_CTL_FCERR)581 ret = -EIO;582 else if (status & HSFSTS_CTL_AEL)583 ret = -EACCES;584 585 if (ret < 0) {586 dev_err(ispi->dev, "read error: %x: %#x\n", addr, status);587 return ret;588 }589 590 ret = intel_spi_read_block(ispi, read_buf, block_size);591 if (ret)592 return ret;593 594 nbytes -= block_size;595 addr += block_size;596 read_buf += block_size;597 }598 599 return 0;600}601 602static int intel_spi_write(struct intel_spi *ispi, const struct spi_mem *mem,603 const struct intel_spi_mem_op *iop,604 const struct spi_mem_op *op)605{606 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;607 size_t block_size, nbytes = op->data.nbytes;608 const void *write_buf = op->data.buf.out;609 u32 val, status;610 int ret;611 612 /* Not needed with HW sequencer write, make sure it is cleared */613 ispi->atomic_preopcode = 0;614 615 while (nbytes > 0) {616 block_size = min_t(size_t, nbytes, INTEL_SPI_FIFO_SZ);617 618 /* Write cannot cross 4K boundary */619 block_size = min_t(loff_t, addr + block_size,620 round_up(addr + 1, SZ_4K)) - addr;621 622 writel(addr, ispi->base + FADDR);623 624 val = readl(ispi->base + HSFSTS_CTL);625 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);626 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;627 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;628 val |= HSFSTS_CTL_FCYCLE_WRITE;629 630 ret = intel_spi_write_block(ispi, write_buf, block_size);631 if (ret) {632 dev_err(ispi->dev, "failed to write block\n");633 return ret;634 }635 636 /* Start the write now */637 val |= HSFSTS_CTL_FGO;638 writel(val, ispi->base + HSFSTS_CTL);639 640 ret = intel_spi_wait_hw_busy(ispi);641 if (ret) {642 dev_err(ispi->dev, "timeout\n");643 return ret;644 }645 646 status = readl(ispi->base + HSFSTS_CTL);647 if (status & HSFSTS_CTL_FCERR)648 ret = -EIO;649 else if (status & HSFSTS_CTL_AEL)650 ret = -EACCES;651 652 if (ret < 0) {653 dev_err(ispi->dev, "write error: %x: %#x\n", addr, status);654 return ret;655 }656 657 nbytes -= block_size;658 addr += block_size;659 write_buf += block_size;660 }661 662 return 0;663}664 665static int intel_spi_erase(struct intel_spi *ispi, const struct spi_mem *mem,666 const struct intel_spi_mem_op *iop,667 const struct spi_mem_op *op)668{669 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;670 u8 opcode = op->cmd.opcode;671 u32 val, status;672 int ret;673 674 writel(addr, ispi->base + FADDR);675 676 if (ispi->swseq_erase)677 return intel_spi_sw_cycle(ispi, opcode, 0,678 OPTYPE_WRITE_WITH_ADDR);679 680 /* Not needed with HW sequencer erase, make sure it is cleared */681 ispi->atomic_preopcode = 0;682 683 val = readl(ispi->base + HSFSTS_CTL);684 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);685 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;686 val |= HSFSTS_CTL_FGO;687 val |= iop->replacement_op;688 writel(val, ispi->base + HSFSTS_CTL);689 690 ret = intel_spi_wait_hw_busy(ispi);691 if (ret)692 return ret;693 694 status = readl(ispi->base + HSFSTS_CTL);695 if (status & HSFSTS_CTL_FCERR)696 return -EIO;697 if (status & HSFSTS_CTL_AEL)698 return -EACCES;699 700 return 0;701}702 703static int intel_spi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)704{705 op->data.nbytes = clamp_val(op->data.nbytes, 0, INTEL_SPI_FIFO_SZ);706 return 0;707}708 709static bool intel_spi_cmp_mem_op(const struct intel_spi_mem_op *iop,710 const struct spi_mem_op *op)711{712 if (iop->mem_op.cmd.nbytes != op->cmd.nbytes ||713 iop->mem_op.cmd.buswidth != op->cmd.buswidth ||714 iop->mem_op.cmd.dtr != op->cmd.dtr)715 return false;716 717 if (iop->mem_op.addr.nbytes != op->addr.nbytes ||718 iop->mem_op.addr.dtr != op->addr.dtr)719 return false;720 721 if (iop->mem_op.data.dir != op->data.dir ||722 iop->mem_op.data.dtr != op->data.dtr)723 return false;724 725 if (iop->mem_op.data.dir != SPI_MEM_NO_DATA) {726 if (iop->mem_op.data.buswidth != op->data.buswidth)727 return false;728 }729 730 return true;731}732 733static const struct intel_spi_mem_op *734intel_spi_match_mem_op(struct intel_spi *ispi, const struct spi_mem_op *op)735{736 const struct intel_spi_mem_op *iop;737 738 for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) {739 if (iop->mem_op.cmd.opcode == op->cmd.opcode &&740 intel_spi_cmp_mem_op(iop, op))741 return iop;742 }743 744 return NULL;745}746 747static bool intel_spi_supports_mem_op(struct spi_mem *mem,748 const struct spi_mem_op *op)749{750 struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);751 const struct intel_spi_mem_op *iop;752 753 iop = intel_spi_match_mem_op(ispi, op);754 if (!iop) {755 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);756 return false;757 }758 759 /*760 * For software sequencer check that the opcode is actually761 * present in the opmenu if it is locked.762 */763 if (ispi->swseq_reg && ispi->locked) {764 int i;765 766 /* Check if it is in the locked opcodes list */767 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) {768 if (ispi->opcodes[i] == op->cmd.opcode)769 return true;770 }771 772 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);773 return false;774 }775 776 return true;777}778 779static int intel_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)780{781 struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);782 const struct intel_spi_mem_op *iop;783 784 iop = intel_spi_match_mem_op(ispi, op);785 if (!iop)786 return -EOPNOTSUPP;787 788 return iop->exec_op(ispi, mem, iop, op);789}790 791static const char *intel_spi_get_name(struct spi_mem *mem)792{793 const struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);794 795 /*796 * Return name of the flash controller device to be compatible797 * with the MTD version.798 */799 return dev_name(ispi->dev);800}801 802static int intel_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)803{804 struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);805 const struct intel_spi_mem_op *iop;806 807 iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl);808 if (!iop)809 return -EOPNOTSUPP;810 811 desc->priv = (void *)iop;812 return 0;813}814 815static ssize_t intel_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs,816 size_t len, void *buf)817{818 struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);819 const struct intel_spi_mem_op *iop = desc->priv;820 struct spi_mem_op op = desc->info.op_tmpl;821 int ret;822 823 /* Fill in the gaps */824 op.addr.val = offs;825 op.data.nbytes = len;826 op.data.buf.in = buf;827 828 ret = iop->exec_op(ispi, desc->mem, iop, &op);829 return ret ? ret : len;830}831 832static ssize_t intel_spi_dirmap_write(struct spi_mem_dirmap_desc *desc, u64 offs,833 size_t len, const void *buf)834{835 struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);836 const struct intel_spi_mem_op *iop = desc->priv;837 struct spi_mem_op op = desc->info.op_tmpl;838 int ret;839 840 op.addr.val = offs;841 op.data.nbytes = len;842 op.data.buf.out = buf;843 844 ret = iop->exec_op(ispi, desc->mem, iop, &op);845 return ret ? ret : len;846}847 848static const struct spi_controller_mem_ops intel_spi_mem_ops = {849 .adjust_op_size = intel_spi_adjust_op_size,850 .supports_op = intel_spi_supports_mem_op,851 .exec_op = intel_spi_exec_mem_op,852 .get_name = intel_spi_get_name,853 .dirmap_create = intel_spi_dirmap_create,854 .dirmap_read = intel_spi_dirmap_read,855 .dirmap_write = intel_spi_dirmap_write,856};857 858#define INTEL_SPI_OP_ADDR(__nbytes) \859 { \860 .nbytes = __nbytes, \861 }862 863#define INTEL_SPI_OP_NO_DATA \864 { \865 .dir = SPI_MEM_NO_DATA, \866 }867 868#define INTEL_SPI_OP_DATA_IN(__buswidth) \869 { \870 .dir = SPI_MEM_DATA_IN, \871 .buswidth = __buswidth, \872 }873 874#define INTEL_SPI_OP_DATA_OUT(__buswidth) \875 { \876 .dir = SPI_MEM_DATA_OUT, \877 .buswidth = __buswidth, \878 }879 880#define INTEL_SPI_MEM_OP(__cmd, __addr, __data, __exec_op) \881 { \882 .mem_op = { \883 .cmd = __cmd, \884 .addr = __addr, \885 .data = __data, \886 }, \887 .exec_op = __exec_op, \888 }889 890#define INTEL_SPI_MEM_OP_REPL(__cmd, __addr, __data, __exec_op, __repl) \891 { \892 .mem_op = { \893 .cmd = __cmd, \894 .addr = __addr, \895 .data = __data, \896 }, \897 .exec_op = __exec_op, \898 .replacement_op = __repl, \899 }900 901/*902 * The controller handles pretty much everything internally based on the903 * SFDP data but we want to make sure we only support the operations904 * actually possible. Only check buswidth and transfer direction, the905 * core validates data.906 */907#define INTEL_SPI_GENERIC_OPS \908 /* Status register operations */ \909 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 1), \910 SPI_MEM_OP_NO_ADDR, \911 INTEL_SPI_OP_DATA_IN(1), \912 intel_spi_read_reg, \913 HSFSTS_CTL_FCYCLE_RDID), \914 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDSR, 1), \915 SPI_MEM_OP_NO_ADDR, \916 INTEL_SPI_OP_DATA_IN(1), \917 intel_spi_read_reg, \918 HSFSTS_CTL_FCYCLE_RDSR), \919 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_WRSR, 1), \920 SPI_MEM_OP_NO_ADDR, \921 INTEL_SPI_OP_DATA_OUT(1), \922 intel_spi_write_reg, \923 HSFSTS_CTL_FCYCLE_WRSR), \924 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_RDSFDP, 1), \925 INTEL_SPI_OP_ADDR(3), \926 INTEL_SPI_OP_DATA_IN(1), \927 intel_spi_read_reg, \928 HSFSTS_CTL_FCYCLE_RDSFDP), \929 /* Normal read */ \930 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \931 INTEL_SPI_OP_ADDR(3), \932 INTEL_SPI_OP_DATA_IN(1), \933 intel_spi_read), \934 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \935 INTEL_SPI_OP_ADDR(3), \936 INTEL_SPI_OP_DATA_IN(2), \937 intel_spi_read), \938 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \939 INTEL_SPI_OP_ADDR(3), \940 INTEL_SPI_OP_DATA_IN(4), \941 intel_spi_read), \942 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \943 INTEL_SPI_OP_ADDR(4), \944 INTEL_SPI_OP_DATA_IN(1), \945 intel_spi_read), \946 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \947 INTEL_SPI_OP_ADDR(4), \948 INTEL_SPI_OP_DATA_IN(2), \949 intel_spi_read), \950 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 1), \951 INTEL_SPI_OP_ADDR(4), \952 INTEL_SPI_OP_DATA_IN(4), \953 intel_spi_read), \954 /* Fast read */ \955 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \956 INTEL_SPI_OP_ADDR(3), \957 INTEL_SPI_OP_DATA_IN(1), \958 intel_spi_read), \959 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \960 INTEL_SPI_OP_ADDR(3), \961 INTEL_SPI_OP_DATA_IN(2), \962 intel_spi_read), \963 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \964 INTEL_SPI_OP_ADDR(3), \965 INTEL_SPI_OP_DATA_IN(4), \966 intel_spi_read), \967 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \968 INTEL_SPI_OP_ADDR(4), \969 INTEL_SPI_OP_DATA_IN(1), \970 intel_spi_read), \971 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \972 INTEL_SPI_OP_ADDR(4), \973 INTEL_SPI_OP_DATA_IN(2), \974 intel_spi_read), \975 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST, 1), \976 INTEL_SPI_OP_ADDR(4), \977 INTEL_SPI_OP_DATA_IN(4), \978 intel_spi_read), \979 /* Read with 4-byte address opcode */ \980 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \981 INTEL_SPI_OP_ADDR(4), \982 INTEL_SPI_OP_DATA_IN(1), \983 intel_spi_read), \984 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \985 INTEL_SPI_OP_ADDR(4), \986 INTEL_SPI_OP_DATA_IN(2), \987 intel_spi_read), \988 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_4B, 1), \989 INTEL_SPI_OP_ADDR(4), \990 INTEL_SPI_OP_DATA_IN(4), \991 intel_spi_read), \992 /* Fast read with 4-byte address opcode */ \993 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \994 INTEL_SPI_OP_ADDR(4), \995 INTEL_SPI_OP_DATA_IN(1), \996 intel_spi_read), \997 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \998 INTEL_SPI_OP_ADDR(4), \999 INTEL_SPI_OP_DATA_IN(2), \1000 intel_spi_read), \1001 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ_FAST_4B, 1), \1002 INTEL_SPI_OP_ADDR(4), \1003 INTEL_SPI_OP_DATA_IN(4), \1004 intel_spi_read), \1005 /* Write operations */ \1006 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \1007 INTEL_SPI_OP_ADDR(3), \1008 INTEL_SPI_OP_DATA_OUT(1), \1009 intel_spi_write), \1010 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP, 1), \1011 INTEL_SPI_OP_ADDR(4), \1012 INTEL_SPI_OP_DATA_OUT(1), \1013 intel_spi_write), \1014 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_PP_4B, 1), \1015 INTEL_SPI_OP_ADDR(4), \1016 INTEL_SPI_OP_DATA_OUT(1), \1017 intel_spi_write), \1018 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WREN, 1), \1019 SPI_MEM_OP_NO_ADDR, \1020 SPI_MEM_OP_NO_DATA, \1021 intel_spi_write_reg), \1022 INTEL_SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRDI, 1), \1023 SPI_MEM_OP_NO_ADDR, \1024 SPI_MEM_OP_NO_DATA, \1025 intel_spi_write_reg), \1026 /* Erase operations */ \1027 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \1028 INTEL_SPI_OP_ADDR(3), \1029 SPI_MEM_OP_NO_DATA, \1030 intel_spi_erase, \1031 HSFSTS_CTL_FCYCLE_ERASE), \1032 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K, 1), \1033 INTEL_SPI_OP_ADDR(4), \1034 SPI_MEM_OP_NO_DATA, \1035 intel_spi_erase, \1036 HSFSTS_CTL_FCYCLE_ERASE), \1037 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_BE_4K_4B, 1), \1038 INTEL_SPI_OP_ADDR(4), \1039 SPI_MEM_OP_NO_DATA, \1040 intel_spi_erase, \1041 HSFSTS_CTL_FCYCLE_ERASE) \1042 1043static const struct intel_spi_mem_op generic_mem_ops[] = {1044 INTEL_SPI_GENERIC_OPS,1045 { },1046};1047 1048static const struct intel_spi_mem_op erase_64k_mem_ops[] = {1049 INTEL_SPI_GENERIC_OPS,1050 /* 64k sector erase operations */1051 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1),1052 INTEL_SPI_OP_ADDR(3),1053 SPI_MEM_OP_NO_DATA,1054 intel_spi_erase,1055 HSFSTS_CTL_FCYCLE_ERASE_64K),1056 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE, 1),1057 INTEL_SPI_OP_ADDR(4),1058 SPI_MEM_OP_NO_DATA,1059 intel_spi_erase,1060 HSFSTS_CTL_FCYCLE_ERASE_64K),1061 INTEL_SPI_MEM_OP_REPL(SPI_MEM_OP_CMD(SPINOR_OP_SE_4B, 1),1062 INTEL_SPI_OP_ADDR(4),1063 SPI_MEM_OP_NO_DATA,1064 intel_spi_erase,1065 HSFSTS_CTL_FCYCLE_ERASE_64K),1066 { },1067};1068 1069static int intel_spi_init(struct intel_spi *ispi)1070{1071 u32 opmenu0, opmenu1, lvscc, uvscc, val;1072 bool erase_64k = false;1073 int i;1074 1075 switch (ispi->info->type) {1076 case INTEL_SPI_BYT:1077 ispi->sregs = ispi->base + BYT_SSFSTS_CTL;1078 ispi->pregs = ispi->base + BYT_PR;1079 ispi->nregions = BYT_FREG_NUM;1080 ispi->pr_num = BYT_PR_NUM;1081 ispi->swseq_reg = true;1082 break;1083 1084 case INTEL_SPI_LPT:1085 ispi->sregs = ispi->base + LPT_SSFSTS_CTL;1086 ispi->pregs = ispi->base + LPT_PR;1087 ispi->nregions = LPT_FREG_NUM;1088 ispi->pr_num = LPT_PR_NUM;1089 ispi->swseq_reg = true;1090 break;1091 1092 case INTEL_SPI_BXT:1093 ispi->sregs = ispi->base + BXT_SSFSTS_CTL;1094 ispi->pregs = ispi->base + BXT_PR;1095 ispi->nregions = BXT_FREG_NUM;1096 ispi->pr_num = BXT_PR_NUM;1097 erase_64k = true;1098 break;1099 1100 case INTEL_SPI_CNL:1101 ispi->sregs = NULL;1102 ispi->pregs = ispi->base + CNL_PR;1103 ispi->nregions = CNL_FREG_NUM;1104 ispi->pr_num = CNL_PR_NUM;1105 erase_64k = true;1106 break;1107 1108 default:1109 return -EINVAL;1110 }1111 1112 /* Try to disable write protection if user asked to do so */1113 if (writeable && !intel_spi_set_writeable(ispi)) {1114 dev_warn(ispi->dev, "can't disable chip write protection\n");1115 writeable = false;1116 }1117 1118 /* Disable #SMI generation from HW sequencer */1119 val = readl(ispi->base + HSFSTS_CTL);1120 val &= ~HSFSTS_CTL_FSMIE;1121 writel(val, ispi->base + HSFSTS_CTL);1122 1123 /*1124 * Determine whether erase operation should use HW or SW sequencer.1125 *1126 * The HW sequencer has a predefined list of opcodes, with only the1127 * erase opcode being programmable in LVSCC and UVSCC registers.1128 * If these registers don't contain a valid erase opcode, erase1129 * cannot be done using HW sequencer.1130 */1131 lvscc = readl(ispi->base + LVSCC);1132 uvscc = readl(ispi->base + UVSCC);1133 if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK))1134 ispi->swseq_erase = true;1135 /* SPI controller on Intel BXT supports 64K erase opcode */1136 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)1137 if (!(lvscc & ERASE_64K_OPCODE_MASK) ||1138 !(uvscc & ERASE_64K_OPCODE_MASK))1139 erase_64k = false;1140 1141 if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) {1142 dev_err(ispi->dev, "software sequencer not supported, but required\n");1143 return -EINVAL;1144 }1145 1146 /*1147 * Some controllers can only do basic operations using hardware1148 * sequencer. All other operations are supposed to be carried out1149 * using software sequencer.1150 */1151 if (ispi->swseq_reg) {1152 /* Disable #SMI generation from SW sequencer */1153 val = readl(ispi->sregs + SSFSTS_CTL);1154 val &= ~SSFSTS_CTL_FSMIE;1155 writel(val, ispi->sregs + SSFSTS_CTL);1156 }1157 1158 /* Check controller's lock status */1159 val = readl(ispi->base + HSFSTS_CTL);1160 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);1161 1162 if (ispi->locked && ispi->sregs) {1163 /*1164 * BIOS programs allowed opcodes and then locks down the1165 * register. So read back what opcodes it decided to support.1166 * That's the set we are going to support as well.1167 */1168 opmenu0 = readl(ispi->sregs + OPMENU0);1169 opmenu1 = readl(ispi->sregs + OPMENU1);1170 1171 if (opmenu0 && opmenu1) {1172 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {1173 ispi->opcodes[i] = opmenu0 >> i * 8;1174 ispi->opcodes[i + 4] = opmenu1 >> i * 8;1175 }1176 }1177 }1178 1179 if (erase_64k) {1180 dev_dbg(ispi->dev, "Using erase_64k memory operations");1181 ispi->mem_ops = erase_64k_mem_ops;1182 } else {1183 dev_dbg(ispi->dev, "Using generic memory operations");1184 ispi->mem_ops = generic_mem_ops;1185 }1186 1187 intel_spi_dump_regs(ispi);1188 return 0;1189}1190 1191static bool intel_spi_is_protected(const struct intel_spi *ispi,1192 unsigned int base, unsigned int limit)1193{1194 int i;1195 1196 for (i = 0; i < ispi->pr_num; i++) {1197 u32 pr_base, pr_limit, pr_value;1198 1199 pr_value = readl(ispi->pregs + PR(i));1200 if (!(pr_value & (PR_WPE | PR_RPE)))1201 continue;1202 1203 pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;1204 pr_base = pr_value & PR_BASE_MASK;1205 1206 if (pr_base >= base && pr_limit <= limit)1207 return true;1208 }1209 1210 return false;1211}1212 1213/*1214 * There will be a single partition holding all enabled flash regions. We1215 * call this "BIOS".1216 */1217static void intel_spi_fill_partition(struct intel_spi *ispi,1218 struct mtd_partition *part)1219{1220 u64 end;1221 int i;1222 1223 memset(part, 0, sizeof(*part));1224 1225 /* Start from the mandatory descriptor region */1226 part->size = 4096;1227 part->name = "BIOS";1228 1229 /*1230 * Now try to find where this partition ends based on the flash1231 * region registers.1232 */1233 for (i = 1; i < ispi->nregions; i++) {1234 u32 region, base, limit;1235 1236 region = readl(ispi->base + FREG(i));1237 base = region & FREG_BASE_MASK;1238 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;1239 1240 if (base >= limit || limit == 0)1241 continue;1242 1243 /*1244 * If any of the regions have protection bits set, make the1245 * whole partition read-only to be on the safe side.1246 *1247 * Also if the user did not ask the chip to be writeable1248 * mask the bit too.1249 */1250 if (!writeable || intel_spi_is_protected(ispi, base, limit))1251 part->mask_flags |= MTD_WRITEABLE;1252 1253 end = (limit << 12) + 4096;1254 if (end > part->size)1255 part->size = end;1256 }1257 1258 /*1259 * Regions can refer to the second chip too so in this case we1260 * just make the BIOS partition to occupy the whole chip.1261 */1262 if (ispi->chip0_size && part->size > ispi->chip0_size)1263 part->size = MTDPART_SIZ_FULL;1264}1265 1266static int intel_spi_read_desc(struct intel_spi *ispi)1267{1268 struct spi_mem_op op =1269 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_READ, 0),1270 SPI_MEM_OP_ADDR(3, 0, 0),1271 SPI_MEM_OP_NO_DUMMY,1272 SPI_MEM_OP_DATA_IN(0, NULL, 0));1273 u32 buf[2], nc, fcba, flcomp;1274 ssize_t ret;1275 1276 op.addr.val = 0x10;1277 op.data.buf.in = buf;1278 op.data.nbytes = sizeof(buf);1279 1280 ret = intel_spi_read(ispi, NULL, NULL, &op);1281 if (ret) {1282 dev_warn(ispi->dev, "failed to read descriptor\n");1283 return ret;1284 }1285 1286 dev_dbg(ispi->dev, "FLVALSIG=0x%08x\n", buf[0]);1287 dev_dbg(ispi->dev, "FLMAP0=0x%08x\n", buf[1]);1288 1289 if (buf[0] != FLVALSIG_MAGIC) {1290 dev_warn(ispi->dev, "descriptor signature not valid\n");1291 return -ENODEV;1292 }1293 1294 fcba = (buf[1] & FLMAP0_FCBA_MASK) << 4;1295 dev_dbg(ispi->dev, "FCBA=%#x\n", fcba);1296 1297 op.addr.val = fcba;1298 op.data.buf.in = &flcomp;1299 op.data.nbytes = sizeof(flcomp);1300 1301 ret = intel_spi_read(ispi, NULL, NULL, &op);1302 if (ret) {1303 dev_warn(ispi->dev, "failed to read FLCOMP\n");1304 return -ENODEV;1305 }1306 1307 dev_dbg(ispi->dev, "FLCOMP=0x%08x\n", flcomp);1308 1309 switch (flcomp & FLCOMP_C0DEN_MASK) {1310 case FLCOMP_C0DEN_512K:1311 ispi->chip0_size = SZ_512K;1312 break;1313 case FLCOMP_C0DEN_1M:1314 ispi->chip0_size = SZ_1M;1315 break;1316 case FLCOMP_C0DEN_2M:1317 ispi->chip0_size = SZ_2M;1318 break;1319 case FLCOMP_C0DEN_4M:1320 ispi->chip0_size = SZ_4M;1321 break;1322 case FLCOMP_C0DEN_8M:1323 ispi->chip0_size = SZ_8M;1324 break;1325 case FLCOMP_C0DEN_16M:1326 ispi->chip0_size = SZ_16M;1327 break;1328 case FLCOMP_C0DEN_32M:1329 ispi->chip0_size = SZ_32M;1330 break;1331 case FLCOMP_C0DEN_64M:1332 ispi->chip0_size = SZ_64M;1333 break;1334 default:1335 return -EINVAL;1336 }1337 1338 dev_dbg(ispi->dev, "chip0 size %zd KB\n", ispi->chip0_size / SZ_1K);1339 1340 nc = (buf[1] & FLMAP0_NC_MASK) >> FLMAP0_NC_SHIFT;1341 if (!nc)1342 ispi->host->num_chipselect = 1;1343 else if (nc == 1)1344 ispi->host->num_chipselect = 2;1345 else1346 return -EINVAL;1347 1348 dev_dbg(ispi->dev, "%u flash components found\n",1349 ispi->host->num_chipselect);1350 return 0;1351}1352 1353static int intel_spi_populate_chip(struct intel_spi *ispi)1354{1355 struct flash_platform_data *pdata;1356 struct mtd_partition *parts;1357 struct spi_board_info chip;1358 int ret;1359 1360 ret = intel_spi_read_desc(ispi);1361 if (ret)1362 return ret;1363 1364 pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL);1365 if (!pdata)1366 return -ENOMEM;1367 1368 pdata->nr_parts = 1;1369 pdata->parts = devm_kcalloc(ispi->dev, pdata->nr_parts,1370 sizeof(*pdata->parts), GFP_KERNEL);1371 if (!pdata->parts)1372 return -ENOMEM;1373 1374 intel_spi_fill_partition(ispi, pdata->parts);1375 1376 memset(&chip, 0, sizeof(chip));1377 snprintf(chip.modalias, 8, "spi-nor");1378 chip.platform_data = pdata;1379 1380 if (!spi_new_device(ispi->host, &chip))1381 return -ENODEV;1382 1383 /* Add the second chip if present */1384 if (ispi->host->num_chipselect < 2)1385 return 0;1386 1387 pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL);1388 if (!pdata)1389 return -ENOMEM;1390 1391 pdata->name = devm_kasprintf(ispi->dev, GFP_KERNEL, "%s-chip1",1392 dev_name(ispi->dev));1393 if (!pdata->name)1394 return -ENOMEM;1395 1396 pdata->nr_parts = 1;1397 parts = devm_kcalloc(ispi->dev, pdata->nr_parts, sizeof(*parts),1398 GFP_KERNEL);1399 if (!parts)1400 return -ENOMEM;1401 1402 parts[0].size = MTDPART_SIZ_FULL;1403 parts[0].name = "BIOS1";1404 pdata->parts = parts;1405 1406 chip.platform_data = pdata;1407 chip.chip_select = 1;1408 1409 if (!spi_new_device(ispi->host, &chip))1410 return -ENODEV;1411 return 0;1412}1413 1414/**1415 * intel_spi_probe() - Probe the Intel SPI flash controller1416 * @dev: Pointer to the parent device1417 * @mem: MMIO resource1418 * @info: Platform specific information1419 *1420 * Probes Intel SPI flash controller and creates the flash chip device.1421 * Returns %0 on success and negative errno in case of failure.1422 */1423int intel_spi_probe(struct device *dev, struct resource *mem,1424 const struct intel_spi_boardinfo *info)1425{1426 struct spi_controller *host;1427 struct intel_spi *ispi;1428 int ret;1429 1430 host = devm_spi_alloc_host(dev, sizeof(*ispi));1431 if (!host)1432 return -ENOMEM;1433 1434 host->mem_ops = &intel_spi_mem_ops;1435 1436 ispi = spi_controller_get_devdata(host);1437 1438 ispi->base = devm_ioremap_resource(dev, mem);1439 if (IS_ERR(ispi->base))1440 return PTR_ERR(ispi->base);1441 1442 ispi->dev = dev;1443 ispi->host = host;1444 ispi->info = info;1445 1446 ret = intel_spi_init(ispi);1447 if (ret)1448 return ret;1449 1450 ret = devm_spi_register_controller(dev, host);1451 if (ret)1452 return ret;1453 1454 return intel_spi_populate_chip(ispi);1455}1456EXPORT_SYMBOL_GPL(intel_spi_probe);1457 1458MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");1459MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");1460MODULE_LICENSE("GPL v2");1461