964 lines · c
1/*2 * Driver for Amlogic Meson SPI communication controller (SPICC)3 *4 * Copyright (C) BayLibre, SAS5 * Author: Neil Armstrong <narmstrong@baylibre.com>6 *7 * SPDX-License-Identifier: GPL-2.0+8 */9 10#include <linux/bitfield.h>11#include <linux/clk.h>12#include <linux/clk-provider.h>13#include <linux/device.h>14#include <linux/io.h>15#include <linux/kernel.h>16#include <linux/module.h>17#include <linux/of.h>18#include <linux/platform_device.h>19#include <linux/spi/spi.h>20#include <linux/types.h>21#include <linux/interrupt.h>22#include <linux/reset.h>23#include <linux/pinctrl/consumer.h>24 25/*26 * The Meson SPICC controller could support DMA based transfers, but is not27 * implemented by the vendor code, and while having the registers documentation28 * it has never worked on the GXL Hardware.29 * The PIO mode is the only mode implemented, and due to badly designed HW :30 * - all transfers are cutted in 16 words burst because the FIFO hangs on31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by32 * FIFO max size chunk only33 * - CS management is dumb, and goes UP between every burst, so is really a34 * "Data Valid" signal than a Chip Select, GPIO link should be used instead35 * to have a CS go down over the full transfer36 */37 38#define SPICC_MAX_BURST 12839 40/* Register Map */41#define SPICC_RXDATA 0x0042 43#define SPICC_TXDATA 0x0444 45#define SPICC_CONREG 0x0846#define SPICC_ENABLE BIT(0)47#define SPICC_MODE_MASTER BIT(1)48#define SPICC_XCH BIT(2)49#define SPICC_SMC BIT(3)50#define SPICC_POL BIT(4)51#define SPICC_PHA BIT(5)52#define SPICC_SSCTL BIT(6)53#define SPICC_SSPOL BIT(7)54#define SPICC_DRCTL_MASK GENMASK(9, 8)55#define SPICC_DRCTL_IGNORE 056#define SPICC_DRCTL_FALLING 157#define SPICC_DRCTL_LOWLEVEL 258#define SPICC_CS_MASK GENMASK(13, 12)59#define SPICC_DATARATE_MASK GENMASK(18, 16)60#define SPICC_DATARATE_DIV4 061#define SPICC_DATARATE_DIV8 162#define SPICC_DATARATE_DIV16 263#define SPICC_DATARATE_DIV32 364#define SPICC_BITLENGTH_MASK GENMASK(24, 19)65#define SPICC_BURSTLENGTH_MASK GENMASK(31, 25)66 67#define SPICC_INTREG 0x0c68#define SPICC_TE_EN BIT(0) /* TX FIFO Empty Interrupt */69#define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */70#define SPICC_TF_EN BIT(2) /* TX FIFO Full Interrupt */71#define SPICC_RR_EN BIT(3) /* RX FIFO Ready Interrupt */72#define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */73#define SPICC_RF_EN BIT(5) /* RX FIFO Full Interrupt */74#define SPICC_RO_EN BIT(6) /* RX FIFO Overflow Interrupt */75#define SPICC_TC_EN BIT(7) /* Transfert Complete Interrupt */76 77#define SPICC_DMAREG 0x1078#define SPICC_DMA_ENABLE BIT(0)79#define SPICC_TXFIFO_THRESHOLD_MASK GENMASK(5, 1)80#define SPICC_RXFIFO_THRESHOLD_MASK GENMASK(10, 6)81#define SPICC_READ_BURST_MASK GENMASK(14, 11)82#define SPICC_WRITE_BURST_MASK GENMASK(18, 15)83#define SPICC_DMA_URGENT BIT(19)84#define SPICC_DMA_THREADID_MASK GENMASK(25, 20)85#define SPICC_DMA_BURSTNUM_MASK GENMASK(31, 26)86 87#define SPICC_STATREG 0x1488#define SPICC_TE BIT(0) /* TX FIFO Empty Interrupt */89#define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */90#define SPICC_TF BIT(2) /* TX FIFO Full Interrupt */91#define SPICC_RR BIT(3) /* RX FIFO Ready Interrupt */92#define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */93#define SPICC_RF BIT(5) /* RX FIFO Full Interrupt */94#define SPICC_RO BIT(6) /* RX FIFO Overflow Interrupt */95#define SPICC_TC BIT(7) /* Transfert Complete Interrupt */96 97#define SPICC_PERIODREG 0x1898#define SPICC_PERIOD GENMASK(14, 0) /* Wait cycles */99 100#define SPICC_TESTREG 0x1c101#define SPICC_TXCNT_MASK GENMASK(4, 0) /* TX FIFO Counter */102#define SPICC_RXCNT_MASK GENMASK(9, 5) /* RX FIFO Counter */103#define SPICC_SMSTATUS_MASK GENMASK(12, 10) /* State Machine Status */104#define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */105#define SPICC_LBC_W1 BIT(14) /* Loop Back Control Write-Only */106#define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */107#define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */108#define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */109#define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */110#define SPICC_MO_NO_DELAY 0111#define SPICC_MO_DELAY_1_CYCLE 1112#define SPICC_MO_DELAY_2_CYCLE 2113#define SPICC_MO_DELAY_3_CYCLE 3114#define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */115#define SPICC_MI_NO_DELAY 0116#define SPICC_MI_DELAY_1_CYCLE 1117#define SPICC_MI_DELAY_2_CYCLE 2118#define SPICC_MI_DELAY_3_CYCLE 3119#define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */120#define SPICC_CAP_AHEAD_2_CYCLE 0121#define SPICC_CAP_AHEAD_1_CYCLE 1122#define SPICC_CAP_NO_DELAY 2123#define SPICC_CAP_DELAY_1_CYCLE 3124#define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */125#define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */126 127#define SPICC_DRADDR 0x20 /* Read Address of DMA */128 129#define SPICC_DWADDR 0x24 /* Write Address of DMA */130 131#define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */132#define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0)133#define SPICC_ENH_DATARATE_MASK GENMASK(23, 16)134#define SPICC_ENH_DATARATE_EN BIT(24)135#define SPICC_ENH_MOSI_OEN BIT(25)136#define SPICC_ENH_CLK_OEN BIT(26)137#define SPICC_ENH_CS_OEN BIT(27)138#define SPICC_ENH_CLK_CS_DELAY_EN BIT(28)139#define SPICC_ENH_MAIN_CLK_AO BIT(29)140 141#define writel_bits_relaxed(mask, val, addr) \142 writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)143 144struct meson_spicc_data {145 unsigned int max_speed_hz;146 unsigned int min_speed_hz;147 unsigned int fifo_size;148 bool has_oen;149 bool has_enhance_clk_div;150 bool has_pclk;151};152 153struct meson_spicc_device {154 struct spi_controller *host;155 struct platform_device *pdev;156 void __iomem *base;157 struct clk *core;158 struct clk *pclk;159 struct clk_divider pow2_div;160 struct clk *clk;161 struct spi_message *message;162 struct spi_transfer *xfer;163 struct completion done;164 const struct meson_spicc_data *data;165 u8 *tx_buf;166 u8 *rx_buf;167 unsigned int bytes_per_word;168 unsigned long tx_remain;169 unsigned long rx_remain;170 unsigned long xfer_remain;171 struct pinctrl *pinctrl;172 struct pinctrl_state *pins_idle_high;173 struct pinctrl_state *pins_idle_low;174};175 176#define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div)177 178static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)179{180 u32 conf;181 182 if (!spicc->data->has_oen) {183 /* Try to get pinctrl states for idle high/low */184 spicc->pins_idle_high = pinctrl_lookup_state(spicc->pinctrl,185 "idle-high");186 if (IS_ERR(spicc->pins_idle_high)) {187 dev_warn(&spicc->pdev->dev, "can't get idle-high pinctrl\n");188 spicc->pins_idle_high = NULL;189 }190 spicc->pins_idle_low = pinctrl_lookup_state(spicc->pinctrl,191 "idle-low");192 if (IS_ERR(spicc->pins_idle_low)) {193 dev_warn(&spicc->pdev->dev, "can't get idle-low pinctrl\n");194 spicc->pins_idle_low = NULL;195 }196 return;197 }198 199 conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |200 SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;201 202 writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);203}204 205static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)206{207 return !!FIELD_GET(SPICC_TF,208 readl_relaxed(spicc->base + SPICC_STATREG));209}210 211static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc)212{213 return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF,214 readl_relaxed(spicc->base + SPICC_STATREG));215}216 217static inline u32 meson_spicc_pull_data(struct meson_spicc_device *spicc)218{219 unsigned int bytes = spicc->bytes_per_word;220 unsigned int byte_shift = 0;221 u32 data = 0;222 u8 byte;223 224 while (bytes--) {225 byte = *spicc->tx_buf++;226 data |= (byte & 0xff) << byte_shift;227 byte_shift += 8;228 }229 230 spicc->tx_remain--;231 return data;232}233 234static inline void meson_spicc_push_data(struct meson_spicc_device *spicc,235 u32 data)236{237 unsigned int bytes = spicc->bytes_per_word;238 unsigned int byte_shift = 0;239 u8 byte;240 241 while (bytes--) {242 byte = (data >> byte_shift) & 0xff;243 *spicc->rx_buf++ = byte;244 byte_shift += 8;245 }246 247 spicc->rx_remain--;248}249 250static inline void meson_spicc_rx(struct meson_spicc_device *spicc)251{252 /* Empty RX FIFO */253 while (spicc->rx_remain &&254 meson_spicc_rxready(spicc))255 meson_spicc_push_data(spicc,256 readl_relaxed(spicc->base + SPICC_RXDATA));257}258 259static inline void meson_spicc_tx(struct meson_spicc_device *spicc)260{261 /* Fill Up TX FIFO */262 while (spicc->tx_remain &&263 !meson_spicc_txfull(spicc))264 writel_relaxed(meson_spicc_pull_data(spicc),265 spicc->base + SPICC_TXDATA);266}267 268static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc)269{270 271 unsigned int burst_len = min_t(unsigned int,272 spicc->xfer_remain /273 spicc->bytes_per_word,274 spicc->data->fifo_size);275 /* Setup Xfer variables */276 spicc->tx_remain = burst_len;277 spicc->rx_remain = burst_len;278 spicc->xfer_remain -= burst_len * spicc->bytes_per_word;279 280 /* Setup burst length */281 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK,282 FIELD_PREP(SPICC_BURSTLENGTH_MASK,283 burst_len - 1),284 spicc->base + SPICC_CONREG);285 286 /* Fill TX FIFO */287 meson_spicc_tx(spicc);288}289 290static irqreturn_t meson_spicc_irq(int irq, void *data)291{292 struct meson_spicc_device *spicc = (void *) data;293 294 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG);295 296 /* Empty RX FIFO */297 meson_spicc_rx(spicc);298 299 if (!spicc->xfer_remain) {300 /* Disable all IRQs */301 writel(0, spicc->base + SPICC_INTREG);302 303 complete(&spicc->done);304 305 return IRQ_HANDLED;306 }307 308 /* Setup burst */309 meson_spicc_setup_burst(spicc);310 311 /* Start burst */312 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);313 314 return IRQ_HANDLED;315}316 317static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc)318{319 u32 div, hz;320 u32 mi_delay, cap_delay;321 u32 conf;322 323 if (spicc->data->has_enhance_clk_div) {324 div = FIELD_GET(SPICC_ENH_DATARATE_MASK,325 readl_relaxed(spicc->base + SPICC_ENH_CTL0));326 div++;327 div <<= 1;328 } else {329 div = FIELD_GET(SPICC_DATARATE_MASK,330 readl_relaxed(spicc->base + SPICC_CONREG));331 div += 2;332 div = 1 << div;333 }334 335 mi_delay = SPICC_MI_NO_DELAY;336 cap_delay = SPICC_CAP_AHEAD_2_CYCLE;337 hz = clk_get_rate(spicc->clk);338 339 if (hz >= 100000000)340 cap_delay = SPICC_CAP_DELAY_1_CYCLE;341 else if (hz >= 80000000)342 cap_delay = SPICC_CAP_NO_DELAY;343 else if (hz >= 40000000)344 cap_delay = SPICC_CAP_AHEAD_1_CYCLE;345 else if (div >= 16)346 mi_delay = SPICC_MI_DELAY_3_CYCLE;347 else if (div >= 8)348 mi_delay = SPICC_MI_DELAY_2_CYCLE;349 else if (div >= 6)350 mi_delay = SPICC_MI_DELAY_1_CYCLE;351 352 conf = readl_relaxed(spicc->base + SPICC_TESTREG);353 conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK354 | SPICC_MI_CAP_DELAY_MASK);355 conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay);356 conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay);357 writel_relaxed(conf, spicc->base + SPICC_TESTREG);358}359 360static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc,361 struct spi_transfer *xfer)362{363 u32 conf, conf_orig;364 365 /* Read original configuration */366 conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG);367 368 /* Setup word width */369 conf &= ~SPICC_BITLENGTH_MASK;370 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK,371 (spicc->bytes_per_word << 3) - 1);372 373 /* Ignore if unchanged */374 if (conf != conf_orig)375 writel_relaxed(conf, spicc->base + SPICC_CONREG);376 377 clk_set_rate(spicc->clk, xfer->speed_hz);378 379 meson_spicc_auto_io_delay(spicc);380 381 writel_relaxed(0, spicc->base + SPICC_DMAREG);382}383 384static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc)385{386 if (spicc->data->has_oen)387 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO,388 SPICC_ENH_MAIN_CLK_AO,389 spicc->base + SPICC_ENH_CTL0);390 391 writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK,392 spicc->base + SPICC_TESTREG);393 394 while (meson_spicc_rxready(spicc))395 readl_relaxed(spicc->base + SPICC_RXDATA);396 397 if (spicc->data->has_oen)398 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0,399 spicc->base + SPICC_ENH_CTL0);400}401 402static int meson_spicc_transfer_one(struct spi_controller *host,403 struct spi_device *spi,404 struct spi_transfer *xfer)405{406 struct meson_spicc_device *spicc = spi_controller_get_devdata(host);407 uint64_t timeout;408 409 /* Store current transfer */410 spicc->xfer = xfer;411 412 /* Setup transfer parameters */413 spicc->tx_buf = (u8 *)xfer->tx_buf;414 spicc->rx_buf = (u8 *)xfer->rx_buf;415 spicc->xfer_remain = xfer->len;416 417 /* Pre-calculate word size */418 spicc->bytes_per_word =419 DIV_ROUND_UP(spicc->xfer->bits_per_word, 8);420 421 if (xfer->len % spicc->bytes_per_word)422 return -EINVAL;423 424 /* Setup transfer parameters */425 meson_spicc_setup_xfer(spicc, xfer);426 427 meson_spicc_reset_fifo(spicc);428 429 /* Setup burst */430 meson_spicc_setup_burst(spicc);431 432 /* Setup wait for completion */433 reinit_completion(&spicc->done);434 435 /* For each byte we wait for 8 cycles of the SPI clock */436 timeout = 8LL * MSEC_PER_SEC * xfer->len;437 do_div(timeout, xfer->speed_hz);438 439 /* Add 10us delay between each fifo bursts */440 timeout += ((xfer->len >> 4) * 10) / MSEC_PER_SEC;441 442 /* Increase it twice and add 200 ms tolerance */443 timeout += timeout + 200;444 445 /* Start burst */446 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG);447 448 /* Enable interrupts */449 writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG);450 451 if (!wait_for_completion_timeout(&spicc->done, msecs_to_jiffies(timeout)))452 return -ETIMEDOUT;453 454 return 0;455}456 457static int meson_spicc_prepare_message(struct spi_controller *host,458 struct spi_message *message)459{460 struct meson_spicc_device *spicc = spi_controller_get_devdata(host);461 struct spi_device *spi = message->spi;462 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;463 464 /* Store current message */465 spicc->message = message;466 467 /* Enable Master */468 conf |= SPICC_ENABLE;469 conf |= SPICC_MODE_MASTER;470 471 /* SMC = 0 */472 473 /* Setup transfer mode */474 if (spi->mode & SPI_CPOL)475 conf |= SPICC_POL;476 else477 conf &= ~SPICC_POL;478 479 if (!spicc->data->has_oen) {480 if (spi->mode & SPI_CPOL) {481 if (spicc->pins_idle_high)482 pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_high);483 } else {484 if (spicc->pins_idle_low)485 pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_low);486 }487 }488 489 if (spi->mode & SPI_CPHA)490 conf |= SPICC_PHA;491 else492 conf &= ~SPICC_PHA;493 494 /* SSCTL = 0 */495 496 if (spi->mode & SPI_CS_HIGH)497 conf |= SPICC_SSPOL;498 else499 conf &= ~SPICC_SSPOL;500 501 if (spi->mode & SPI_READY)502 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_LOWLEVEL);503 else504 conf |= FIELD_PREP(SPICC_DRCTL_MASK, SPICC_DRCTL_IGNORE);505 506 /* Select CS */507 conf |= FIELD_PREP(SPICC_CS_MASK, spi_get_chipselect(spi, 0));508 509 /* Default 8bit word */510 conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, 8 - 1);511 512 writel_relaxed(conf, spicc->base + SPICC_CONREG);513 514 /* Setup no wait cycles by default */515 writel_relaxed(0, spicc->base + SPICC_PERIODREG);516 517 writel_bits_relaxed(SPICC_LBC_W1,518 spi->mode & SPI_LOOP ? SPICC_LBC_W1 : 0,519 spicc->base + SPICC_TESTREG);520 521 return 0;522}523 524static int meson_spicc_unprepare_transfer(struct spi_controller *host)525{526 struct meson_spicc_device *spicc = spi_controller_get_devdata(host);527 u32 conf = readl_relaxed(spicc->base + SPICC_CONREG) & SPICC_DATARATE_MASK;528 529 /* Disable all IRQs */530 writel(0, spicc->base + SPICC_INTREG);531 532 device_reset_optional(&spicc->pdev->dev);533 534 /* Set default configuration, keeping datarate field */535 writel_relaxed(conf, spicc->base + SPICC_CONREG);536 537 if (!spicc->data->has_oen)538 pinctrl_select_default_state(&spicc->pdev->dev);539 540 return 0;541}542 543static int meson_spicc_setup(struct spi_device *spi)544{545 if (!spi->controller_state)546 spi->controller_state = spi_controller_get_devdata(spi->controller);547 548 return 0;549}550 551static void meson_spicc_cleanup(struct spi_device *spi)552{553 spi->controller_state = NULL;554}555 556/*557 * The Clock Mux558 * x-----------------x x------------x x------\559 * |---| pow2 fixed div |---| pow2 div |----| |560 * | x-----------------x x------------x | |561 * src ---| | mux |-- out562 * | x-----------------x x------------x | |563 * |---| enh fixed div |---| enh div |0---| |564 * x-----------------x x------------x x------/565 *566 * Clk path for GX series:567 * src -> pow2 fixed div -> pow2 div -> out568 *569 * Clk path for AXG series:570 * src -> pow2 fixed div -> pow2 div -> mux -> out571 * src -> enh fixed div -> enh div -> mux -> out572 *573 * Clk path for G12A series:574 * pclk -> pow2 fixed div -> pow2 div -> mux -> out575 * pclk -> enh fixed div -> enh div -> mux -> out576 *577 * The pow2 divider is tied to the controller HW state, and the578 * divider is only valid when the controller is initialized.579 *580 * A set of clock ops is added to make sure we don't read/set this581 * clock rate while the controller is in an unknown state.582 */583 584static unsigned long meson_spicc_pow2_recalc_rate(struct clk_hw *hw,585 unsigned long parent_rate)586{587 struct clk_divider *divider = to_clk_divider(hw);588 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);589 590 if (!spicc->host->cur_msg)591 return 0;592 593 return clk_divider_ops.recalc_rate(hw, parent_rate);594}595 596static int meson_spicc_pow2_determine_rate(struct clk_hw *hw,597 struct clk_rate_request *req)598{599 struct clk_divider *divider = to_clk_divider(hw);600 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);601 602 if (!spicc->host->cur_msg)603 return -EINVAL;604 605 return clk_divider_ops.determine_rate(hw, req);606}607 608static int meson_spicc_pow2_set_rate(struct clk_hw *hw, unsigned long rate,609 unsigned long parent_rate)610{611 struct clk_divider *divider = to_clk_divider(hw);612 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);613 614 if (!spicc->host->cur_msg)615 return -EINVAL;616 617 return clk_divider_ops.set_rate(hw, rate, parent_rate);618}619 620static const struct clk_ops meson_spicc_pow2_clk_ops = {621 .recalc_rate = meson_spicc_pow2_recalc_rate,622 .determine_rate = meson_spicc_pow2_determine_rate,623 .set_rate = meson_spicc_pow2_set_rate,624};625 626static int meson_spicc_pow2_clk_init(struct meson_spicc_device *spicc)627{628 struct device *dev = &spicc->pdev->dev;629 struct clk_fixed_factor *pow2_fixed_div;630 struct clk_init_data init;631 struct clk *clk;632 struct clk_parent_data parent_data[2];633 char name[64];634 635 memset(&init, 0, sizeof(init));636 memset(&parent_data, 0, sizeof(parent_data));637 638 init.parent_data = parent_data;639 640 /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */641 642 pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL);643 if (!pow2_fixed_div)644 return -ENOMEM;645 646 snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev));647 init.name = name;648 init.ops = &clk_fixed_factor_ops;649 if (spicc->data->has_pclk) {650 init.flags = CLK_SET_RATE_PARENT;651 parent_data[0].hw = __clk_get_hw(spicc->pclk);652 } else {653 init.flags = 0;654 parent_data[0].hw = __clk_get_hw(spicc->core);655 }656 init.num_parents = 1;657 658 pow2_fixed_div->mult = 1;659 pow2_fixed_div->div = 4;660 pow2_fixed_div->hw.init = &init;661 662 clk = devm_clk_register(dev, &pow2_fixed_div->hw);663 if (WARN_ON(IS_ERR(clk)))664 return PTR_ERR(clk);665 666 snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev));667 init.name = name;668 init.ops = &meson_spicc_pow2_clk_ops;669 /*670 * Set NOCACHE here to make sure we read the actual HW value671 * since we reset the HW after each transfer.672 */673 init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;674 parent_data[0].hw = &pow2_fixed_div->hw;675 init.num_parents = 1;676 677 spicc->pow2_div.shift = 16;678 spicc->pow2_div.width = 3;679 spicc->pow2_div.flags = CLK_DIVIDER_POWER_OF_TWO;680 spicc->pow2_div.reg = spicc->base + SPICC_CONREG;681 spicc->pow2_div.hw.init = &init;682 683 spicc->clk = devm_clk_register(dev, &spicc->pow2_div.hw);684 if (WARN_ON(IS_ERR(spicc->clk)))685 return PTR_ERR(spicc->clk);686 687 return 0;688}689 690static int meson_spicc_enh_clk_init(struct meson_spicc_device *spicc)691{692 struct device *dev = &spicc->pdev->dev;693 struct clk_fixed_factor *enh_fixed_div;694 struct clk_divider *enh_div;695 struct clk_mux *mux;696 struct clk_init_data init;697 struct clk *clk;698 struct clk_parent_data parent_data[2];699 char name[64];700 701 memset(&init, 0, sizeof(init));702 memset(&parent_data, 0, sizeof(parent_data));703 704 init.parent_data = parent_data;705 706 /* algorithm for enh div: rate = freq / 2 / (N + 1) */707 708 enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL);709 if (!enh_fixed_div)710 return -ENOMEM;711 712 snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev));713 init.name = name;714 init.ops = &clk_fixed_factor_ops;715 if (spicc->data->has_pclk) {716 init.flags = CLK_SET_RATE_PARENT;717 parent_data[0].hw = __clk_get_hw(spicc->pclk);718 } else {719 init.flags = 0;720 parent_data[0].hw = __clk_get_hw(spicc->core);721 }722 init.num_parents = 1;723 724 enh_fixed_div->mult = 1;725 enh_fixed_div->div = 2;726 enh_fixed_div->hw.init = &init;727 728 clk = devm_clk_register(dev, &enh_fixed_div->hw);729 if (WARN_ON(IS_ERR(clk)))730 return PTR_ERR(clk);731 732 enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL);733 if (!enh_div)734 return -ENOMEM;735 736 snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev));737 init.name = name;738 init.ops = &clk_divider_ops;739 init.flags = CLK_SET_RATE_PARENT;740 parent_data[0].hw = &enh_fixed_div->hw;741 init.num_parents = 1;742 743 enh_div->shift = 16;744 enh_div->width = 8;745 enh_div->reg = spicc->base + SPICC_ENH_CTL0;746 enh_div->hw.init = &init;747 748 clk = devm_clk_register(dev, &enh_div->hw);749 if (WARN_ON(IS_ERR(clk)))750 return PTR_ERR(clk);751 752 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);753 if (!mux)754 return -ENOMEM;755 756 snprintf(name, sizeof(name), "%s#sel", dev_name(dev));757 init.name = name;758 init.ops = &clk_mux_ops;759 parent_data[0].hw = &spicc->pow2_div.hw;760 parent_data[1].hw = &enh_div->hw;761 init.num_parents = 2;762 init.flags = CLK_SET_RATE_PARENT;763 764 mux->mask = 0x1;765 mux->shift = 24;766 mux->reg = spicc->base + SPICC_ENH_CTL0;767 mux->hw.init = &init;768 769 spicc->clk = devm_clk_register(dev, &mux->hw);770 if (WARN_ON(IS_ERR(spicc->clk)))771 return PTR_ERR(spicc->clk);772 773 return 0;774}775 776static int meson_spicc_probe(struct platform_device *pdev)777{778 struct spi_controller *host;779 struct meson_spicc_device *spicc;780 int ret, irq;781 782 host = spi_alloc_host(&pdev->dev, sizeof(*spicc));783 if (!host) {784 dev_err(&pdev->dev, "host allocation failed\n");785 return -ENOMEM;786 }787 spicc = spi_controller_get_devdata(host);788 spicc->host = host;789 790 spicc->data = of_device_get_match_data(&pdev->dev);791 if (!spicc->data) {792 dev_err(&pdev->dev, "failed to get match data\n");793 ret = -EINVAL;794 goto out_host;795 }796 797 spicc->pdev = pdev;798 platform_set_drvdata(pdev, spicc);799 800 init_completion(&spicc->done);801 802 spicc->base = devm_platform_ioremap_resource(pdev, 0);803 if (IS_ERR(spicc->base)) {804 dev_err(&pdev->dev, "io resource mapping failed\n");805 ret = PTR_ERR(spicc->base);806 goto out_host;807 }808 809 /* Set master mode and enable controller */810 writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER,811 spicc->base + SPICC_CONREG);812 813 /* Disable all IRQs */814 writel_relaxed(0, spicc->base + SPICC_INTREG);815 816 irq = platform_get_irq(pdev, 0);817 if (irq < 0) {818 ret = irq;819 goto out_host;820 }821 822 ret = devm_request_irq(&pdev->dev, irq, meson_spicc_irq,823 0, NULL, spicc);824 if (ret) {825 dev_err(&pdev->dev, "irq request failed\n");826 goto out_host;827 }828 829 spicc->core = devm_clk_get_enabled(&pdev->dev, "core");830 if (IS_ERR(spicc->core)) {831 dev_err(&pdev->dev, "core clock request failed\n");832 ret = PTR_ERR(spicc->core);833 goto out_host;834 }835 836 if (spicc->data->has_pclk) {837 spicc->pclk = devm_clk_get_enabled(&pdev->dev, "pclk");838 if (IS_ERR(spicc->pclk)) {839 dev_err(&pdev->dev, "pclk clock request failed\n");840 ret = PTR_ERR(spicc->pclk);841 goto out_host;842 }843 }844 845 spicc->pinctrl = devm_pinctrl_get(&pdev->dev);846 if (IS_ERR(spicc->pinctrl)) {847 ret = PTR_ERR(spicc->pinctrl);848 goto out_host;849 }850 851 device_reset_optional(&pdev->dev);852 853 host->num_chipselect = 4;854 host->dev.of_node = pdev->dev.of_node;855 host->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LOOP;856 host->bits_per_word_mask = SPI_BPW_MASK(32) |857 SPI_BPW_MASK(24) |858 SPI_BPW_MASK(16) |859 SPI_BPW_MASK(8);860 host->flags = (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX);861 host->min_speed_hz = spicc->data->min_speed_hz;862 host->max_speed_hz = spicc->data->max_speed_hz;863 host->setup = meson_spicc_setup;864 host->cleanup = meson_spicc_cleanup;865 host->prepare_message = meson_spicc_prepare_message;866 host->unprepare_transfer_hardware = meson_spicc_unprepare_transfer;867 host->transfer_one = meson_spicc_transfer_one;868 host->use_gpio_descriptors = true;869 870 meson_spicc_oen_enable(spicc);871 872 ret = meson_spicc_pow2_clk_init(spicc);873 if (ret) {874 dev_err(&pdev->dev, "pow2 clock registration failed\n");875 goto out_host;876 }877 878 if (spicc->data->has_enhance_clk_div) {879 ret = meson_spicc_enh_clk_init(spicc);880 if (ret) {881 dev_err(&pdev->dev, "clock registration failed\n");882 goto out_host;883 }884 }885 886 ret = devm_spi_register_controller(&pdev->dev, host);887 if (ret) {888 dev_err(&pdev->dev, "spi registration failed\n");889 goto out_host;890 }891 892 return 0;893 894out_host:895 spi_controller_put(host);896 897 return ret;898}899 900static void meson_spicc_remove(struct platform_device *pdev)901{902 struct meson_spicc_device *spicc = platform_get_drvdata(pdev);903 904 /* Disable SPI */905 writel(0, spicc->base + SPICC_CONREG);906 907 spi_controller_put(spicc->host);908}909 910static const struct meson_spicc_data meson_spicc_gx_data = {911 .max_speed_hz = 30000000,912 .min_speed_hz = 325000,913 .fifo_size = 16,914};915 916static const struct meson_spicc_data meson_spicc_axg_data = {917 .max_speed_hz = 80000000,918 .min_speed_hz = 325000,919 .fifo_size = 16,920 .has_oen = true,921 .has_enhance_clk_div = true,922};923 924static const struct meson_spicc_data meson_spicc_g12a_data = {925 .max_speed_hz = 166666666,926 .min_speed_hz = 50000,927 .fifo_size = 15,928 .has_oen = true,929 .has_enhance_clk_div = true,930 .has_pclk = true,931};932 933static const struct of_device_id meson_spicc_of_match[] = {934 {935 .compatible = "amlogic,meson-gx-spicc",936 .data = &meson_spicc_gx_data,937 },938 {939 .compatible = "amlogic,meson-axg-spicc",940 .data = &meson_spicc_axg_data,941 },942 {943 .compatible = "amlogic,meson-g12a-spicc",944 .data = &meson_spicc_g12a_data,945 },946 { /* sentinel */ }947};948MODULE_DEVICE_TABLE(of, meson_spicc_of_match);949 950static struct platform_driver meson_spicc_driver = {951 .probe = meson_spicc_probe,952 .remove_new = meson_spicc_remove,953 .driver = {954 .name = "meson-spicc",955 .of_match_table = of_match_ptr(meson_spicc_of_match),956 },957};958 959module_platform_driver(meson_spicc_driver);960 961MODULE_DESCRIPTION("Meson SPI Communication Controller driver");962MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");963MODULE_LICENSE("GPL");964