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1// SPDX-License-Identifier: (GPL-2.0)2/*3 * Microchip CoreSPI SPI controller driver4 *5 * Copyright (c) 2018-2022 Microchip Technology Inc. and its subsidiaries6 *7 * Author: Daire McNamara <daire.mcnamara@microchip.com>8 * Author: Conor Dooley <conor.dooley@microchip.com>9 *10 */11 12#include <linux/clk.h>13#include <linux/delay.h>14#include <linux/err.h>15#include <linux/init.h>16#include <linux/interrupt.h>17#include <linux/io.h>18#include <linux/module.h>19#include <linux/of.h>20#include <linux/platform_device.h>21#include <linux/spi/spi.h>22 23#define MAX_LEN (0xffff)24#define MAX_CS (1)25#define DEFAULT_FRAMESIZE (8)26#define FIFO_DEPTH (32)27#define CLK_GEN_MODE1_MAX (255)28#define CLK_GEN_MODE0_MAX (15)29#define CLK_GEN_MIN (0)30#define MODE_X_MASK_SHIFT (24)31 32#define CONTROL_ENABLE BIT(0)33#define CONTROL_MASTER BIT(1)34#define CONTROL_RX_DATA_INT BIT(4)35#define CONTROL_TX_DATA_INT BIT(5)36#define CONTROL_RX_OVER_INT BIT(6)37#define CONTROL_TX_UNDER_INT BIT(7)38#define CONTROL_SPO BIT(24)39#define CONTROL_SPH BIT(25)40#define CONTROL_SPS BIT(26)41#define CONTROL_FRAMEURUN BIT(27)42#define CONTROL_CLKMODE BIT(28)43#define CONTROL_BIGFIFO BIT(29)44#define CONTROL_OENOFF BIT(30)45#define CONTROL_RESET BIT(31)46 47#define CONTROL_MODE_MASK GENMASK(3, 2)48#define MOTOROLA_MODE (0)49#define CONTROL_FRAMECNT_MASK GENMASK(23, 8)50#define CONTROL_FRAMECNT_SHIFT (8)51 52#define STATUS_ACTIVE BIT(14)53#define STATUS_SSEL BIT(13)54#define STATUS_FRAMESTART BIT(12)55#define STATUS_TXFIFO_EMPTY_NEXT_READ BIT(11)56#define STATUS_TXFIFO_EMPTY BIT(10)57#define STATUS_TXFIFO_FULL_NEXT_WRITE BIT(9)58#define STATUS_TXFIFO_FULL BIT(8)59#define STATUS_RXFIFO_EMPTY_NEXT_READ BIT(7)60#define STATUS_RXFIFO_EMPTY BIT(6)61#define STATUS_RXFIFO_FULL_NEXT_WRITE BIT(5)62#define STATUS_RXFIFO_FULL BIT(4)63#define STATUS_TX_UNDERRUN BIT(3)64#define STATUS_RX_OVERFLOW BIT(2)65#define STATUS_RXDAT_RXED BIT(1)66#define STATUS_TXDAT_SENT BIT(0)67 68#define INT_TXDONE BIT(0)69#define INT_RXRDY BIT(1)70#define INT_RX_CHANNEL_OVERFLOW BIT(2)71#define INT_TX_CHANNEL_UNDERRUN BIT(3)72 73#define INT_ENABLE_MASK (CONTROL_RX_DATA_INT | CONTROL_TX_DATA_INT | \74 CONTROL_RX_OVER_INT | CONTROL_TX_UNDER_INT)75 76#define REG_CONTROL (0x00)77#define REG_FRAME_SIZE (0x04)78#define FRAME_SIZE_MASK GENMASK(5, 0)79#define REG_STATUS (0x08)80#define REG_INT_CLEAR (0x0c)81#define REG_RX_DATA (0x10)82#define REG_TX_DATA (0x14)83#define REG_CLK_GEN (0x18)84#define REG_SLAVE_SELECT (0x1c)85#define SSEL_MASK GENMASK(7, 0)86#define SSEL_DIRECT BIT(8)87#define SSELOUT_SHIFT 988#define SSELOUT BIT(SSELOUT_SHIFT)89#define REG_MIS (0x20)90#define REG_RIS (0x24)91#define REG_CONTROL2 (0x28)92#define REG_COMMAND (0x2c)93#define COMMAND_CLRFRAMECNT BIT(4)94#define COMMAND_TXFIFORST BIT(3)95#define COMMAND_RXFIFORST BIT(2)96#define REG_PKTSIZE (0x30)97#define REG_CMD_SIZE (0x34)98#define REG_HWSTATUS (0x38)99#define REG_STAT8 (0x3c)100#define REG_CTRL2 (0x48)101#define REG_FRAMESUP (0x50)102 103struct mchp_corespi {104 void __iomem *regs;105 struct clk *clk;106 const u8 *tx_buf;107 u8 *rx_buf;108 u32 clk_gen; /* divider for spi output clock generated by the controller */109 u32 clk_mode;110 u32 pending_slave_select;111 int irq;112 int tx_len;113 int rx_len;114 int n_bytes;115};116 117static inline u32 mchp_corespi_read(struct mchp_corespi *spi, unsigned int reg)118{119 return readl(spi->regs + reg);120}121 122static inline void mchp_corespi_write(struct mchp_corespi *spi, unsigned int reg, u32 val)123{124 writel(val, spi->regs + reg);125}126 127static inline void mchp_corespi_disable(struct mchp_corespi *spi)128{129 u32 control = mchp_corespi_read(spi, REG_CONTROL);130 131 control &= ~CONTROL_ENABLE;132 133 mchp_corespi_write(spi, REG_CONTROL, control);134}135 136static inline void mchp_corespi_read_fifo(struct mchp_corespi *spi)137{138 while (spi->rx_len >= spi->n_bytes && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_RXFIFO_EMPTY)) {139 u32 data = mchp_corespi_read(spi, REG_RX_DATA);140 141 spi->rx_len -= spi->n_bytes;142 143 if (!spi->rx_buf)144 continue;145 146 if (spi->n_bytes == 4)147 *((u32 *)spi->rx_buf) = data;148 else if (spi->n_bytes == 2)149 *((u16 *)spi->rx_buf) = data;150 else151 *spi->rx_buf = data;152 153 spi->rx_buf += spi->n_bytes;154 }155}156 157static void mchp_corespi_enable_ints(struct mchp_corespi *spi)158{159 u32 control = mchp_corespi_read(spi, REG_CONTROL);160 161 control |= INT_ENABLE_MASK;162 mchp_corespi_write(spi, REG_CONTROL, control);163}164 165static void mchp_corespi_disable_ints(struct mchp_corespi *spi)166{167 u32 control = mchp_corespi_read(spi, REG_CONTROL);168 169 control &= ~INT_ENABLE_MASK;170 mchp_corespi_write(spi, REG_CONTROL, control);171}172 173static inline void mchp_corespi_set_xfer_size(struct mchp_corespi *spi, int len)174{175 u32 control;176 u32 lenpart;177 u32 frames = mchp_corespi_read(spi, REG_FRAMESUP);178 179 /*180 * Writing to FRAMECNT in REG_CONTROL will reset the frame count, taking181 * a shortcut requires an explicit clear.182 */183 if (frames == len) {184 mchp_corespi_write(spi, REG_COMMAND, COMMAND_CLRFRAMECNT);185 return;186 }187 188 /*189 * The lower 16 bits of the frame count are stored in the control reg190 * for legacy reasons, but the upper 16 written to a different register:191 * FRAMESUP. While both the upper and lower bits can be *READ* from the192 * FRAMESUP register, writing to the lower 16 bits is (supposedly) a NOP.193 *194 * The driver used to disable the controller while modifying the frame195 * count, and mask off the lower 16 bits of len while writing to196 * FRAMES_UP. When the driver was changed to disable the controller as197 * infrequently as possible, it was discovered that the logic of198 * lenpart = len & 0xffff_0000199 * write(REG_FRAMESUP, lenpart)200 * would actually write zeros into the lower 16 bits on an mpfs250t-es,201 * despite documentation stating these bits were read-only.202 * Writing len unmasked into FRAMES_UP ensures those bits aren't zeroed203 * on an mpfs250t-es and will be a NOP for the lower 16 bits on hardware204 * that matches the documentation.205 */206 lenpart = len & 0xffff;207 control = mchp_corespi_read(spi, REG_CONTROL);208 control &= ~CONTROL_FRAMECNT_MASK;209 control |= lenpart << CONTROL_FRAMECNT_SHIFT;210 mchp_corespi_write(spi, REG_CONTROL, control);211 mchp_corespi_write(spi, REG_FRAMESUP, len);212}213 214static inline void mchp_corespi_write_fifo(struct mchp_corespi *spi)215{216 int fifo_max, i = 0;217 218 fifo_max = DIV_ROUND_UP(min(spi->tx_len, FIFO_DEPTH), spi->n_bytes);219 mchp_corespi_set_xfer_size(spi, fifo_max);220 221 while ((i < fifo_max) && !(mchp_corespi_read(spi, REG_STATUS) & STATUS_TXFIFO_FULL)) {222 u32 word;223 224 if (spi->n_bytes == 4)225 word = spi->tx_buf ? *((u32 *)spi->tx_buf) : 0xaa;226 else if (spi->n_bytes == 2)227 word = spi->tx_buf ? *((u16 *)spi->tx_buf) : 0xaa;228 else229 word = spi->tx_buf ? *spi->tx_buf : 0xaa;230 231 mchp_corespi_write(spi, REG_TX_DATA, word);232 if (spi->tx_buf)233 spi->tx_buf += spi->n_bytes;234 i++;235 }236 237 spi->tx_len -= i * spi->n_bytes;238}239 240static inline void mchp_corespi_set_framesize(struct mchp_corespi *spi, int bt)241{242 u32 frame_size = mchp_corespi_read(spi, REG_FRAME_SIZE);243 u32 control;244 245 if ((frame_size & FRAME_SIZE_MASK) == bt)246 return;247 248 /*249 * Disable the SPI controller. Writes to the frame size have250 * no effect when the controller is enabled.251 */252 control = mchp_corespi_read(spi, REG_CONTROL);253 control &= ~CONTROL_ENABLE;254 mchp_corespi_write(spi, REG_CONTROL, control);255 256 mchp_corespi_write(spi, REG_FRAME_SIZE, bt);257 258 control |= CONTROL_ENABLE;259 mchp_corespi_write(spi, REG_CONTROL, control);260}261 262static void mchp_corespi_set_cs(struct spi_device *spi, bool disable)263{264 u32 reg;265 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);266 267 reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);268 reg &= ~BIT(spi_get_chipselect(spi, 0));269 reg |= !disable << spi_get_chipselect(spi, 0);270 corespi->pending_slave_select = reg;271 272 /*273 * Only deassert chip select immediately. Writing to some registers274 * requires the controller to be disabled, which results in the275 * output pins being tristated and can cause the SCLK and MOSI lines276 * to transition. Therefore asserting the chip select is deferred277 * until just before writing to the TX FIFO, to ensure the device278 * doesn't see any spurious clock transitions whilst CS is enabled.279 */280 if (((spi->mode & SPI_CS_HIGH) == 0) == disable)281 mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);282}283 284static int mchp_corespi_setup(struct spi_device *spi)285{286 struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);287 u32 reg;288 289 if (spi_is_csgpiod(spi))290 return 0;291 292 /*293 * Active high targets need to be specifically set to their inactive294 * states during probe by adding them to the "control group" & thus295 * driving their select line low.296 */297 if (spi->mode & SPI_CS_HIGH) {298 reg = mchp_corespi_read(corespi, REG_SLAVE_SELECT);299 reg |= BIT(spi_get_chipselect(spi, 0));300 corespi->pending_slave_select = reg;301 mchp_corespi_write(corespi, REG_SLAVE_SELECT, reg);302 }303 return 0;304}305 306static void mchp_corespi_init(struct spi_controller *host, struct mchp_corespi *spi)307{308 unsigned long clk_hz;309 u32 control = mchp_corespi_read(spi, REG_CONTROL);310 311 control &= ~CONTROL_ENABLE;312 mchp_corespi_write(spi, REG_CONTROL, control);313 314 control |= CONTROL_MASTER;315 control &= ~CONTROL_MODE_MASK;316 control |= MOTOROLA_MODE;317 318 /*319 * The controller must be configured so that it doesn't remove Chip320 * Select until the entire message has been transferred, even if at321 * some points TX FIFO becomes empty.322 *323 * BIGFIFO mode is also enabled, which sets the fifo depth to 32 frames324 * for the 8 bit transfers that this driver uses.325 */326 control |= CONTROL_SPS | CONTROL_BIGFIFO;327 328 mchp_corespi_write(spi, REG_CONTROL, control);329 330 mchp_corespi_set_framesize(spi, DEFAULT_FRAMESIZE);331 332 /* max. possible spi clock rate is the apb clock rate */333 clk_hz = clk_get_rate(spi->clk);334 host->max_speed_hz = clk_hz;335 336 mchp_corespi_enable_ints(spi);337 338 /*339 * It is required to enable direct mode, otherwise control over the chip340 * select is relinquished to the hardware. SSELOUT is enabled too so we341 * can deal with active high targets.342 */343 spi->pending_slave_select = SSELOUT | SSEL_DIRECT;344 mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);345 346 control = mchp_corespi_read(spi, REG_CONTROL);347 348 control &= ~CONTROL_RESET;349 control |= CONTROL_ENABLE;350 351 mchp_corespi_write(spi, REG_CONTROL, control);352}353 354static inline void mchp_corespi_set_clk_gen(struct mchp_corespi *spi)355{356 u32 control;357 358 control = mchp_corespi_read(spi, REG_CONTROL);359 if (spi->clk_mode)360 control |= CONTROL_CLKMODE;361 else362 control &= ~CONTROL_CLKMODE;363 364 mchp_corespi_write(spi, REG_CLK_GEN, spi->clk_gen);365 mchp_corespi_write(spi, REG_CONTROL, control);366}367 368static inline void mchp_corespi_set_mode(struct mchp_corespi *spi, unsigned int mode)369{370 u32 mode_val;371 u32 control = mchp_corespi_read(spi, REG_CONTROL);372 373 switch (mode & SPI_MODE_X_MASK) {374 case SPI_MODE_0:375 mode_val = 0;376 break;377 case SPI_MODE_1:378 mode_val = CONTROL_SPH;379 break;380 case SPI_MODE_2:381 mode_val = CONTROL_SPO;382 break;383 case SPI_MODE_3:384 mode_val = CONTROL_SPH | CONTROL_SPO;385 break;386 }387 388 /*389 * Disable the SPI controller. Writes to the frame protocol have390 * no effect when the controller is enabled.391 */392 393 control &= ~CONTROL_ENABLE;394 mchp_corespi_write(spi, REG_CONTROL, control);395 396 control &= ~(SPI_MODE_X_MASK << MODE_X_MASK_SHIFT);397 control |= mode_val;398 399 mchp_corespi_write(spi, REG_CONTROL, control);400 401 control |= CONTROL_ENABLE;402 mchp_corespi_write(spi, REG_CONTROL, control);403}404 405static irqreturn_t mchp_corespi_interrupt(int irq, void *dev_id)406{407 struct spi_controller *host = dev_id;408 struct mchp_corespi *spi = spi_controller_get_devdata(host);409 u32 intfield = mchp_corespi_read(spi, REG_MIS) & 0xf;410 bool finalise = false;411 412 /* Interrupt line may be shared and not for us at all */413 if (intfield == 0)414 return IRQ_NONE;415 416 if (intfield & INT_TXDONE)417 mchp_corespi_write(spi, REG_INT_CLEAR, INT_TXDONE);418 419 if (intfield & INT_RXRDY) {420 mchp_corespi_write(spi, REG_INT_CLEAR, INT_RXRDY);421 422 if (spi->rx_len)423 mchp_corespi_read_fifo(spi);424 }425 426 if (!spi->rx_len && !spi->tx_len)427 finalise = true;428 429 if (intfield & INT_RX_CHANNEL_OVERFLOW) {430 mchp_corespi_write(spi, REG_INT_CLEAR, INT_RX_CHANNEL_OVERFLOW);431 finalise = true;432 dev_err(&host->dev,433 "%s: RX OVERFLOW: rxlen: %d, txlen: %d\n", __func__,434 spi->rx_len, spi->tx_len);435 }436 437 if (intfield & INT_TX_CHANNEL_UNDERRUN) {438 mchp_corespi_write(spi, REG_INT_CLEAR, INT_TX_CHANNEL_UNDERRUN);439 finalise = true;440 dev_err(&host->dev,441 "%s: TX UNDERFLOW: rxlen: %d, txlen: %d\n", __func__,442 spi->rx_len, spi->tx_len);443 }444 445 if (finalise)446 spi_finalize_current_transfer(host);447 448 return IRQ_HANDLED;449}450 451static int mchp_corespi_calculate_clkgen(struct mchp_corespi *spi,452 unsigned long target_hz)453{454 unsigned long clk_hz, spi_hz, clk_gen;455 456 clk_hz = clk_get_rate(spi->clk);457 if (!clk_hz)458 return -EINVAL;459 spi_hz = min(target_hz, clk_hz);460 461 /*462 * There are two possible clock modes for the controller generated463 * clock's division ratio:464 * CLK_MODE = 0: 1 / (2^(CLK_GEN + 1)) where CLK_GEN = 0 to 15.465 * CLK_MODE = 1: 1 / (2 * CLK_GEN + 1) where CLK_GEN = 0 to 255.466 * First try mode 1, fall back to 0 and if we have tried both modes and467 * we /still/ can't get a good setting, we then throw the toys out of468 * the pram and give up469 * clk_gen is the register name for the clock divider on MPFS.470 */471 clk_gen = DIV_ROUND_UP(clk_hz, 2 * spi_hz) - 1;472 if (clk_gen > CLK_GEN_MODE1_MAX || clk_gen <= CLK_GEN_MIN) {473 clk_gen = DIV_ROUND_UP(clk_hz, spi_hz);474 clk_gen = fls(clk_gen) - 1;475 476 if (clk_gen > CLK_GEN_MODE0_MAX)477 return -EINVAL;478 479 spi->clk_mode = 0;480 } else {481 spi->clk_mode = 1;482 }483 484 spi->clk_gen = clk_gen;485 return 0;486}487 488static int mchp_corespi_transfer_one(struct spi_controller *host,489 struct spi_device *spi_dev,490 struct spi_transfer *xfer)491{492 struct mchp_corespi *spi = spi_controller_get_devdata(host);493 int ret;494 495 ret = mchp_corespi_calculate_clkgen(spi, (unsigned long)xfer->speed_hz);496 if (ret) {497 dev_err(&host->dev, "failed to set clk_gen for target %u Hz\n", xfer->speed_hz);498 return ret;499 }500 501 mchp_corespi_set_clk_gen(spi);502 503 spi->tx_buf = xfer->tx_buf;504 spi->rx_buf = xfer->rx_buf;505 spi->tx_len = xfer->len;506 spi->rx_len = xfer->len;507 spi->n_bytes = roundup_pow_of_two(DIV_ROUND_UP(xfer->bits_per_word, BITS_PER_BYTE));508 509 mchp_corespi_set_framesize(spi, xfer->bits_per_word);510 511 mchp_corespi_write(spi, REG_COMMAND, COMMAND_RXFIFORST | COMMAND_TXFIFORST);512 513 mchp_corespi_write(spi, REG_SLAVE_SELECT, spi->pending_slave_select);514 515 while (spi->tx_len)516 mchp_corespi_write_fifo(spi);517 518 return 1;519}520 521static int mchp_corespi_prepare_message(struct spi_controller *host,522 struct spi_message *msg)523{524 struct spi_device *spi_dev = msg->spi;525 struct mchp_corespi *spi = spi_controller_get_devdata(host);526 527 mchp_corespi_set_mode(spi, spi_dev->mode);528 529 return 0;530}531 532static int mchp_corespi_probe(struct platform_device *pdev)533{534 struct spi_controller *host;535 struct mchp_corespi *spi;536 struct resource *res;537 u32 num_cs;538 int ret = 0;539 540 host = devm_spi_alloc_host(&pdev->dev, sizeof(*spi));541 if (!host)542 return dev_err_probe(&pdev->dev, -ENOMEM,543 "unable to allocate host for SPI controller\n");544 545 platform_set_drvdata(pdev, host);546 547 if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs))548 num_cs = MAX_CS;549 550 host->num_chipselect = num_cs;551 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;552 host->use_gpio_descriptors = true;553 host->setup = mchp_corespi_setup;554 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);555 host->transfer_one = mchp_corespi_transfer_one;556 host->prepare_message = mchp_corespi_prepare_message;557 host->set_cs = mchp_corespi_set_cs;558 host->dev.of_node = pdev->dev.of_node;559 560 spi = spi_controller_get_devdata(host);561 562 spi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);563 if (IS_ERR(spi->regs))564 return PTR_ERR(spi->regs);565 566 spi->irq = platform_get_irq(pdev, 0);567 if (spi->irq < 0)568 return spi->irq;569 570 ret = devm_request_irq(&pdev->dev, spi->irq, mchp_corespi_interrupt,571 IRQF_SHARED, dev_name(&pdev->dev), host);572 if (ret)573 return dev_err_probe(&pdev->dev, ret,574 "could not request irq\n");575 576 spi->clk = devm_clk_get_enabled(&pdev->dev, NULL);577 if (IS_ERR(spi->clk))578 return dev_err_probe(&pdev->dev, PTR_ERR(spi->clk),579 "could not get clk\n");580 581 mchp_corespi_init(host, spi);582 583 ret = devm_spi_register_controller(&pdev->dev, host);584 if (ret) {585 mchp_corespi_disable(spi);586 return dev_err_probe(&pdev->dev, ret,587 "unable to register host for SPI controller\n");588 }589 590 dev_info(&pdev->dev, "Registered SPI controller %d\n", host->bus_num);591 592 return 0;593}594 595static void mchp_corespi_remove(struct platform_device *pdev)596{597 struct spi_controller *host = platform_get_drvdata(pdev);598 struct mchp_corespi *spi = spi_controller_get_devdata(host);599 600 mchp_corespi_disable_ints(spi);601 mchp_corespi_disable(spi);602}603 604#define MICROCHIP_SPI_PM_OPS (NULL)605 606/*607 * Platform driver data structure608 */609 610#if defined(CONFIG_OF)611static const struct of_device_id mchp_corespi_dt_ids[] = {612 { .compatible = "microchip,mpfs-spi" },613 { /* sentinel */ }614};615MODULE_DEVICE_TABLE(of, mchp_corespi_dt_ids);616#endif617 618static struct platform_driver mchp_corespi_driver = {619 .probe = mchp_corespi_probe,620 .driver = {621 .name = "microchip-corespi",622 .pm = MICROCHIP_SPI_PM_OPS,623 .of_match_table = of_match_ptr(mchp_corespi_dt_ids),624 },625 .remove_new = mchp_corespi_remove,626};627module_platform_driver(mchp_corespi_driver);628MODULE_DESCRIPTION("Microchip coreSPI SPI controller driver");629MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");630MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");631MODULE_LICENSE("GPL");632