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1// SPDX-License-Identifier: GPL-2.02// PCI1xxxx SPI driver3// Copyright (C) 2022 Microchip Technology Inc.4// Authors: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>5// Kumaravel Thiagarajan <Kumaravel.Thiagarajan@microchip.com>6 7 8#include <linux/bitfield.h>9#include <linux/delay.h>10#include <linux/dma-mapping.h>11#include <linux/iopoll.h>12#include <linux/irq.h>13#include <linux/module.h>14#include <linux/msi.h>15#include <linux/pci_regs.h>16#include <linux/pci.h>17#include <linux/spinlock.h>18#include <linux/spi/spi.h>19#include "internals.h"20 21#define DRV_NAME "spi-pci1xxxx"22 23#define SYS_FREQ_DEFAULT (62500000)24 25#define PCI1XXXX_SPI_MAX_CLOCK_HZ (30000000)26#define PCI1XXXX_SPI_CLK_20MHZ (20000000)27#define PCI1XXXX_SPI_CLK_15MHZ (15000000)28#define PCI1XXXX_SPI_CLK_12MHZ (12000000)29#define PCI1XXXX_SPI_CLK_10MHZ (10000000)30#define PCI1XXXX_SPI_MIN_CLOCK_HZ (2000000)31 32#define PCI1XXXX_SPI_BUFFER_SIZE (320)33 34#define SPI_MST_CTL_DEVSEL_MASK (GENMASK(27, 25))35#define SPI_MST_CTL_CMD_LEN_MASK (GENMASK(16, 8))36#define SPI_MST_CTL_SPEED_MASK (GENMASK(7, 5))37#define SPI_MSI_VECTOR_SEL_MASK (GENMASK(4, 4))38 39#define SPI_MST_CTL_FORCE_CE (BIT(4))40#define SPI_MST_CTL_MODE_SEL (BIT(2))41#define SPI_MST_CTL_GO (BIT(0))42 43#define SPI_PERI_ADDR_BASE (0x160000)44#define SPI_SYSTEM_ADDR_BASE (0x2000)45#define SPI_MST1_ADDR_BASE (0x800)46 47#define DEV_REV_REG (SPI_SYSTEM_ADDR_BASE + 0x00)48#define SPI_SYSLOCK_REG (SPI_SYSTEM_ADDR_BASE + 0xA0)49#define SPI_CONFIG_PERI_ENABLE_REG (SPI_SYSTEM_ADDR_BASE + 0x108)50 51#define SPI_PERI_ENBLE_PF_MASK (GENMASK(17, 16))52#define DEV_REV_MASK (GENMASK(7, 0))53 54#define SPI_SYSLOCK BIT(4)55#define SPI0 (0)56#define SPI1 (1)57 58/* DMA Related Registers */59#define SPI_DMA_ADDR_BASE (0x1000)60#define SPI_DMA_GLOBAL_WR_ENGINE_EN (SPI_DMA_ADDR_BASE + 0x0C)61#define SPI_DMA_WR_DOORBELL_REG (SPI_DMA_ADDR_BASE + 0x10)62#define SPI_DMA_GLOBAL_RD_ENGINE_EN (SPI_DMA_ADDR_BASE + 0x2C)63#define SPI_DMA_RD_DOORBELL_REG (SPI_DMA_ADDR_BASE + 0x30)64#define SPI_DMA_INTR_WR_STS (SPI_DMA_ADDR_BASE + 0x4C)65#define SPI_DMA_WR_INT_MASK (SPI_DMA_ADDR_BASE + 0x54)66#define SPI_DMA_INTR_WR_CLR (SPI_DMA_ADDR_BASE + 0x58)67#define SPI_DMA_ERR_WR_STS (SPI_DMA_ADDR_BASE + 0x5C)68#define SPI_DMA_INTR_IMWR_WDONE_LOW (SPI_DMA_ADDR_BASE + 0x60)69#define SPI_DMA_INTR_IMWR_WDONE_HIGH (SPI_DMA_ADDR_BASE + 0x64)70#define SPI_DMA_INTR_IMWR_WABORT_LOW (SPI_DMA_ADDR_BASE + 0x68)71#define SPI_DMA_INTR_IMWR_WABORT_HIGH (SPI_DMA_ADDR_BASE + 0x6C)72#define SPI_DMA_INTR_WR_IMWR_DATA (SPI_DMA_ADDR_BASE + 0x70)73#define SPI_DMA_INTR_RD_STS (SPI_DMA_ADDR_BASE + 0xA0)74#define SPI_DMA_RD_INT_MASK (SPI_DMA_ADDR_BASE + 0xA8)75#define SPI_DMA_INTR_RD_CLR (SPI_DMA_ADDR_BASE + 0xAC)76#define SPI_DMA_ERR_RD_STS (SPI_DMA_ADDR_BASE + 0xB8)77#define SPI_DMA_INTR_IMWR_RDONE_LOW (SPI_DMA_ADDR_BASE + 0xCC)78#define SPI_DMA_INTR_IMWR_RDONE_HIGH (SPI_DMA_ADDR_BASE + 0xD0)79#define SPI_DMA_INTR_IMWR_RABORT_LOW (SPI_DMA_ADDR_BASE + 0xD4)80#define SPI_DMA_INTR_IMWR_RABORT_HIGH (SPI_DMA_ADDR_BASE + 0xD8)81#define SPI_DMA_INTR_RD_IMWR_DATA (SPI_DMA_ADDR_BASE + 0xDC)82 83#define SPI_DMA_CH0_WR_BASE (SPI_DMA_ADDR_BASE + 0x200)84#define SPI_DMA_CH0_RD_BASE (SPI_DMA_ADDR_BASE + 0x300)85#define SPI_DMA_CH1_WR_BASE (SPI_DMA_ADDR_BASE + 0x400)86#define SPI_DMA_CH1_RD_BASE (SPI_DMA_ADDR_BASE + 0x500)87 88#define SPI_DMA_CH_CTL1_OFFSET (0x00)89#define SPI_DMA_CH_XFER_LEN_OFFSET (0x08)90#define SPI_DMA_CH_SAR_LO_OFFSET (0x0C)91#define SPI_DMA_CH_SAR_HI_OFFSET (0x10)92#define SPI_DMA_CH_DAR_LO_OFFSET (0x14)93#define SPI_DMA_CH_DAR_HI_OFFSET (0x18)94 95#define SPI_DMA_CH0_DONE_INT BIT(0)96#define SPI_DMA_CH1_DONE_INT BIT(1)97#define SPI_DMA_CH0_ABORT_INT BIT(16)98#define SPI_DMA_CH1_ABORT_INT BIT(17)99#define SPI_DMA_DONE_INT_MASK (SPI_DMA_CH0_DONE_INT | SPI_DMA_CH1_DONE_INT)100#define SPI_DMA_ABORT_INT_MASK (SPI_DMA_CH0_ABORT_INT | SPI_DMA_CH1_ABORT_INT)101#define DMA_CH_CONTROL_LIE BIT(3)102#define DMA_CH_CONTROL_RIE BIT(4)103#define DMA_INTR_EN (DMA_CH_CONTROL_RIE | DMA_CH_CONTROL_LIE)104 105/* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */106 107#define SPI_MST_CMD_BUF_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x00)108#define SPI_MST_RSP_BUF_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x200)109#define SPI_MST_CTL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x400)110#define SPI_MST_EVENT_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x420)111#define SPI_MST_EVENT_MASK_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x424)112#define SPI_MST_PAD_CTL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x460)113#define SPIALERT_MST_DB_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x464)114#define SPIALERT_MST_VAL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x468)115#define SPI_PCI_CTRL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x480)116 117#define PCI1XXXX_IRQ_FLAGS (IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE)118#define SPI_MAX_DATA_LEN 320119 120#define PCI1XXXX_SPI_TIMEOUT (msecs_to_jiffies(100))121#define SYSLOCK_RETRY_CNT (1000)122#define SPI_DMA_ENGINE_EN (0x1)123#define SPI_DMA_ENGINE_DIS (0x0)124 125#define SPI_INTR BIT(8)126#define SPI_FORCE_CE BIT(4)127 128#define SPI_CHIP_SEL_COUNT 7129#define VENDOR_ID_MCHP 0x1055130 131#define SPI_SUSPEND_CONFIG 0x101132#define SPI_RESUME_CONFIG 0x203133 134struct pci1xxxx_spi_internal {135 u8 hw_inst;136 u8 clkdiv;137 int irq;138 int mode;139 bool spi_xfer_in_progress;140 void *rx_buf;141 bool dma_aborted_rd;142 u32 bytes_recvd;143 u32 tx_sgl_len;144 u32 rx_sgl_len;145 struct scatterlist *tx_sgl, *rx_sgl;146 bool dma_aborted_wr;147 struct completion spi_xfer_done;148 struct spi_controller *spi_host;149 struct pci1xxxx_spi *parent;150 struct spi_transfer *xfer;151 struct {152 unsigned int dev_sel : 3;153 unsigned int msi_vector_sel : 1;154 } prev_val;155};156 157struct pci1xxxx_spi {158 struct pci_dev *dev;159 u8 total_hw_instances;160 u8 dev_rev;161 void __iomem *reg_base;162 void __iomem *dma_offset_bar;163 /* lock to safely access the DMA registers in isr */164 spinlock_t dma_reg_lock;165 bool can_dma;166 struct pci1xxxx_spi_internal *spi_int[] __counted_by(total_hw_instances);167};168 169static const struct pci_device_id pci1xxxx_spi_pci_id_table[] = {170 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0001), 0, 0, 0x02},171 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0002), 0, 0, 0x01},172 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0003), 0, 0, 0x11},173 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},174 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0001), 0, 0, 0x02},175 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0002), 0, 0, 0x01},176 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0003), 0, 0, 0x11},177 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},178 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0001), 0, 0, 0x02},179 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0002), 0, 0, 0x01},180 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0003), 0, 0, 0x11},181 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},182 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0001), 0, 0, 0x02},183 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0002), 0, 0, 0x01},184 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0003), 0, 0, 0x11},185 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},186 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0001), 0, 0, 0x02},187 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0002), 0, 0, 0x01},188 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0003), 0, 0, 0x11},189 { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0x01},190 { 0, }191};192 193MODULE_DEVICE_TABLE(pci, pci1xxxx_spi_pci_id_table);194 195static int pci1xxxx_set_sys_lock(struct pci1xxxx_spi *par)196{197 writel(SPI_SYSLOCK, par->reg_base + SPI_SYSLOCK_REG);198 return readl(par->reg_base + SPI_SYSLOCK_REG);199}200 201static int pci1xxxx_acquire_sys_lock(struct pci1xxxx_spi *par)202{203 u32 regval;204 205 return readx_poll_timeout(pci1xxxx_set_sys_lock, par, regval,206 (regval & SPI_SYSLOCK), 100,207 SYSLOCK_RETRY_CNT * 100);208}209 210static void pci1xxxx_release_sys_lock(struct pci1xxxx_spi *par)211{212 writel(0x0, par->reg_base + SPI_SYSLOCK_REG);213}214 215static int pci1xxxx_check_spi_can_dma(struct pci1xxxx_spi *spi_bus, int irq)216{217 struct pci_dev *pdev = spi_bus->dev;218 u32 pf_num;219 u32 regval;220 int ret;221 222 /*223 * DEV REV Registers is a system register, HW Syslock bit224 * should be acquired before accessing the register225 */226 ret = pci1xxxx_acquire_sys_lock(spi_bus);227 if (ret) {228 dev_err(&pdev->dev, "Error failed to acquire syslock\n");229 return ret;230 }231 232 regval = readl(spi_bus->reg_base + DEV_REV_REG);233 spi_bus->dev_rev = regval & DEV_REV_MASK;234 if (spi_bus->dev_rev >= 0xC0) {235 regval = readl(spi_bus->reg_base +236 SPI_CONFIG_PERI_ENABLE_REG);237 pf_num = regval & SPI_PERI_ENBLE_PF_MASK;238 }239 240 pci1xxxx_release_sys_lock(spi_bus);241 242 /*243 * DMA is supported only from C0 and SPI can use DMA only if244 * it is mapped to PF0245 */246 if (spi_bus->dev_rev < 0xC0 || pf_num)247 return -EOPNOTSUPP;248 249 /*250 * DMA Supported only with MSI Interrupts251 * One of the SPI instance's MSI vector address and data252 * is used for DMA Interrupt253 */254 if (!irq_get_msi_desc(irq)) {255 dev_warn(&pdev->dev, "Error MSI Interrupt not supported, will operate in PIO mode\n");256 return -EOPNOTSUPP;257 }258 259 spi_bus->dma_offset_bar = pcim_iomap(pdev, 2, pci_resource_len(pdev, 2));260 if (!spi_bus->dma_offset_bar) {261 dev_warn(&pdev->dev, "Error failed to map dma bar, will operate in PIO mode\n");262 return -EOPNOTSUPP;263 }264 265 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {266 dev_warn(&pdev->dev, "Error failed to set DMA mask, will operate in PIO mode\n");267 pcim_iounmap(pdev, spi_bus->dma_offset_bar);268 spi_bus->dma_offset_bar = NULL;269 return -EOPNOTSUPP;270 }271 272 return 0;273}274 275static int pci1xxxx_spi_dma_init(struct pci1xxxx_spi *spi_bus, int irq)276{277 struct msi_msg msi;278 int ret;279 280 ret = pci1xxxx_check_spi_can_dma(spi_bus, irq);281 if (ret)282 return ret;283 284 spin_lock_init(&spi_bus->dma_reg_lock);285 get_cached_msi_msg(irq, &msi);286 writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);287 writel(SPI_DMA_ENGINE_EN, spi_bus->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);288 writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WDONE_HIGH);289 writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WABORT_HIGH);290 writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RDONE_HIGH);291 writel(msi.address_hi, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RABORT_HIGH);292 writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WDONE_LOW);293 writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_WABORT_LOW);294 writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RDONE_LOW);295 writel(msi.address_lo, spi_bus->dma_offset_bar + SPI_DMA_INTR_IMWR_RABORT_LOW);296 writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_WR_IMWR_DATA);297 writel(msi.data, spi_bus->dma_offset_bar + SPI_DMA_INTR_RD_IMWR_DATA);298 dma_set_max_seg_size(&spi_bus->dev->dev, PCI1XXXX_SPI_BUFFER_SIZE);299 spi_bus->can_dma = true;300 return 0;301}302 303static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable)304{305 struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi->controller);306 struct pci1xxxx_spi *par = p->parent;307 u32 regval;308 309 /* Set the DEV_SEL bits of the SPI_MST_CTL_REG */310 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));311 if (!enable) {312 regval |= SPI_FORCE_CE;313 regval &= ~SPI_MST_CTL_DEVSEL_MASK;314 regval |= (spi_get_chipselect(spi, 0) << 25);315 } else {316 regval &= ~SPI_FORCE_CE;317 }318 writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst));319}320 321static u8 pci1xxxx_get_clock_div(u32 hz)322{323 u8 val = 0;324 325 if (hz >= PCI1XXXX_SPI_MAX_CLOCK_HZ)326 val = 2;327 else if ((hz < PCI1XXXX_SPI_MAX_CLOCK_HZ) && (hz >= PCI1XXXX_SPI_CLK_20MHZ))328 val = 3;329 else if ((hz < PCI1XXXX_SPI_CLK_20MHZ) && (hz >= PCI1XXXX_SPI_CLK_15MHZ))330 val = 4;331 else if ((hz < PCI1XXXX_SPI_CLK_15MHZ) && (hz >= PCI1XXXX_SPI_CLK_12MHZ))332 val = 5;333 else if ((hz < PCI1XXXX_SPI_CLK_12MHZ) && (hz >= PCI1XXXX_SPI_CLK_10MHZ))334 val = 6;335 else if ((hz < PCI1XXXX_SPI_CLK_10MHZ) && (hz >= PCI1XXXX_SPI_MIN_CLOCK_HZ))336 val = 7;337 else338 val = 2;339 340 return val;341}342 343static void pci1xxxx_spi_setup_dma_to_io(struct pci1xxxx_spi_internal *p,344 dma_addr_t dma_addr, u32 len)345{346 void __iomem *base;347 348 if (!p->hw_inst)349 base = p->parent->dma_offset_bar + SPI_DMA_CH0_RD_BASE;350 else351 base = p->parent->dma_offset_bar + SPI_DMA_CH1_RD_BASE;352 353 writel(DMA_INTR_EN, base + SPI_DMA_CH_CTL1_OFFSET);354 writel(len, base + SPI_DMA_CH_XFER_LEN_OFFSET);355 writel(lower_32_bits(dma_addr), base + SPI_DMA_CH_SAR_LO_OFFSET);356 writel(upper_32_bits(dma_addr), base + SPI_DMA_CH_SAR_HI_OFFSET);357 /* Updated SPI Command Registers */358 writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)),359 base + SPI_DMA_CH_DAR_LO_OFFSET);360 writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_CMD_BUF_OFFSET(p->hw_inst)),361 base + SPI_DMA_CH_DAR_HI_OFFSET);362}363 364static void pci1xxxx_spi_setup_dma_from_io(struct pci1xxxx_spi_internal *p,365 dma_addr_t dma_addr, u32 len)366{367 void *base;368 369 if (!p->hw_inst)370 base = p->parent->dma_offset_bar + SPI_DMA_CH0_WR_BASE;371 else372 base = p->parent->dma_offset_bar + SPI_DMA_CH1_WR_BASE;373 374 writel(DMA_INTR_EN, base + SPI_DMA_CH_CTL1_OFFSET);375 writel(len, base + SPI_DMA_CH_XFER_LEN_OFFSET);376 writel(lower_32_bits(dma_addr), base + SPI_DMA_CH_DAR_LO_OFFSET);377 writel(upper_32_bits(dma_addr), base + SPI_DMA_CH_DAR_HI_OFFSET);378 writel(lower_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)),379 base + SPI_DMA_CH_SAR_LO_OFFSET);380 writel(upper_32_bits(SPI_PERI_ADDR_BASE + SPI_MST_RSP_BUF_OFFSET(p->hw_inst)),381 base + SPI_DMA_CH_SAR_HI_OFFSET);382}383 384static void pci1xxxx_spi_setup(struct pci1xxxx_spi *par, u8 hw_inst, u32 mode,385 u8 clkdiv, u32 len)386{387 u32 regval;388 389 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));390 regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK |391 SPI_MST_CTL_SPEED_MASK);392 393 if (mode == SPI_MODE_3)394 regval |= SPI_MST_CTL_MODE_SEL;395 396 regval |= FIELD_PREP(SPI_MST_CTL_CMD_LEN_MASK, len);397 regval |= FIELD_PREP(SPI_MST_CTL_SPEED_MASK, clkdiv);398 writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));399}400 401static void pci1xxxx_start_spi_xfer(struct pci1xxxx_spi_internal *p, u8 hw_inst)402{403 u32 regval;404 405 regval = readl(p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));406 regval |= SPI_MST_CTL_GO;407 writel(regval, p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst));408}409 410static int pci1xxxx_spi_transfer_with_io(struct spi_controller *spi_ctlr,411 struct spi_device *spi, struct spi_transfer *xfer)412{413 struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr);414 struct pci1xxxx_spi *par = p->parent;415 int len, loop_iter, transfer_len;416 unsigned long bytes_transfered;417 unsigned long bytes_recvd;418 unsigned long loop_count;419 u8 *rx_buf, result;420 const u8 *tx_buf;421 u32 regval;422 u8 clkdiv;423 424 p->spi_xfer_in_progress = true;425 p->bytes_recvd = 0;426 clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz);427 tx_buf = xfer->tx_buf;428 rx_buf = xfer->rx_buf;429 transfer_len = xfer->len;430 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));431 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));432 433 if (tx_buf) {434 bytes_transfered = 0;435 bytes_recvd = 0;436 loop_count = transfer_len / SPI_MAX_DATA_LEN;437 if (transfer_len % SPI_MAX_DATA_LEN != 0)438 loop_count += 1;439 440 for (loop_iter = 0; loop_iter < loop_count; loop_iter++) {441 len = SPI_MAX_DATA_LEN;442 if ((transfer_len % SPI_MAX_DATA_LEN != 0) &&443 (loop_iter == loop_count - 1))444 len = transfer_len % SPI_MAX_DATA_LEN;445 446 reinit_completion(&p->spi_xfer_done);447 memcpy_toio(par->reg_base + SPI_MST_CMD_BUF_OFFSET(p->hw_inst),448 &tx_buf[bytes_transfered], len);449 bytes_transfered += len;450 pci1xxxx_spi_setup(par, p->hw_inst, spi->mode, clkdiv, len);451 pci1xxxx_start_spi_xfer(p, p->hw_inst);452 453 /* Wait for DMA_TERM interrupt */454 result = wait_for_completion_timeout(&p->spi_xfer_done,455 PCI1XXXX_SPI_TIMEOUT);456 if (!result)457 return -ETIMEDOUT;458 459 if (rx_buf) {460 memcpy_fromio(&rx_buf[bytes_recvd], par->reg_base +461 SPI_MST_RSP_BUF_OFFSET(p->hw_inst), len);462 bytes_recvd += len;463 }464 }465 }466 p->spi_xfer_in_progress = false;467 468 return 0;469}470 471static int pci1xxxx_spi_transfer_with_dma(struct spi_controller *spi_ctlr,472 struct spi_device *spi,473 struct spi_transfer *xfer)474{475 struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(spi_ctlr);476 struct pci1xxxx_spi *par = p->parent;477 dma_addr_t rx_dma_addr = 0;478 dma_addr_t tx_dma_addr = 0;479 int ret = 0;480 u32 regval;481 482 p->spi_xfer_in_progress = true;483 p->tx_sgl = xfer->tx_sg.sgl;484 p->rx_sgl = xfer->rx_sg.sgl;485 p->rx_buf = xfer->rx_buf;486 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));487 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));488 489 if (!xfer->tx_buf || !p->tx_sgl) {490 ret = -EINVAL;491 goto error;492 }493 p->xfer = xfer;494 p->mode = spi->mode;495 p->clkdiv = pci1xxxx_get_clock_div(xfer->speed_hz);496 p->bytes_recvd = 0;497 p->rx_buf = xfer->rx_buf;498 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));499 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));500 501 tx_dma_addr = sg_dma_address(p->tx_sgl);502 rx_dma_addr = sg_dma_address(p->rx_sgl);503 p->tx_sgl_len = sg_dma_len(p->tx_sgl);504 p->rx_sgl_len = sg_dma_len(p->rx_sgl);505 pci1xxxx_spi_setup(par, p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len);506 pci1xxxx_spi_setup_dma_to_io(p, (tx_dma_addr), p->tx_sgl_len);507 if (rx_dma_addr)508 pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len);509 writel(p->hw_inst, par->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG);510 511 reinit_completion(&p->spi_xfer_done);512 /* Wait for DMA_TERM interrupt */513 ret = wait_for_completion_timeout(&p->spi_xfer_done, PCI1XXXX_SPI_TIMEOUT);514 if (!ret) {515 ret = -ETIMEDOUT;516 if (p->dma_aborted_rd) {517 writel(SPI_DMA_ENGINE_DIS,518 par->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);519 /*520 * DMA ENGINE reset takes time if any TLP521 * completeion in progress, should wait522 * till DMA Engine reset is completed.523 */524 ret = readl_poll_timeout(par->dma_offset_bar +525 SPI_DMA_GLOBAL_RD_ENGINE_EN, regval,526 (regval == 0x0), 0, USEC_PER_MSEC);527 if (ret) {528 ret = -ECANCELED;529 goto error;530 }531 writel(SPI_DMA_ENGINE_EN,532 par->dma_offset_bar + SPI_DMA_GLOBAL_RD_ENGINE_EN);533 p->dma_aborted_rd = false;534 ret = -ECANCELED;535 }536 if (p->dma_aborted_wr) {537 writel(SPI_DMA_ENGINE_DIS,538 par->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);539 540 /*541 * DMA ENGINE reset takes time if any TLP542 * completeion in progress, should wait543 * till DMA Engine reset is completed.544 */545 ret = readl_poll_timeout(par->dma_offset_bar +546 SPI_DMA_GLOBAL_WR_ENGINE_EN, regval,547 (regval == 0x0), 0, USEC_PER_MSEC);548 if (ret) {549 ret = -ECANCELED;550 goto error;551 }552 553 writel(SPI_DMA_ENGINE_EN,554 par->dma_offset_bar + SPI_DMA_GLOBAL_WR_ENGINE_EN);555 p->dma_aborted_wr = false;556 ret = -ECANCELED;557 }558 goto error;559 }560 ret = 0;561 562error:563 p->spi_xfer_in_progress = false;564 565 return ret;566}567 568static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr,569 struct spi_device *spi, struct spi_transfer *xfer)570{571 if (spi_xfer_is_dma_mapped(spi_ctlr, spi, xfer))572 return pci1xxxx_spi_transfer_with_dma(spi_ctlr, spi, xfer);573 else574 return pci1xxxx_spi_transfer_with_io(spi_ctlr, spi, xfer);575}576 577static irqreturn_t pci1xxxx_spi_isr_io(int irq, void *dev)578{579 struct pci1xxxx_spi_internal *p = dev;580 irqreturn_t spi_int_fired = IRQ_NONE;581 u32 regval;582 583 /* Clear the SPI GO_BIT Interrupt */584 regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));585 if (regval & SPI_INTR) {586 /* Clear xfer_done */587 if (p->parent->can_dma && p->rx_buf)588 writel(p->hw_inst, p->parent->dma_offset_bar +589 SPI_DMA_WR_DOORBELL_REG);590 else591 complete(&p->parent->spi_int[p->hw_inst]->spi_xfer_done);592 spi_int_fired = IRQ_HANDLED;593 }594 writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));595 return spi_int_fired;596}597 598static void pci1xxxx_spi_setup_next_dma_transfer(struct pci1xxxx_spi_internal *p)599{600 dma_addr_t tx_dma_addr = 0;601 dma_addr_t rx_dma_addr = 0;602 u32 prev_len;603 604 p->tx_sgl = sg_next(p->tx_sgl);605 if (p->rx_sgl)606 p->rx_sgl = sg_next(p->rx_sgl);607 if (!p->tx_sgl) {608 /* Clear xfer_done */609 complete(&p->spi_xfer_done);610 } else {611 tx_dma_addr = sg_dma_address(p->tx_sgl);612 prev_len = p->tx_sgl_len;613 p->tx_sgl_len = sg_dma_len(p->tx_sgl);614 if (prev_len != p->tx_sgl_len)615 pci1xxxx_spi_setup(p->parent,616 p->hw_inst, p->mode, p->clkdiv, p->tx_sgl_len);617 pci1xxxx_spi_setup_dma_to_io(p, tx_dma_addr, p->tx_sgl_len);618 if (p->rx_sgl) {619 rx_dma_addr = sg_dma_address(p->rx_sgl);620 p->rx_sgl_len = sg_dma_len(p->rx_sgl);621 pci1xxxx_spi_setup_dma_from_io(p, rx_dma_addr, p->rx_sgl_len);622 }623 writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_RD_DOORBELL_REG);624 }625}626 627static irqreturn_t pci1xxxx_spi_isr_dma(int irq, void *dev)628{629 struct pci1xxxx_spi_internal *p = dev;630 irqreturn_t spi_int_fired = IRQ_NONE;631 unsigned long flags;632 u32 regval;633 634 spin_lock_irqsave(&p->parent->dma_reg_lock, flags);635 /* Clear the DMA RD INT and start spi xfer*/636 regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_RD_STS);637 if (regval & SPI_DMA_DONE_INT_MASK) {638 if (regval & SPI_DMA_CH0_DONE_INT)639 pci1xxxx_start_spi_xfer(p, SPI0);640 if (regval & SPI_DMA_CH1_DONE_INT)641 pci1xxxx_start_spi_xfer(p, SPI1);642 spi_int_fired = IRQ_HANDLED;643 }644 if (regval & SPI_DMA_ABORT_INT_MASK) {645 p->dma_aborted_rd = true;646 spi_int_fired = IRQ_HANDLED;647 }648 writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_RD_CLR);649 650 /* Clear the DMA WR INT */651 regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_WR_STS);652 if (regval & SPI_DMA_DONE_INT_MASK) {653 if (regval & SPI_DMA_CH0_DONE_INT)654 pci1xxxx_spi_setup_next_dma_transfer(p->parent->spi_int[SPI0]);655 656 if (regval & SPI_DMA_CH1_DONE_INT)657 pci1xxxx_spi_setup_next_dma_transfer(p->parent->spi_int[SPI1]);658 659 spi_int_fired = IRQ_HANDLED;660 }661 if (regval & SPI_DMA_ABORT_INT_MASK) {662 p->dma_aborted_wr = true;663 spi_int_fired = IRQ_HANDLED;664 }665 writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_WR_CLR);666 spin_unlock_irqrestore(&p->parent->dma_reg_lock, flags);667 668 /* Clear the SPI GO_BIT Interrupt */669 regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));670 if (regval & SPI_INTR) {671 writel(p->hw_inst, p->parent->dma_offset_bar + SPI_DMA_WR_DOORBELL_REG);672 spi_int_fired = IRQ_HANDLED;673 }674 writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst));675 return spi_int_fired;676}677 678static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev)679{680 struct pci1xxxx_spi_internal *p = dev;681 682 if (p->spi_host->can_dma(p->spi_host, NULL, p->xfer))683 return pci1xxxx_spi_isr_dma(irq, dev);684 else685 return pci1xxxx_spi_isr_io(irq, dev);686}687 688static bool pci1xxxx_spi_can_dma(struct spi_controller *host,689 struct spi_device *spi,690 struct spi_transfer *xfer)691{692 struct pci1xxxx_spi_internal *p = spi_controller_get_devdata(host);693 struct pci1xxxx_spi *par = p->parent;694 695 return par->can_dma;696}697 698static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_device_id *ent)699{700 u8 hw_inst_cnt, iter, start, only_sec_inst;701 struct pci1xxxx_spi_internal *spi_sub_ptr;702 struct device *dev = &pdev->dev;703 struct pci1xxxx_spi *spi_bus;704 struct spi_controller *spi_host;705 u32 regval;706 int ret;707 708 hw_inst_cnt = ent->driver_data & 0x0f;709 start = (ent->driver_data & 0xf0) >> 4;710 if (start == 1)711 only_sec_inst = 1;712 else713 only_sec_inst = 0;714 715 spi_bus = devm_kzalloc(&pdev->dev,716 struct_size(spi_bus, spi_int, hw_inst_cnt),717 GFP_KERNEL);718 if (!spi_bus)719 return -ENOMEM;720 721 spi_bus->dev = pdev;722 spi_bus->total_hw_instances = hw_inst_cnt;723 pci_set_master(pdev);724 725 for (iter = 0; iter < hw_inst_cnt; iter++) {726 spi_bus->spi_int[iter] = devm_kzalloc(&pdev->dev,727 sizeof(struct pci1xxxx_spi_internal),728 GFP_KERNEL);729 if (!spi_bus->spi_int[iter])730 return -ENOMEM;731 spi_sub_ptr = spi_bus->spi_int[iter];732 spi_sub_ptr->spi_host = devm_spi_alloc_host(dev, sizeof(struct spi_controller));733 if (!spi_sub_ptr->spi_host)734 return -ENOMEM;735 736 spi_sub_ptr->parent = spi_bus;737 spi_sub_ptr->spi_xfer_in_progress = false;738 739 if (!iter) {740 ret = pcim_enable_device(pdev);741 if (ret)742 return -ENOMEM;743 744 ret = pci_request_regions(pdev, DRV_NAME);745 if (ret)746 return -ENOMEM;747 748 spi_bus->reg_base = pcim_iomap(pdev, 0, pci_resource_len(pdev, 0));749 if (!spi_bus->reg_base) {750 ret = -EINVAL;751 goto error;752 }753 754 ret = pci_alloc_irq_vectors(pdev, hw_inst_cnt, hw_inst_cnt,755 PCI_IRQ_ALL_TYPES);756 if (ret < 0) {757 dev_err(&pdev->dev, "Error allocating MSI vectors\n");758 goto error;759 }760 761 init_completion(&spi_sub_ptr->spi_xfer_done);762 /* Initialize Interrupts - SPI_INT */763 regval = readl(spi_bus->reg_base +764 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));765 regval &= ~SPI_INTR;766 writel(regval, spi_bus->reg_base +767 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));768 spi_sub_ptr->irq = pci_irq_vector(pdev, 0);769 770 ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,771 pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,772 pci_name(pdev), spi_sub_ptr);773 if (ret < 0) {774 dev_err(&pdev->dev, "Unable to request irq : %d",775 spi_sub_ptr->irq);776 ret = -ENODEV;777 goto error;778 }779 780 ret = pci1xxxx_spi_dma_init(spi_bus, spi_sub_ptr->irq);781 if (ret && ret != -EOPNOTSUPP)782 goto error;783 784 /* This register is only applicable for 1st instance */785 regval = readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));786 if (!only_sec_inst)787 regval |= (BIT(4));788 else789 regval &= ~(BIT(4));790 791 writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0));792 }793 794 spi_sub_ptr->hw_inst = start++;795 796 if (iter == 1) {797 init_completion(&spi_sub_ptr->spi_xfer_done);798 /* Initialize Interrupts - SPI_INT */799 regval = readl(spi_bus->reg_base +800 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));801 regval &= ~SPI_INTR;802 writel(regval, spi_bus->reg_base +803 SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst));804 spi_sub_ptr->irq = pci_irq_vector(pdev, iter);805 ret = devm_request_irq(&pdev->dev, spi_sub_ptr->irq,806 pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS,807 pci_name(pdev), spi_sub_ptr);808 if (ret < 0) {809 dev_err(&pdev->dev, "Unable to request irq : %d",810 spi_sub_ptr->irq);811 ret = -ENODEV;812 goto error;813 }814 }815 816 spi_host = spi_sub_ptr->spi_host;817 spi_host->num_chipselect = SPI_CHIP_SEL_COUNT;818 spi_host->mode_bits = SPI_MODE_0 | SPI_MODE_3 | SPI_RX_DUAL |819 SPI_TX_DUAL | SPI_LOOP;820 spi_host->can_dma = pci1xxxx_spi_can_dma;821 spi_host->transfer_one = pci1xxxx_spi_transfer_one;822 823 spi_host->set_cs = pci1xxxx_spi_set_cs;824 spi_host->bits_per_word_mask = SPI_BPW_MASK(8);825 spi_host->max_speed_hz = PCI1XXXX_SPI_MAX_CLOCK_HZ;826 spi_host->min_speed_hz = PCI1XXXX_SPI_MIN_CLOCK_HZ;827 spi_host->flags = SPI_CONTROLLER_MUST_TX;828 spi_controller_set_devdata(spi_host, spi_sub_ptr);829 ret = devm_spi_register_controller(dev, spi_host);830 if (ret)831 goto error;832 }833 pci_set_drvdata(pdev, spi_bus);834 835 return 0;836 837error:838 pci_release_regions(pdev);839 return ret;840}841 842static void store_restore_config(struct pci1xxxx_spi *spi_ptr,843 struct pci1xxxx_spi_internal *spi_sub_ptr,844 u8 inst, bool store)845{846 u32 regval;847 848 if (store) {849 regval = readl(spi_ptr->reg_base +850 SPI_MST_CTL_REG_OFFSET(spi_sub_ptr->hw_inst));851 regval &= SPI_MST_CTL_DEVSEL_MASK;852 spi_sub_ptr->prev_val.dev_sel = (regval >> 25) & 7;853 regval = readl(spi_ptr->reg_base +854 SPI_PCI_CTRL_REG_OFFSET(spi_sub_ptr->hw_inst));855 regval &= SPI_MSI_VECTOR_SEL_MASK;856 spi_sub_ptr->prev_val.msi_vector_sel = (regval >> 4) & 1;857 } else {858 regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));859 regval &= ~SPI_MST_CTL_DEVSEL_MASK;860 regval |= (spi_sub_ptr->prev_val.dev_sel << 25);861 writel(regval,862 spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst));863 writel((spi_sub_ptr->prev_val.msi_vector_sel << 4),864 spi_ptr->reg_base + SPI_PCI_CTRL_REG_OFFSET(inst));865 }866}867 868static int pci1xxxx_spi_resume(struct device *dev)869{870 struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);871 struct pci1xxxx_spi_internal *spi_sub_ptr;872 u32 regval = SPI_RESUME_CONFIG;873 u8 iter;874 875 for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {876 spi_sub_ptr = spi_ptr->spi_int[iter];877 spi_controller_resume(spi_sub_ptr->spi_host);878 writel(regval, spi_ptr->reg_base +879 SPI_MST_EVENT_MASK_REG_OFFSET(iter));880 881 /* Restore config at resume */882 store_restore_config(spi_ptr, spi_sub_ptr, iter, 0);883 }884 885 return 0;886}887 888static int pci1xxxx_spi_suspend(struct device *dev)889{890 struct pci1xxxx_spi *spi_ptr = dev_get_drvdata(dev);891 struct pci1xxxx_spi_internal *spi_sub_ptr;892 u32 reg1 = SPI_SUSPEND_CONFIG;893 u8 iter;894 895 for (iter = 0; iter < spi_ptr->total_hw_instances; iter++) {896 spi_sub_ptr = spi_ptr->spi_int[iter];897 898 while (spi_sub_ptr->spi_xfer_in_progress)899 msleep(20);900 901 /* Store existing config before suspend */902 store_restore_config(spi_ptr, spi_sub_ptr, iter, 1);903 spi_controller_suspend(spi_sub_ptr->spi_host);904 writel(reg1, spi_ptr->reg_base +905 SPI_MST_EVENT_MASK_REG_OFFSET(iter));906 }907 908 return 0;909}910 911static DEFINE_SIMPLE_DEV_PM_OPS(spi_pm_ops, pci1xxxx_spi_suspend,912 pci1xxxx_spi_resume);913 914static struct pci_driver pci1xxxx_spi_driver = {915 .name = DRV_NAME,916 .id_table = pci1xxxx_spi_pci_id_table,917 .probe = pci1xxxx_spi_probe,918 .driver = {919 .pm = pm_sleep_ptr(&spi_pm_ops),920 },921};922 923module_pci_driver(pci1xxxx_spi_driver);924 925MODULE_DESCRIPTION("Microchip Technology Inc. pci1xxxx SPI bus driver");926MODULE_AUTHOR("Tharun Kumar P<tharunkumar.pasumarthi@microchip.com>");927MODULE_AUTHOR("Kumaravel Thiagarajan<kumaravel.thiagarajan@microchip.com>");928MODULE_LICENSE("GPL v2");929