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1// SPDX-License-Identifier: GPL-2.0+2/*3 * Copyright (C) 2019 Xilinx, Inc.4 *5 * Author: Naga Sureshkumar Relli <nagasure@xilinx.com>6 */7 8#include <linux/clk.h>9#include <linux/delay.h>10#include <linux/interrupt.h>11#include <linux/io.h>12#include <linux/module.h>13#include <linux/of_irq.h>14#include <linux/of_address.h>15#include <linux/platform_device.h>16#include <linux/spi/spi.h>17#include <linux/workqueue.h>18#include <linux/spi/spi-mem.h>19 20/* Register offset definitions */21#define ZYNQ_QSPI_CONFIG_OFFSET 0x00 /* Configuration Register, RW */22#define ZYNQ_QSPI_STATUS_OFFSET 0x04 /* Interrupt Status Register, RO */23#define ZYNQ_QSPI_IEN_OFFSET 0x08 /* Interrupt Enable Register, WO */24#define ZYNQ_QSPI_IDIS_OFFSET 0x0C /* Interrupt Disable Reg, WO */25#define ZYNQ_QSPI_IMASK_OFFSET 0x10 /* Interrupt Enabled Mask Reg,RO */26#define ZYNQ_QSPI_ENABLE_OFFSET 0x14 /* Enable/Disable Register, RW */27#define ZYNQ_QSPI_DELAY_OFFSET 0x18 /* Delay Register, RW */28#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */29#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */30#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */31#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */32#define ZYNQ_QSPI_RXD_OFFSET 0x20 /* Data Receive Register, RO */33#define ZYNQ_QSPI_SIC_OFFSET 0x24 /* Slave Idle Count Register, RW */34#define ZYNQ_QSPI_TX_THRESH_OFFSET 0x28 /* TX FIFO Watermark Reg, RW */35#define ZYNQ_QSPI_RX_THRESH_OFFSET 0x2C /* RX FIFO Watermark Reg, RW */36#define ZYNQ_QSPI_GPIO_OFFSET 0x30 /* GPIO Register, RW */37#define ZYNQ_QSPI_LINEAR_CFG_OFFSET 0xA0 /* Linear Adapter Config Ref, RW */38#define ZYNQ_QSPI_MOD_ID_OFFSET 0xFC /* Module ID Register, RO */39 40/*41 * QSPI Configuration Register bit Masks42 *43 * This register contains various control bits that effect the operation44 * of the QSPI controller45 */46#define ZYNQ_QSPI_CONFIG_IFMODE_MASK BIT(31) /* Flash Memory Interface */47#define ZYNQ_QSPI_CONFIG_MANSRT_MASK BIT(16) /* Manual TX Start */48#define ZYNQ_QSPI_CONFIG_MANSRTEN_MASK BIT(15) /* Enable Manual TX Mode */49#define ZYNQ_QSPI_CONFIG_SSFORCE_MASK BIT(14) /* Manual Chip Select */50#define ZYNQ_QSPI_CONFIG_BDRATE_MASK GENMASK(5, 3) /* Baud Rate Mask */51#define ZYNQ_QSPI_CONFIG_CPHA_MASK BIT(2) /* Clock Phase Control */52#define ZYNQ_QSPI_CONFIG_CPOL_MASK BIT(1) /* Clock Polarity Control */53#define ZYNQ_QSPI_CONFIG_FWIDTH_MASK GENMASK(7, 6) /* FIFO width */54#define ZYNQ_QSPI_CONFIG_MSTREN_MASK BIT(0) /* Master Mode */55 56/*57 * QSPI Configuration Register - Baud rate and target select58 *59 * These are the values used in the calculation of baud rate divisor and60 * setting the target select.61 */62#define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */63#define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift */64#define ZYNQ_QSPI_CONFIG_PCS BIT(10) /* Peripheral Chip Select */65 66/*67 * QSPI Interrupt Registers bit Masks68 *69 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same70 * bit definitions.71 */72#define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */73#define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */74#define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */75#define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */76#define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */77#define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */78#define ZYNQ_QSPI_IXR_ALL_MASK (ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK | \79 ZYNQ_QSPI_IXR_TXNFULL_MASK | \80 ZYNQ_QSPI_IXR_TXFULL_MASK | \81 ZYNQ_QSPI_IXR_RXNEMTY_MASK | \82 ZYNQ_QSPI_IXR_RXF_FULL_MASK | \83 ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK)84#define ZYNQ_QSPI_IXR_RXTX_MASK (ZYNQ_QSPI_IXR_TXNFULL_MASK | \85 ZYNQ_QSPI_IXR_RXNEMTY_MASK)86 87/*88 * QSPI Enable Register bit Masks89 *90 * This register is used to enable or disable the QSPI controller91 */92#define ZYNQ_QSPI_ENABLE_ENABLE_MASK BIT(0) /* QSPI Enable Bit Mask */93 94/*95 * QSPI Linear Configuration Register96 *97 * It is named Linear Configuration but it controls other modes when not in98 * linear mode also.99 */100#define ZYNQ_QSPI_LCFG_TWO_MEM BIT(30) /* LQSPI Two memories */101#define ZYNQ_QSPI_LCFG_SEP_BUS BIT(29) /* LQSPI Separate bus */102#define ZYNQ_QSPI_LCFG_U_PAGE BIT(28) /* LQSPI Upper Page */103 104#define ZYNQ_QSPI_LCFG_DUMMY_SHIFT 8105 106#define ZYNQ_QSPI_FAST_READ_QOUT_CODE 0x6B /* read instruction code */107#define ZYNQ_QSPI_FIFO_DEPTH 63 /* FIFO depth in words */108#define ZYNQ_QSPI_RX_THRESHOLD 32 /* Rx FIFO threshold level */109#define ZYNQ_QSPI_TX_THRESHOLD 1 /* Tx FIFO threshold level */110 111/*112 * The modebits configurable by the driver to make the SPI support different113 * data formats114 */115#define ZYNQ_QSPI_MODEBITS (SPI_CPOL | SPI_CPHA)116 117/* Maximum number of chip selects */118#define ZYNQ_QSPI_MAX_NUM_CS 2119 120/**121 * struct zynq_qspi - Defines qspi driver instance122 * @dev: Pointer to the this device's information123 * @regs: Virtual address of the QSPI controller registers124 * @refclk: Pointer to the peripheral clock125 * @pclk: Pointer to the APB clock126 * @irq: IRQ number127 * @txbuf: Pointer to the TX buffer128 * @rxbuf: Pointer to the RX buffer129 * @tx_bytes: Number of bytes left to transfer130 * @rx_bytes: Number of bytes left to receive131 * @data_completion: completion structure132 */133struct zynq_qspi {134 struct device *dev;135 void __iomem *regs;136 struct clk *refclk;137 struct clk *pclk;138 int irq;139 u8 *txbuf;140 u8 *rxbuf;141 int tx_bytes;142 int rx_bytes;143 struct completion data_completion;144};145 146/*147 * Inline functions for the QSPI controller read/write148 */149static inline u32 zynq_qspi_read(struct zynq_qspi *xqspi, u32 offset)150{151 return readl_relaxed(xqspi->regs + offset);152}153 154static inline void zynq_qspi_write(struct zynq_qspi *xqspi, u32 offset,155 u32 val)156{157 writel_relaxed(val, xqspi->regs + offset);158}159 160/**161 * zynq_qspi_init_hw - Initialize the hardware162 * @xqspi: Pointer to the zynq_qspi structure163 * @num_cs: Number of connected CS (to enable dual memories if needed)164 *165 * The default settings of the QSPI controller's configurable parameters on166 * reset are167 * - Host mode168 * - Baud rate divisor is set to 2169 * - Tx threshold set to 1l Rx threshold set to 32170 * - Flash memory interface mode enabled171 * - Size of the word to be transferred as 8 bit172 * This function performs the following actions173 * - Disable and clear all the interrupts174 * - Enable manual target select175 * - Enable manual start176 * - Deselect all the chip select lines177 * - Set the size of the word to be transferred as 32 bit178 * - Set the little endian mode of TX FIFO and179 * - Enable the QSPI controller180 */181static void zynq_qspi_init_hw(struct zynq_qspi *xqspi, unsigned int num_cs)182{183 u32 config_reg;184 185 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);186 zynq_qspi_write(xqspi, ZYNQ_QSPI_IDIS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);187 188 /* Disable linear mode as the boot loader may have used it */189 config_reg = 0;190 /* At the same time, enable dual mode if more than 1 CS is available */191 if (num_cs > 1)192 config_reg |= ZYNQ_QSPI_LCFG_TWO_MEM;193 194 zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);195 196 /* Clear the RX FIFO */197 while (zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET) &198 ZYNQ_QSPI_IXR_RXNEMTY_MASK)199 zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);200 201 zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, ZYNQ_QSPI_IXR_ALL_MASK);202 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);203 config_reg &= ~(ZYNQ_QSPI_CONFIG_MSTREN_MASK |204 ZYNQ_QSPI_CONFIG_CPOL_MASK |205 ZYNQ_QSPI_CONFIG_CPHA_MASK |206 ZYNQ_QSPI_CONFIG_BDRATE_MASK |207 ZYNQ_QSPI_CONFIG_SSFORCE_MASK |208 ZYNQ_QSPI_CONFIG_MANSRTEN_MASK |209 ZYNQ_QSPI_CONFIG_MANSRT_MASK);210 config_reg |= (ZYNQ_QSPI_CONFIG_MSTREN_MASK |211 ZYNQ_QSPI_CONFIG_SSFORCE_MASK |212 ZYNQ_QSPI_CONFIG_FWIDTH_MASK |213 ZYNQ_QSPI_CONFIG_IFMODE_MASK);214 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);215 216 zynq_qspi_write(xqspi, ZYNQ_QSPI_RX_THRESH_OFFSET,217 ZYNQ_QSPI_RX_THRESHOLD);218 zynq_qspi_write(xqspi, ZYNQ_QSPI_TX_THRESH_OFFSET,219 ZYNQ_QSPI_TX_THRESHOLD);220 221 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET,222 ZYNQ_QSPI_ENABLE_ENABLE_MASK);223}224 225static bool zynq_qspi_supports_op(struct spi_mem *mem,226 const struct spi_mem_op *op)227{228 if (!spi_mem_default_supports_op(mem, op))229 return false;230 231 /*232 * The number of address bytes should be equal to or less than 3 bytes.233 */234 if (op->addr.nbytes > 3)235 return false;236 237 return true;238}239 240/**241 * zynq_qspi_rxfifo_op - Read 1..4 bytes from RxFIFO to RX buffer242 * @xqspi: Pointer to the zynq_qspi structure243 * @size: Number of bytes to be read (1..4)244 */245static void zynq_qspi_rxfifo_op(struct zynq_qspi *xqspi, unsigned int size)246{247 u32 data;248 249 data = zynq_qspi_read(xqspi, ZYNQ_QSPI_RXD_OFFSET);250 251 if (xqspi->rxbuf) {252 memcpy(xqspi->rxbuf, ((u8 *)&data) + 4 - size, size);253 xqspi->rxbuf += size;254 }255 256 xqspi->rx_bytes -= size;257 if (xqspi->rx_bytes < 0)258 xqspi->rx_bytes = 0;259}260 261/**262 * zynq_qspi_txfifo_op - Write 1..4 bytes from TX buffer to TxFIFO263 * @xqspi: Pointer to the zynq_qspi structure264 * @size: Number of bytes to be written (1..4)265 */266static void zynq_qspi_txfifo_op(struct zynq_qspi *xqspi, unsigned int size)267{268 static const unsigned int offset[4] = {269 ZYNQ_QSPI_TXD_00_01_OFFSET, ZYNQ_QSPI_TXD_00_10_OFFSET,270 ZYNQ_QSPI_TXD_00_11_OFFSET, ZYNQ_QSPI_TXD_00_00_OFFSET };271 u32 data;272 273 if (xqspi->txbuf) {274 data = 0xffffffff;275 memcpy(&data, xqspi->txbuf, size);276 xqspi->txbuf += size;277 } else {278 data = 0;279 }280 281 xqspi->tx_bytes -= size;282 zynq_qspi_write(xqspi, offset[size - 1], data);283}284 285/**286 * zynq_qspi_chipselect - Select or deselect the chip select line287 * @spi: Pointer to the spi_device structure288 * @assert: 1 for select or 0 for deselect the chip select line289 */290static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)291{292 struct spi_controller *ctlr = spi->controller;293 struct zynq_qspi *xqspi = spi_controller_get_devdata(ctlr);294 u32 config_reg;295 296 /* Select the lower (CS0) or upper (CS1) memory */297 if (ctlr->num_chipselect > 1) {298 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET);299 if (!spi_get_chipselect(spi, 0))300 config_reg &= ~ZYNQ_QSPI_LCFG_U_PAGE;301 else302 config_reg |= ZYNQ_QSPI_LCFG_U_PAGE;303 304 zynq_qspi_write(xqspi, ZYNQ_QSPI_LINEAR_CFG_OFFSET, config_reg);305 }306 307 /* Ground the line to assert the CS */308 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);309 if (assert)310 config_reg &= ~ZYNQ_QSPI_CONFIG_PCS;311 else312 config_reg |= ZYNQ_QSPI_CONFIG_PCS;313 314 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);315}316 317/**318 * zynq_qspi_config_op - Configure QSPI controller for specified transfer319 * @xqspi: Pointer to the zynq_qspi structure320 * @spi: Pointer to the spi_device structure321 *322 * Sets the operational mode of QSPI controller for the next QSPI transfer and323 * sets the requested clock frequency.324 *325 * Return: 0 on success and -EINVAL on invalid input parameter326 *327 * Note: If the requested frequency is not an exact match with what can be328 * obtained using the prescalar value, the driver sets the clock frequency which329 * is lower than the requested frequency (maximum lower) for the transfer. If330 * the requested frequency is higher or lower than that is supported by the QSPI331 * controller the driver will set the highest or lowest frequency supported by332 * controller.333 */334static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi)335{336 u32 config_reg, baud_rate_val = 0;337 338 /*339 * Set the clock frequency340 * The baud rate divisor is not a direct mapping to the value written341 * into the configuration register (config_reg[5:3])342 * i.e. 000 - divide by 2343 * 001 - divide by 4344 * ----------------345 * 111 - divide by 256346 */347 while ((baud_rate_val < ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX) &&348 (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) >349 spi->max_speed_hz)350 baud_rate_val++;351 352 config_reg = zynq_qspi_read(xqspi, ZYNQ_QSPI_CONFIG_OFFSET);353 354 /* Set the QSPI clock phase and clock polarity */355 config_reg &= (~ZYNQ_QSPI_CONFIG_CPHA_MASK) &356 (~ZYNQ_QSPI_CONFIG_CPOL_MASK);357 if (spi->mode & SPI_CPHA)358 config_reg |= ZYNQ_QSPI_CONFIG_CPHA_MASK;359 if (spi->mode & SPI_CPOL)360 config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;361 362 config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK;363 config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT);364 zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);365 366 return 0;367}368 369/**370 * zynq_qspi_setup_op - Configure the QSPI controller371 * @spi: Pointer to the spi_device structure372 *373 * Sets the operational mode of QSPI controller for the next QSPI transfer, baud374 * rate and divisor value to setup the requested qspi clock.375 *376 * Return: 0 on success and error value on failure377 */378static int zynq_qspi_setup_op(struct spi_device *spi)379{380 struct spi_controller *ctlr = spi->controller;381 struct zynq_qspi *qspi = spi_controller_get_devdata(ctlr);382 383 if (ctlr->busy)384 return -EBUSY;385 386 clk_enable(qspi->refclk);387 clk_enable(qspi->pclk);388 zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET,389 ZYNQ_QSPI_ENABLE_ENABLE_MASK);390 391 return 0;392}393 394/**395 * zynq_qspi_write_op - Fills the TX FIFO with as many bytes as possible396 * @xqspi: Pointer to the zynq_qspi structure397 * @txcount: Maximum number of words to write398 * @txempty: Indicates that TxFIFO is empty399 */400static void zynq_qspi_write_op(struct zynq_qspi *xqspi, int txcount,401 bool txempty)402{403 int count, len, k;404 405 len = xqspi->tx_bytes;406 if (len && len < 4) {407 /*408 * We must empty the TxFIFO between accesses to TXD0,409 * TXD1, TXD2, TXD3.410 */411 if (txempty)412 zynq_qspi_txfifo_op(xqspi, len);413 414 return;415 }416 417 count = len / 4;418 if (count > txcount)419 count = txcount;420 421 if (xqspi->txbuf) {422 iowrite32_rep(xqspi->regs + ZYNQ_QSPI_TXD_00_00_OFFSET,423 xqspi->txbuf, count);424 xqspi->txbuf += count * 4;425 } else {426 for (k = 0; k < count; k++)427 writel_relaxed(0, xqspi->regs +428 ZYNQ_QSPI_TXD_00_00_OFFSET);429 }430 431 xqspi->tx_bytes -= count * 4;432}433 434/**435 * zynq_qspi_read_op - Drains the RX FIFO by as many bytes as possible436 * @xqspi: Pointer to the zynq_qspi structure437 * @rxcount: Maximum number of words to read438 */439static void zynq_qspi_read_op(struct zynq_qspi *xqspi, int rxcount)440{441 int count, len, k;442 443 len = xqspi->rx_bytes - xqspi->tx_bytes;444 count = len / 4;445 if (count > rxcount)446 count = rxcount;447 if (xqspi->rxbuf) {448 ioread32_rep(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET,449 xqspi->rxbuf, count);450 xqspi->rxbuf += count * 4;451 } else {452 for (k = 0; k < count; k++)453 readl_relaxed(xqspi->regs + ZYNQ_QSPI_RXD_OFFSET);454 }455 xqspi->rx_bytes -= count * 4;456 len -= count * 4;457 458 if (len && len < 4 && count < rxcount)459 zynq_qspi_rxfifo_op(xqspi, len);460}461 462/**463 * zynq_qspi_irq - Interrupt service routine of the QSPI controller464 * @irq: IRQ number465 * @dev_id: Pointer to the xqspi structure466 *467 * This function handles TX empty only.468 * On TX empty interrupt this function reads the received data from RX FIFO and469 * fills the TX FIFO if there is any data remaining to be transferred.470 *471 * Return: IRQ_HANDLED when interrupt is handled; IRQ_NONE otherwise.472 */473static irqreturn_t zynq_qspi_irq(int irq, void *dev_id)474{475 u32 intr_status;476 bool txempty;477 struct zynq_qspi *xqspi = (struct zynq_qspi *)dev_id;478 479 intr_status = zynq_qspi_read(xqspi, ZYNQ_QSPI_STATUS_OFFSET);480 zynq_qspi_write(xqspi, ZYNQ_QSPI_STATUS_OFFSET, intr_status);481 482 if ((intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK) ||483 (intr_status & ZYNQ_QSPI_IXR_RXNEMTY_MASK)) {484 /*485 * This bit is set when Tx FIFO has < THRESHOLD entries.486 * We have the THRESHOLD value set to 1,487 * so this bit indicates Tx FIFO is empty.488 */489 txempty = !!(intr_status & ZYNQ_QSPI_IXR_TXNFULL_MASK);490 /* Read out the data from the RX FIFO */491 zynq_qspi_read_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD);492 if (xqspi->tx_bytes) {493 /* There is more data to send */494 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_RX_THRESHOLD,495 txempty);496 } else {497 /*498 * If transfer and receive is completed then only send499 * complete signal.500 */501 if (!xqspi->rx_bytes) {502 zynq_qspi_write(xqspi,503 ZYNQ_QSPI_IDIS_OFFSET,504 ZYNQ_QSPI_IXR_RXTX_MASK);505 complete(&xqspi->data_completion);506 }507 }508 return IRQ_HANDLED;509 }510 511 return IRQ_NONE;512}513 514/**515 * zynq_qspi_exec_mem_op() - Initiates the QSPI transfer516 * @mem: the SPI memory517 * @op: the memory operation to execute518 *519 * Executes a memory operation.520 *521 * This function first selects the chip and starts the memory operation.522 *523 * Return: 0 in case of success, a negative error code otherwise.524 */525static int zynq_qspi_exec_mem_op(struct spi_mem *mem,526 const struct spi_mem_op *op)527{528 struct zynq_qspi *xqspi = spi_controller_get_devdata(mem->spi->controller);529 int err = 0, i;530 u8 *tmpbuf;531 532 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",533 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,534 op->dummy.buswidth, op->data.buswidth);535 536 zynq_qspi_chipselect(mem->spi, true);537 zynq_qspi_config_op(xqspi, mem->spi);538 539 if (op->cmd.opcode) {540 reinit_completion(&xqspi->data_completion);541 xqspi->txbuf = (u8 *)&op->cmd.opcode;542 xqspi->rxbuf = NULL;543 xqspi->tx_bytes = op->cmd.nbytes;544 xqspi->rx_bytes = op->cmd.nbytes;545 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);546 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,547 ZYNQ_QSPI_IXR_RXTX_MASK);548 if (!wait_for_completion_timeout(&xqspi->data_completion,549 msecs_to_jiffies(1000)))550 err = -ETIMEDOUT;551 }552 553 if (op->addr.nbytes) {554 for (i = 0; i < op->addr.nbytes; i++) {555 xqspi->txbuf[i] = op->addr.val >>556 (8 * (op->addr.nbytes - i - 1));557 }558 559 reinit_completion(&xqspi->data_completion);560 xqspi->rxbuf = NULL;561 xqspi->tx_bytes = op->addr.nbytes;562 xqspi->rx_bytes = op->addr.nbytes;563 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);564 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,565 ZYNQ_QSPI_IXR_RXTX_MASK);566 if (!wait_for_completion_timeout(&xqspi->data_completion,567 msecs_to_jiffies(1000)))568 err = -ETIMEDOUT;569 }570 571 if (op->dummy.nbytes) {572 tmpbuf = kmalloc(op->dummy.nbytes, GFP_KERNEL);573 if (!tmpbuf)574 return -ENOMEM;575 576 memset(tmpbuf, 0xff, op->dummy.nbytes);577 reinit_completion(&xqspi->data_completion);578 xqspi->txbuf = tmpbuf;579 xqspi->rxbuf = NULL;580 xqspi->tx_bytes = op->dummy.nbytes;581 xqspi->rx_bytes = op->dummy.nbytes;582 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);583 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,584 ZYNQ_QSPI_IXR_RXTX_MASK);585 if (!wait_for_completion_timeout(&xqspi->data_completion,586 msecs_to_jiffies(1000)))587 err = -ETIMEDOUT;588 589 kfree(tmpbuf);590 }591 592 if (op->data.nbytes) {593 reinit_completion(&xqspi->data_completion);594 if (op->data.dir == SPI_MEM_DATA_OUT) {595 xqspi->txbuf = (u8 *)op->data.buf.out;596 xqspi->tx_bytes = op->data.nbytes;597 xqspi->rxbuf = NULL;598 xqspi->rx_bytes = op->data.nbytes;599 } else {600 xqspi->txbuf = NULL;601 xqspi->rxbuf = (u8 *)op->data.buf.in;602 xqspi->rx_bytes = op->data.nbytes;603 xqspi->tx_bytes = op->data.nbytes;604 }605 606 zynq_qspi_write_op(xqspi, ZYNQ_QSPI_FIFO_DEPTH, true);607 zynq_qspi_write(xqspi, ZYNQ_QSPI_IEN_OFFSET,608 ZYNQ_QSPI_IXR_RXTX_MASK);609 if (!wait_for_completion_timeout(&xqspi->data_completion,610 msecs_to_jiffies(1000)))611 err = -ETIMEDOUT;612 }613 zynq_qspi_chipselect(mem->spi, false);614 615 return err;616}617 618static const struct spi_controller_mem_ops zynq_qspi_mem_ops = {619 .supports_op = zynq_qspi_supports_op,620 .exec_op = zynq_qspi_exec_mem_op,621};622 623/**624 * zynq_qspi_probe - Probe method for the QSPI driver625 * @pdev: Pointer to the platform_device structure626 *627 * This function initializes the driver data structures and the hardware.628 *629 * Return: 0 on success and error value on failure630 */631static int zynq_qspi_probe(struct platform_device *pdev)632{633 int ret = 0;634 struct spi_controller *ctlr;635 struct device *dev = &pdev->dev;636 struct device_node *np = dev->of_node;637 struct zynq_qspi *xqspi;638 u32 num_cs;639 640 ctlr = spi_alloc_host(&pdev->dev, sizeof(*xqspi));641 if (!ctlr)642 return -ENOMEM;643 644 xqspi = spi_controller_get_devdata(ctlr);645 xqspi->dev = dev;646 platform_set_drvdata(pdev, xqspi);647 xqspi->regs = devm_platform_ioremap_resource(pdev, 0);648 if (IS_ERR(xqspi->regs)) {649 ret = PTR_ERR(xqspi->regs);650 goto remove_ctlr;651 }652 653 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");654 if (IS_ERR(xqspi->pclk)) {655 dev_err(&pdev->dev, "pclk clock not found.\n");656 ret = PTR_ERR(xqspi->pclk);657 goto remove_ctlr;658 }659 660 init_completion(&xqspi->data_completion);661 662 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");663 if (IS_ERR(xqspi->refclk)) {664 dev_err(&pdev->dev, "ref_clk clock not found.\n");665 ret = PTR_ERR(xqspi->refclk);666 goto remove_ctlr;667 }668 669 ret = clk_prepare_enable(xqspi->pclk);670 if (ret) {671 dev_err(&pdev->dev, "Unable to enable APB clock.\n");672 goto remove_ctlr;673 }674 675 ret = clk_prepare_enable(xqspi->refclk);676 if (ret) {677 dev_err(&pdev->dev, "Unable to enable device clock.\n");678 goto clk_dis_pclk;679 }680 681 xqspi->irq = platform_get_irq(pdev, 0);682 if (xqspi->irq < 0) {683 ret = xqspi->irq;684 goto clk_dis_all;685 }686 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq,687 0, pdev->name, xqspi);688 if (ret != 0) {689 ret = -ENXIO;690 dev_err(&pdev->dev, "request_irq failed\n");691 goto clk_dis_all;692 }693 694 ret = of_property_read_u32(np, "num-cs",695 &num_cs);696 if (ret < 0) {697 ctlr->num_chipselect = 1;698 } else if (num_cs > ZYNQ_QSPI_MAX_NUM_CS) {699 ret = -EINVAL;700 dev_err(&pdev->dev, "only 2 chip selects are available\n");701 goto clk_dis_all;702 } else {703 ctlr->num_chipselect = num_cs;704 }705 706 ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |707 SPI_TX_DUAL | SPI_TX_QUAD;708 ctlr->mem_ops = &zynq_qspi_mem_ops;709 ctlr->setup = zynq_qspi_setup_op;710 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;711 ctlr->dev.of_node = np;712 713 /* QSPI controller initializations */714 zynq_qspi_init_hw(xqspi, ctlr->num_chipselect);715 716 ret = devm_spi_register_controller(&pdev->dev, ctlr);717 if (ret) {718 dev_err(&pdev->dev, "devm_spi_register_controller failed\n");719 goto clk_dis_all;720 }721 722 return ret;723 724clk_dis_all:725 clk_disable_unprepare(xqspi->refclk);726clk_dis_pclk:727 clk_disable_unprepare(xqspi->pclk);728remove_ctlr:729 spi_controller_put(ctlr);730 731 return ret;732}733 734/**735 * zynq_qspi_remove - Remove method for the QSPI driver736 * @pdev: Pointer to the platform_device structure737 *738 * This function is called if a device is physically removed from the system or739 * if the driver module is being unloaded. It frees all resources allocated to740 * the device.741 *742 * Return: 0 on success and error value on failure743 */744static void zynq_qspi_remove(struct platform_device *pdev)745{746 struct zynq_qspi *xqspi = platform_get_drvdata(pdev);747 748 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0);749 750 clk_disable_unprepare(xqspi->refclk);751 clk_disable_unprepare(xqspi->pclk);752}753 754static const struct of_device_id zynq_qspi_of_match[] = {755 { .compatible = "xlnx,zynq-qspi-1.0", },756 { /* end of table */ }757};758 759MODULE_DEVICE_TABLE(of, zynq_qspi_of_match);760 761/*762 * zynq_qspi_driver - This structure defines the QSPI platform driver763 */764static struct platform_driver zynq_qspi_driver = {765 .probe = zynq_qspi_probe,766 .remove_new = zynq_qspi_remove,767 .driver = {768 .name = "zynq-qspi",769 .of_match_table = zynq_qspi_of_match,770 },771};772 773module_platform_driver(zynq_qspi_driver);774 775MODULE_AUTHOR("Xilinx, Inc.");776MODULE_DESCRIPTION("Xilinx Zynq QSPI driver");777MODULE_LICENSE("GPL");778