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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver4 * (host mode only)5 *6 * Copyright (C) 2009 - 2015 Xilinx, Inc.7 */8 9#include <linux/clk.h>10#include <linux/delay.h>11#include <linux/dma-mapping.h>12#include <linux/dmaengine.h>13#include <linux/firmware/xlnx-zynqmp.h>14#include <linux/interrupt.h>15#include <linux/io.h>16#include <linux/module.h>17#include <linux/of.h>18#include <linux/platform_device.h>19#include <linux/pm_runtime.h>20#include <linux/spi/spi.h>21#include <linux/spinlock.h>22#include <linux/workqueue.h>23#include <linux/spi/spi-mem.h>24 25/* Generic QSPI register offsets */26#define GQSPI_CONFIG_OFST 0x0000010027#define GQSPI_ISR_OFST 0x0000010428#define GQSPI_IDR_OFST 0x0000010C29#define GQSPI_IER_OFST 0x0000010830#define GQSPI_IMASK_OFST 0x0000011031#define GQSPI_EN_OFST 0x0000011432#define GQSPI_TXD_OFST 0x0000011C33#define GQSPI_RXD_OFST 0x0000012034#define GQSPI_TX_THRESHOLD_OFST 0x0000012835#define GQSPI_RX_THRESHOLD_OFST 0x0000012C36#define IOU_TAPDLY_BYPASS_OFST 0x0000003C37#define GQSPI_LPBK_DLY_ADJ_OFST 0x0000013838#define GQSPI_GEN_FIFO_OFST 0x0000014039#define GQSPI_SEL_OFST 0x0000014440#define GQSPI_GF_THRESHOLD_OFST 0x0000015041#define GQSPI_FIFO_CTRL_OFST 0x0000014C42#define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C43#define GQSPI_QSPIDMA_DST_SIZE_OFST 0x0000080444#define GQSPI_QSPIDMA_DST_STS_OFST 0x0000080845#define GQSPI_QSPIDMA_DST_I_STS_OFST 0x0000081446#define GQSPI_QSPIDMA_DST_I_EN_OFST 0x0000081847#define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C48#define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x0000082049#define GQSPI_QSPIDMA_DST_ADDR_OFST 0x0000080050#define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x0000082851#define GQSPI_DATA_DLY_ADJ_OFST 0x000001F852 53/* GQSPI register bit masks */54#define GQSPI_SEL_MASK 0x0000000155#define GQSPI_EN_MASK 0x0000000156#define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x0000002057#define GQSPI_ISR_WR_TO_CLR_MASK 0x0000000258#define GQSPI_IDR_ALL_MASK 0x00000FBE59#define GQSPI_CFG_MODE_EN_MASK 0xC000000060#define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x2000000061#define GQSPI_CFG_ENDIAN_MASK 0x0400000062#define GQSPI_CFG_EN_POLL_TO_MASK 0x0010000063#define GQSPI_CFG_WP_HOLD_MASK 0x0008000064#define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x0000003865#define GQSPI_CFG_CLK_PHA_MASK 0x0000000466#define GQSPI_CFG_CLK_POL_MASK 0x0000000267#define GQSPI_CFG_START_GEN_FIFO_MASK 0x1000000068#define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF69#define GQSPI_GENFIFO_DATA_XFER 0x0000010070#define GQSPI_GENFIFO_EXP 0x0000020071#define GQSPI_GENFIFO_MODE_SPI 0x0000040072#define GQSPI_GENFIFO_MODE_DUALSPI 0x0000080073#define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C0074#define GQSPI_GENFIFO_MODE_MASK 0x00000C0075#define GQSPI_GENFIFO_CS_LOWER 0x0000100076#define GQSPI_GENFIFO_CS_UPPER 0x0000200077#define GQSPI_GENFIFO_BUS_LOWER 0x0000400078#define GQSPI_GENFIFO_BUS_UPPER 0x0000800079#define GQSPI_GENFIFO_BUS_BOTH 0x0000C00080#define GQSPI_GENFIFO_BUS_MASK 0x0000C00081#define GQSPI_GENFIFO_TX 0x0001000082#define GQSPI_GENFIFO_RX 0x0002000083#define GQSPI_GENFIFO_STRIPE 0x0004000084#define GQSPI_GENFIFO_POLL 0x0008000085#define GQSPI_GENFIFO_EXP_START 0x0000010086#define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x0000000487#define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x0000000288#define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x0000000189#define GQSPI_ISR_RXEMPTY_MASK 0x0000080090#define GQSPI_ISR_GENFIFOFULL_MASK 0x0000040091#define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x0000020092#define GQSPI_ISR_TXEMPTY_MASK 0x0000010093#define GQSPI_ISR_GENFIFOEMPTY_MASK 0x0000008094#define GQSPI_ISR_RXFULL_MASK 0x0000002095#define GQSPI_ISR_RXNEMPTY_MASK 0x0000001096#define GQSPI_ISR_TXFULL_MASK 0x0000000897#define GQSPI_ISR_TXNOT_FULL_MASK 0x0000000498#define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x0000000299#define GQSPI_IER_TXNOT_FULL_MASK 0x00000004100#define GQSPI_IER_RXEMPTY_MASK 0x00000800101#define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002102#define GQSPI_IER_RXNEMPTY_MASK 0x00000010103#define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080104#define GQSPI_IER_TXEMPTY_MASK 0x00000100105#define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE106#define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000107#define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000108#define GQSPI_ISR_IDR_MASK 0x00000994109#define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002110#define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002111#define GQSPI_IRQ_MASK 0x00000980112 113#define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3114#define GQSPI_GENFIFO_CS_SETUP 0x4115#define GQSPI_GENFIFO_CS_HOLD 0x3116#define GQSPI_TXD_DEPTH 64117#define GQSPI_RX_FIFO_THRESHOLD 32118#define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)119#define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32120#define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\121 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)122#define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10123#define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00124#define GQSPI_SELECT_FLASH_CS_LOWER 0x1125#define GQSPI_SELECT_FLASH_CS_UPPER 0x2126#define GQSPI_SELECT_FLASH_CS_BOTH 0x3127#define GQSPI_SELECT_FLASH_BUS_LOWER 0x1128#define GQSPI_SELECT_FLASH_BUS_UPPER 0x2129#define GQSPI_SELECT_FLASH_BUS_BOTH 0x3130#define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */131#define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */132#define GQSPI_SELECT_MODE_SPI 0x1133#define GQSPI_SELECT_MODE_DUALSPI 0x2134#define GQSPI_SELECT_MODE_QUADSPI 0x4135#define GQSPI_DMA_UNALIGN 0x3136#define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */137 138#define GQSPI_MAX_NUM_CS 2 /* Maximum number of chip selects */139 140#define GQSPI_USE_DATA_DLY 0x1141#define GQSPI_USE_DATA_DLY_SHIFT 31142#define GQSPI_DATA_DLY_ADJ_VALUE 0x2143#define GQSPI_DATA_DLY_ADJ_SHIFT 28144#define GQSPI_LPBK_DLY_ADJ_DLY_1 0x1145#define GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT 0x3146#define TAP_DLY_BYPASS_LQSPI_RX_VALUE 0x1147#define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 0x2148 149/* set to differentiate versal from zynqmp, 1=versal, 0=zynqmp */150#define QSPI_QUIRK_HAS_TAPDELAY BIT(0)151 152#define GQSPI_FREQ_37_5MHZ 37500000153#define GQSPI_FREQ_40MHZ 40000000154#define GQSPI_FREQ_100MHZ 100000000155#define GQSPI_FREQ_150MHZ 150000000156 157#define SPI_AUTOSUSPEND_TIMEOUT 3000158enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};159 160/**161 * struct qspi_platform_data - zynqmp qspi platform data structure162 * @quirks: Flags is used to identify the platform163 */164struct qspi_platform_data {165 u32 quirks;166};167 168/**169 * struct zynqmp_qspi - Defines qspi driver instance170 * @ctlr: Pointer to the spi controller information171 * @regs: Virtual address of the QSPI controller registers172 * @refclk: Pointer to the peripheral clock173 * @pclk: Pointer to the APB clock174 * @irq: IRQ number175 * @dev: Pointer to struct device176 * @txbuf: Pointer to the TX buffer177 * @rxbuf: Pointer to the RX buffer178 * @bytes_to_transfer: Number of bytes left to transfer179 * @bytes_to_receive: Number of bytes left to receive180 * @genfifocs: Used for chip select181 * @genfifobus: Used to select the upper or lower bus182 * @dma_rx_bytes: Remaining bytes to receive by DMA mode183 * @dma_addr: DMA address after mapping the kernel buffer184 * @genfifoentry: Used for storing the genfifoentry instruction.185 * @mode: Defines the mode in which QSPI is operating186 * @data_completion: completion structure187 * @op_lock: Operational lock188 * @speed_hz: Current SPI bus clock speed in hz189 * @has_tapdelay: Used for tapdelay register available in qspi190 */191struct zynqmp_qspi {192 struct spi_controller *ctlr;193 void __iomem *regs;194 struct clk *refclk;195 struct clk *pclk;196 int irq;197 struct device *dev;198 const void *txbuf;199 void *rxbuf;200 int bytes_to_transfer;201 int bytes_to_receive;202 u32 genfifocs;203 u32 genfifobus;204 u32 dma_rx_bytes;205 dma_addr_t dma_addr;206 u32 genfifoentry;207 enum mode_type mode;208 struct completion data_completion;209 struct mutex op_lock;210 u32 speed_hz;211 bool has_tapdelay;212};213 214/**215 * zynqmp_gqspi_read - For GQSPI controller read operation216 * @xqspi: Pointer to the zynqmp_qspi structure217 * @offset: Offset from where to read218 * Return: Value at the offset219 */220static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)221{222 return readl_relaxed(xqspi->regs + offset);223}224 225/**226 * zynqmp_gqspi_write - For GQSPI controller write operation227 * @xqspi: Pointer to the zynqmp_qspi structure228 * @offset: Offset where to write229 * @val: Value to be written230 */231static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,232 u32 val)233{234 writel_relaxed(val, (xqspi->regs + offset));235}236 237/**238 * zynqmp_gqspi_selecttarget - For selection of target device239 * @instanceptr: Pointer to the zynqmp_qspi structure240 * @targetcs: For chip select241 * @targetbus: To check which bus is selected- upper or lower242 */243static void zynqmp_gqspi_selecttarget(struct zynqmp_qspi *instanceptr,244 u8 targetcs, u8 targetbus)245{246 /*247 * Bus and CS lines selected here will be updated in the instance and248 * used for subsequent GENFIFO entries during transfer.249 */250 251 /* Choose target select line */252 switch (targetcs) {253 case GQSPI_SELECT_FLASH_CS_BOTH:254 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |255 GQSPI_GENFIFO_CS_UPPER;256 break;257 case GQSPI_SELECT_FLASH_CS_UPPER:258 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;259 break;260 case GQSPI_SELECT_FLASH_CS_LOWER:261 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;262 break;263 default:264 dev_warn(instanceptr->dev, "Invalid target select\n");265 }266 267 /* Choose the bus */268 switch (targetbus) {269 case GQSPI_SELECT_FLASH_BUS_BOTH:270 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |271 GQSPI_GENFIFO_BUS_UPPER;272 break;273 case GQSPI_SELECT_FLASH_BUS_UPPER:274 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;275 break;276 case GQSPI_SELECT_FLASH_BUS_LOWER:277 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;278 break;279 default:280 dev_warn(instanceptr->dev, "Invalid target bus\n");281 }282}283 284/**285 * zynqmp_qspi_set_tapdelay: To configure qspi tap delays286 * @xqspi: Pointer to the zynqmp_qspi structure287 * @baudrateval: Buadrate to configure288 */289static void zynqmp_qspi_set_tapdelay(struct zynqmp_qspi *xqspi, u32 baudrateval)290{291 u32 tapdlybypass = 0, lpbkdlyadj = 0, datadlyadj = 0, clk_rate;292 u32 reqhz = 0;293 294 clk_rate = clk_get_rate(xqspi->refclk);295 reqhz = (clk_rate / (GQSPI_BAUD_DIV_SHIFT << baudrateval));296 297 if (!xqspi->has_tapdelay) {298 if (reqhz <= GQSPI_FREQ_40MHZ) {299 zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,300 PM_TAPDELAY_BYPASS_ENABLE);301 } else if (reqhz <= GQSPI_FREQ_100MHZ) {302 zynqmp_pm_set_tapdelay_bypass(PM_TAPDELAY_QSPI,303 PM_TAPDELAY_BYPASS_ENABLE);304 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);305 datadlyadj |= ((GQSPI_USE_DATA_DLY <<306 GQSPI_USE_DATA_DLY_SHIFT)307 | (GQSPI_DATA_DLY_ADJ_VALUE <<308 GQSPI_DATA_DLY_ADJ_SHIFT));309 } else if (reqhz <= GQSPI_FREQ_150MHZ) {310 lpbkdlyadj |= GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK;311 }312 } else {313 if (reqhz <= GQSPI_FREQ_37_5MHZ) {314 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<315 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);316 } else if (reqhz <= GQSPI_FREQ_100MHZ) {317 tapdlybypass |= (TAP_DLY_BYPASS_LQSPI_RX_VALUE <<318 TAP_DLY_BYPASS_LQSPI_RX_SHIFT);319 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);320 datadlyadj |= (GQSPI_USE_DATA_DLY <<321 GQSPI_USE_DATA_DLY_SHIFT);322 } else if (reqhz <= GQSPI_FREQ_150MHZ) {323 lpbkdlyadj |= (GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK324 | (GQSPI_LPBK_DLY_ADJ_DLY_1 <<325 GQSPI_LPBK_DLY_ADJ_DLY_1_SHIFT));326 }327 zynqmp_gqspi_write(xqspi,328 IOU_TAPDLY_BYPASS_OFST, tapdlybypass);329 }330 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, lpbkdlyadj);331 zynqmp_gqspi_write(xqspi, GQSPI_DATA_DLY_ADJ_OFST, datadlyadj);332}333 334/**335 * zynqmp_qspi_init_hw - Initialize the hardware336 * @xqspi: Pointer to the zynqmp_qspi structure337 *338 * The default settings of the QSPI controller's configurable parameters on339 * reset are340 * - Host mode341 * - TX threshold set to 1342 * - RX threshold set to 1343 * - Flash memory interface mode enabled344 * This function performs the following actions345 * - Disable and clear all the interrupts346 * - Enable manual target select347 * - Enable manual start348 * - Deselect all the chip select lines349 * - Set the little endian mode of TX FIFO350 * - Set clock phase351 * - Set clock polarity and352 * - Enable the QSPI controller353 */354static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)355{356 u32 config_reg, baud_rate_val = 0;357 ulong clk_rate;358 359 /* Select the GQSPI mode */360 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);361 /* Clear and disable interrupts */362 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,363 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |364 GQSPI_ISR_WR_TO_CLR_MASK);365 /* Clear the DMA STS */366 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,367 zynqmp_gqspi_read(xqspi,368 GQSPI_QSPIDMA_DST_I_STS_OFST));369 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,370 zynqmp_gqspi_read(xqspi,371 GQSPI_QSPIDMA_DST_STS_OFST) |372 GQSPI_QSPIDMA_DST_STS_WTC);373 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);374 zynqmp_gqspi_write(xqspi,375 GQSPI_QSPIDMA_DST_I_DIS_OFST,376 GQSPI_QSPIDMA_DST_INTR_ALL_MASK);377 /* Disable the GQSPI */378 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);379 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);380 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;381 /* Manual start */382 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;383 /* Little endian by default */384 config_reg &= ~GQSPI_CFG_ENDIAN_MASK;385 /* Disable poll time out */386 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;387 /* Set hold bit */388 config_reg |= GQSPI_CFG_WP_HOLD_MASK;389 /* Clear pre-scalar by default */390 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;391 /* Set CPHA */392 if (xqspi->ctlr->mode_bits & SPI_CPHA)393 config_reg |= GQSPI_CFG_CLK_PHA_MASK;394 else395 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;396 /* Set CPOL */397 if (xqspi->ctlr->mode_bits & SPI_CPOL)398 config_reg |= GQSPI_CFG_CLK_POL_MASK;399 else400 config_reg &= ~GQSPI_CFG_CLK_POL_MASK;401 402 /* Set the clock frequency */403 clk_rate = clk_get_rate(xqspi->refclk);404 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&405 (clk_rate /406 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > xqspi->speed_hz)407 baud_rate_val++;408 409 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;410 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);411 412 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);413 414 /* Set the tapdelay for clock frequency */415 zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);416 417 /* Clear the TX and RX FIFO */418 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,419 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |420 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |421 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);422 /* Reset thresholds */423 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,424 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);425 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,426 GQSPI_RX_FIFO_THRESHOLD);427 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,428 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);429 zynqmp_gqspi_selecttarget(xqspi,430 GQSPI_SELECT_FLASH_CS_LOWER,431 GQSPI_SELECT_FLASH_BUS_LOWER);432 /* Initialize DMA */433 zynqmp_gqspi_write(xqspi,434 GQSPI_QSPIDMA_DST_CTRL_OFST,435 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);436 437 /* Enable the GQSPI */438 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);439}440 441/**442 * zynqmp_qspi_copy_read_data - Copy data to RX buffer443 * @xqspi: Pointer to the zynqmp_qspi structure444 * @data: The variable where data is stored445 * @size: Number of bytes to be copied from data to RX buffer446 */447static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,448 ulong data, u8 size)449{450 memcpy(xqspi->rxbuf, &data, size);451 xqspi->rxbuf += size;452 xqspi->bytes_to_receive -= size;453}454 455/**456 * zynqmp_qspi_chipselect - Select or deselect the chip select line457 * @qspi: Pointer to the spi_device structure458 * @is_high: Select(0) or deselect (1) the chip select line459 */460static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)461{462 struct zynqmp_qspi *xqspi = spi_controller_get_devdata(qspi->controller);463 ulong timeout;464 u32 genfifoentry = 0, statusreg;465 466 genfifoentry |= GQSPI_GENFIFO_MODE_SPI;467 468 if (!is_high) {469 if (!spi_get_chipselect(qspi, 0)) {470 xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER;471 xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER;472 } else {473 xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER;474 xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER;475 }476 genfifoentry |= xqspi->genfifobus;477 genfifoentry |= xqspi->genfifocs;478 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;479 } else {480 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;481 }482 483 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);484 485 /* Manually start the generic FIFO command */486 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,487 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |488 GQSPI_CFG_START_GEN_FIFO_MASK);489 490 timeout = jiffies + msecs_to_jiffies(1000);491 492 /* Wait until the generic FIFO command is empty */493 do {494 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);495 496 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&497 (statusreg & GQSPI_ISR_TXEMPTY_MASK))498 break;499 cpu_relax();500 } while (!time_after_eq(jiffies, timeout));501 502 if (time_after_eq(jiffies, timeout))503 dev_err(xqspi->dev, "Chip select timed out\n");504}505 506/**507 * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4.508 * @xqspi: xqspi is a pointer to the GQSPI instance509 * @spimode: spimode - SPI or DUAL or QUAD.510 * Return: Mask to set desired SPI mode in GENFIFO entry.511 */512static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,513 u8 spimode)514{515 u32 mask = 0;516 517 switch (spimode) {518 case GQSPI_SELECT_MODE_DUALSPI:519 mask = GQSPI_GENFIFO_MODE_DUALSPI;520 break;521 case GQSPI_SELECT_MODE_QUADSPI:522 mask = GQSPI_GENFIFO_MODE_QUADSPI;523 break;524 case GQSPI_SELECT_MODE_SPI:525 mask = GQSPI_GENFIFO_MODE_SPI;526 break;527 default:528 dev_warn(xqspi->dev, "Invalid SPI mode\n");529 }530 531 return mask;532}533 534/**535 * zynqmp_qspi_config_op - Configure QSPI controller for specified536 * transfer537 * @xqspi: Pointer to the zynqmp_qspi structure538 * @qspi: Pointer to the spi_device structure539 *540 * Sets the operational mode of QSPI controller for the next QSPI transfer and541 * sets the requested clock frequency.542 *543 * Return: Always 0544 *545 * Note:546 * If the requested frequency is not an exact match with what can be547 * obtained using the pre-scalar value, the driver sets the clock548 * frequency which is lower than the requested frequency (maximum lower)549 * for the transfer.550 *551 * If the requested frequency is higher or lower than that is supported552 * by the QSPI controller the driver will set the highest or lowest553 * frequency supported by controller.554 */555static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi,556 struct spi_device *qspi)557{558 ulong clk_rate;559 u32 config_reg, req_speed_hz, baud_rate_val = 0;560 561 req_speed_hz = qspi->max_speed_hz;562 563 if (xqspi->speed_hz != req_speed_hz) {564 xqspi->speed_hz = req_speed_hz;565 566 /* Set the clock frequency */567 /* If req_speed_hz == 0, default to lowest speed */568 clk_rate = clk_get_rate(xqspi->refclk);569 570 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&571 (clk_rate /572 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) >573 req_speed_hz)574 baud_rate_val++;575 576 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);577 578 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;579 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);580 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);581 zynqmp_qspi_set_tapdelay(xqspi, baud_rate_val);582 }583 return 0;584}585 586/**587 * zynqmp_qspi_setup_op - Configure the QSPI controller588 * @qspi: Pointer to the spi_device structure589 *590 * Sets the operational mode of QSPI controller for the next QSPI transfer,591 * baud rate and divisor value to setup the requested qspi clock.592 *593 * Return: 0 on success; error value otherwise.594 */595static int zynqmp_qspi_setup_op(struct spi_device *qspi)596{597 struct spi_controller *ctlr = qspi->controller;598 struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr);599 600 if (ctlr->busy)601 return -EBUSY;602 603 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);604 605 return 0;606}607 608/**609 * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in610 * the FIFO or the bytes required to be611 * transmitted.612 * @xqspi: Pointer to the zynqmp_qspi structure613 * @size: Number of bytes to be copied from TX buffer to TX FIFO614 */615static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)616{617 u32 count = 0, intermediate;618 619 while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) {620 if (xqspi->bytes_to_transfer >= 4) {621 memcpy(&intermediate, xqspi->txbuf, 4);622 xqspi->txbuf += 4;623 xqspi->bytes_to_transfer -= 4;624 count += 4;625 } else {626 memcpy(&intermediate, xqspi->txbuf,627 xqspi->bytes_to_transfer);628 xqspi->txbuf += xqspi->bytes_to_transfer;629 xqspi->bytes_to_transfer = 0;630 count += xqspi->bytes_to_transfer;631 }632 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);633 }634}635 636/**637 * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in638 * the FIFO.639 * @xqspi: Pointer to the zynqmp_qspi structure640 * @size: Number of bytes to be copied from RX buffer to RX FIFO641 */642static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)643{644 ulong data;645 int count = 0;646 647 while ((count < size) && (xqspi->bytes_to_receive > 0)) {648 if (xqspi->bytes_to_receive >= 4) {649 (*(u32 *)xqspi->rxbuf) =650 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);651 xqspi->rxbuf += 4;652 xqspi->bytes_to_receive -= 4;653 count += 4;654 } else {655 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);656 count += xqspi->bytes_to_receive;657 zynqmp_qspi_copy_read_data(xqspi, data,658 xqspi->bytes_to_receive);659 xqspi->bytes_to_receive = 0;660 }661 }662}663 664/**665 * zynqmp_qspi_fillgenfifo - Fills the GENFIFO.666 * @xqspi: Pointer to the zynqmp_qspi structure667 * @nbits: Transfer/Receive buswidth.668 * @genfifoentry: Variable in which GENFIFO mask is saved669 */670static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits,671 u32 genfifoentry)672{673 u32 transfer_len = 0;674 675 if (xqspi->txbuf) {676 genfifoentry &= ~GQSPI_GENFIFO_RX;677 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;678 genfifoentry |= GQSPI_GENFIFO_TX;679 transfer_len = xqspi->bytes_to_transfer;680 } else if (xqspi->rxbuf) {681 genfifoentry &= ~GQSPI_GENFIFO_TX;682 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;683 genfifoentry |= GQSPI_GENFIFO_RX;684 if (xqspi->mode == GQSPI_MODE_DMA)685 transfer_len = xqspi->dma_rx_bytes;686 else687 transfer_len = xqspi->bytes_to_receive;688 } else {689 /* Sending dummy circles here */690 genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX);691 genfifoentry |= GQSPI_GENFIFO_DATA_XFER;692 transfer_len = xqspi->bytes_to_transfer;693 }694 genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits);695 xqspi->genfifoentry = genfifoentry;696 697 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {698 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;699 genfifoentry |= transfer_len;700 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);701 } else {702 int tempcount = transfer_len;703 u32 exponent = 8; /* 2^8 = 256 */704 u8 imm_data = tempcount & 0xFF;705 706 tempcount &= ~(tempcount & 0xFF);707 /* Immediate entry */708 if (tempcount != 0) {709 /* Exponent entries */710 genfifoentry |= GQSPI_GENFIFO_EXP;711 while (tempcount != 0) {712 if (tempcount & GQSPI_GENFIFO_EXP_START) {713 genfifoentry &=714 ~GQSPI_GENFIFO_IMM_DATA_MASK;715 genfifoentry |= exponent;716 zynqmp_gqspi_write(xqspi,717 GQSPI_GEN_FIFO_OFST,718 genfifoentry);719 }720 tempcount = tempcount >> 1;721 exponent++;722 }723 }724 if (imm_data != 0) {725 genfifoentry &= ~GQSPI_GENFIFO_EXP;726 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;727 genfifoentry |= (u8)(imm_data & 0xFF);728 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST,729 genfifoentry);730 }731 }732 if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) {733 /* Dummy generic FIFO entry */734 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);735 }736}737 738/**739 * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI740 * controller741 * @xqspi: zynqmp_qspi instance pointer742 *743 * This function handles DMA interrupt only.744 */745static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)746{747 u32 config_reg, genfifoentry;748 749 dma_unmap_single(xqspi->dev, xqspi->dma_addr,750 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);751 xqspi->rxbuf += xqspi->dma_rx_bytes;752 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;753 xqspi->dma_rx_bytes = 0;754 755 /* Disabling the DMA interrupts */756 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,757 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);758 759 if (xqspi->bytes_to_receive > 0) {760 /* Switch to IO mode,for remaining bytes to receive */761 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);762 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;763 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);764 765 /* Initiate the transfer of remaining bytes */766 genfifoentry = xqspi->genfifoentry;767 genfifoentry |= xqspi->bytes_to_receive;768 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);769 770 /* Dummy generic FIFO entry */771 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);772 773 /* Manual start */774 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,775 (zynqmp_gqspi_read(xqspi,776 GQSPI_CONFIG_OFST) |777 GQSPI_CFG_START_GEN_FIFO_MASK));778 779 /* Enable the RX interrupts for IO mode */780 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,781 GQSPI_IER_GENFIFOEMPTY_MASK |782 GQSPI_IER_RXNEMPTY_MASK |783 GQSPI_IER_RXEMPTY_MASK);784 }785}786 787/**788 * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller789 * @irq: IRQ number790 * @dev_id: Pointer to the xqspi structure791 *792 * This function handles TX empty only.793 * On TX empty interrupt this function reads the received data from RX FIFO794 * and fills the TX FIFO if there is any data remaining to be transferred.795 *796 * Return: IRQ_HANDLED when interrupt is handled797 * IRQ_NONE otherwise.798 */799static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)800{801 struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id;802 irqreturn_t ret = IRQ_NONE;803 u32 status, mask, dma_status = 0;804 805 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);806 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);807 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));808 809 /* Read and clear DMA status */810 if (xqspi->mode == GQSPI_MODE_DMA) {811 dma_status =812 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);813 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,814 dma_status);815 }816 817 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {818 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);819 ret = IRQ_HANDLED;820 }821 822 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {823 zynqmp_process_dma_irq(xqspi);824 ret = IRQ_HANDLED;825 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&826 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {827 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);828 ret = IRQ_HANDLED;829 }830 831 if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 &&832 ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {833 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);834 complete(&xqspi->data_completion);835 ret = IRQ_HANDLED;836 }837 return ret;838}839 840/**841 * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation842 * @xqspi: xqspi is a pointer to the GQSPI instance.843 *844 * Return: 0 on success; error value otherwise.845 */846static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi)847{848 u32 rx_bytes, rx_rem, config_reg;849 dma_addr_t addr;850 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;851 852 if (xqspi->bytes_to_receive < 8 ||853 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {854 /* Setting to IO mode */855 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);856 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;857 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);858 xqspi->mode = GQSPI_MODE_IO;859 xqspi->dma_rx_bytes = 0;860 return 0;861 }862 863 rx_rem = xqspi->bytes_to_receive % 4;864 rx_bytes = (xqspi->bytes_to_receive - rx_rem);865 866 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,867 rx_bytes, DMA_FROM_DEVICE);868 if (dma_mapping_error(xqspi->dev, addr)) {869 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");870 return -ENOMEM;871 }872 873 xqspi->dma_rx_bytes = rx_bytes;874 xqspi->dma_addr = addr;875 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,876 (u32)(addr & 0xffffffff));877 addr = ((addr >> 16) >> 16);878 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,879 ((u32)addr) & 0xfff);880 881 /* Enabling the DMA mode */882 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);883 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;884 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;885 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);886 887 /* Switch to DMA mode */888 xqspi->mode = GQSPI_MODE_DMA;889 890 /* Write the number of bytes to transfer */891 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);892 893 return 0;894}895 896/**897 * zynqmp_qspi_write_op - This function sets up the GENFIFO entries,898 * TX FIFO, and fills the TX FIFO with as many899 * bytes as possible.900 * @xqspi: Pointer to the GQSPI instance.901 * @tx_nbits: Transfer buswidth.902 * @genfifoentry: Variable in which GENFIFO mask is returned903 * to calling function904 */905static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits,906 u32 genfifoentry)907{908 u32 config_reg;909 910 zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry);911 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);912 if (xqspi->mode == GQSPI_MODE_DMA) {913 config_reg = zynqmp_gqspi_read(xqspi,914 GQSPI_CONFIG_OFST);915 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;916 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,917 config_reg);918 xqspi->mode = GQSPI_MODE_IO;919 }920}921 922/**923 * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and924 * RX DMA operation.925 * @xqspi: xqspi is a pointer to the GQSPI instance.926 * @rx_nbits: Receive buswidth.927 * @genfifoentry: genfifoentry is pointer to the variable in which928 * GENFIFO mask is returned to calling function929 *930 * Return: 0 on success; error value otherwise.931 */932static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits,933 u32 genfifoentry)934{935 int ret;936 937 ret = zynqmp_qspi_setuprxdma(xqspi);938 if (ret)939 return ret;940 zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry);941 942 return 0;943}944 945/**946 * zynqmp_qspi_suspend - Suspend method for the QSPI driver947 * @dev: Address of the platform_device structure948 *949 * This function stops the QSPI driver queue and disables the QSPI controller950 *951 * Return: Always 0952 */953static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)954{955 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);956 struct spi_controller *ctlr = xqspi->ctlr;957 int ret;958 959 ret = spi_controller_suspend(ctlr);960 if (ret)961 return ret;962 963 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);964 965 return 0;966}967 968/**969 * zynqmp_qspi_resume - Resume method for the QSPI driver970 * @dev: Address of the platform_device structure971 *972 * The function starts the QSPI driver queue and initializes the QSPI973 * controller974 *975 * Return: 0 on success; error value otherwise976 */977static int __maybe_unused zynqmp_qspi_resume(struct device *dev)978{979 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);980 struct spi_controller *ctlr = xqspi->ctlr;981 982 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);983 984 spi_controller_resume(ctlr);985 986 return 0;987}988 989/**990 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver991 * @dev: Address of the platform_device structure992 *993 * This function disables the clocks994 *995 * Return: Always 0996 */997static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)998{999 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);1000 1001 clk_disable_unprepare(xqspi->refclk);1002 clk_disable_unprepare(xqspi->pclk);1003 1004 return 0;1005}1006 1007/**1008 * zynqmp_runtime_resume - Runtime resume method for the SPI driver1009 * @dev: Address of the platform_device structure1010 *1011 * This function enables the clocks1012 *1013 * Return: 0 on success and error value on error1014 */1015static int __maybe_unused zynqmp_runtime_resume(struct device *dev)1016{1017 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev);1018 int ret;1019 1020 ret = clk_prepare_enable(xqspi->pclk);1021 if (ret) {1022 dev_err(dev, "Cannot enable APB clock.\n");1023 return ret;1024 }1025 1026 ret = clk_prepare_enable(xqspi->refclk);1027 if (ret) {1028 dev_err(dev, "Cannot enable device clock.\n");1029 clk_disable_unprepare(xqspi->pclk);1030 return ret;1031 }1032 1033 return 0;1034}1035 1036static unsigned long zynqmp_qspi_timeout(struct zynqmp_qspi *xqspi, u8 bits,1037 unsigned long bytes)1038{1039 unsigned long timeout;1040 1041 /* Assume we are at most 2x slower than the nominal bus speed */1042 timeout = mult_frac(bytes, 2 * 8 * MSEC_PER_SEC,1043 bits * xqspi->speed_hz);1044 /* And add 100 ms for scheduling delays */1045 return msecs_to_jiffies(timeout + 100);1046}1047 1048/**1049 * zynqmp_qspi_exec_op() - Initiates the QSPI transfer1050 * @mem: The SPI memory1051 * @op: The memory operation to execute1052 *1053 * Executes a memory operation.1054 *1055 * This function first selects the chip and starts the memory operation.1056 *1057 * Return: 0 in case of success, a negative error code otherwise.1058 */1059static int zynqmp_qspi_exec_op(struct spi_mem *mem,1060 const struct spi_mem_op *op)1061{1062 struct zynqmp_qspi *xqspi = spi_controller_get_devdata1063 (mem->spi->controller);1064 unsigned long timeout;1065 int err = 0, i;1066 u32 genfifoentry = 0;1067 u16 opcode = op->cmd.opcode;1068 u64 opaddr;1069 1070 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n",1071 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,1072 op->dummy.buswidth, op->data.buswidth);1073 1074 mutex_lock(&xqspi->op_lock);1075 zynqmp_qspi_config_op(xqspi, mem->spi);1076 zynqmp_qspi_chipselect(mem->spi, false);1077 genfifoentry |= xqspi->genfifocs;1078 genfifoentry |= xqspi->genfifobus;1079 1080 if (op->cmd.opcode) {1081 reinit_completion(&xqspi->data_completion);1082 xqspi->txbuf = &opcode;1083 xqspi->rxbuf = NULL;1084 xqspi->bytes_to_transfer = op->cmd.nbytes;1085 xqspi->bytes_to_receive = 0;1086 zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry);1087 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,1088 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |1089 GQSPI_CFG_START_GEN_FIFO_MASK);1090 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,1091 GQSPI_IER_GENFIFOEMPTY_MASK |1092 GQSPI_IER_TXNOT_FULL_MASK);1093 timeout = zynqmp_qspi_timeout(xqspi, op->cmd.buswidth,1094 op->cmd.nbytes);1095 if (!wait_for_completion_timeout(&xqspi->data_completion,1096 timeout)) {1097 err = -ETIMEDOUT;1098 goto return_err;1099 }1100 }1101 1102 if (op->addr.nbytes) {1103 xqspi->txbuf = &opaddr;1104 for (i = 0; i < op->addr.nbytes; i++) {1105 *(((u8 *)xqspi->txbuf) + i) = op->addr.val >>1106 (8 * (op->addr.nbytes - i - 1));1107 }1108 1109 reinit_completion(&xqspi->data_completion);1110 xqspi->rxbuf = NULL;1111 xqspi->bytes_to_transfer = op->addr.nbytes;1112 xqspi->bytes_to_receive = 0;1113 zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry);1114 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,1115 zynqmp_gqspi_read(xqspi,1116 GQSPI_CONFIG_OFST) |1117 GQSPI_CFG_START_GEN_FIFO_MASK);1118 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,1119 GQSPI_IER_TXEMPTY_MASK |1120 GQSPI_IER_GENFIFOEMPTY_MASK |1121 GQSPI_IER_TXNOT_FULL_MASK);1122 timeout = zynqmp_qspi_timeout(xqspi, op->addr.buswidth,1123 op->addr.nbytes);1124 if (!wait_for_completion_timeout(&xqspi->data_completion,1125 timeout)) {1126 err = -ETIMEDOUT;1127 goto return_err;1128 }1129 }1130 1131 if (op->dummy.nbytes) {1132 xqspi->txbuf = NULL;1133 xqspi->rxbuf = NULL;1134 /*1135 * xqspi->bytes_to_transfer here represents the dummy circles1136 * which need to be sent.1137 */1138 xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth;1139 xqspi->bytes_to_receive = 0;1140 /*1141 * Using op->data.buswidth instead of op->dummy.buswidth here because1142 * we need to use it to configure the correct SPI mode.1143 */1144 zynqmp_qspi_write_op(xqspi, op->data.buswidth,1145 genfifoentry);1146 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,1147 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |1148 GQSPI_CFG_START_GEN_FIFO_MASK);1149 }1150 1151 if (op->data.nbytes) {1152 reinit_completion(&xqspi->data_completion);1153 if (op->data.dir == SPI_MEM_DATA_OUT) {1154 xqspi->txbuf = (u8 *)op->data.buf.out;1155 xqspi->rxbuf = NULL;1156 xqspi->bytes_to_transfer = op->data.nbytes;1157 xqspi->bytes_to_receive = 0;1158 zynqmp_qspi_write_op(xqspi, op->data.buswidth,1159 genfifoentry);1160 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,1161 zynqmp_gqspi_read1162 (xqspi, GQSPI_CONFIG_OFST) |1163 GQSPI_CFG_START_GEN_FIFO_MASK);1164 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,1165 GQSPI_IER_TXEMPTY_MASK |1166 GQSPI_IER_GENFIFOEMPTY_MASK |1167 GQSPI_IER_TXNOT_FULL_MASK);1168 } else {1169 xqspi->txbuf = NULL;1170 xqspi->rxbuf = (u8 *)op->data.buf.in;1171 xqspi->bytes_to_receive = op->data.nbytes;1172 xqspi->bytes_to_transfer = 0;1173 err = zynqmp_qspi_read_op(xqspi, op->data.buswidth,1174 genfifoentry);1175 if (err)1176 goto return_err;1177 1178 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,1179 zynqmp_gqspi_read1180 (xqspi, GQSPI_CONFIG_OFST) |1181 GQSPI_CFG_START_GEN_FIFO_MASK);1182 if (xqspi->mode == GQSPI_MODE_DMA) {1183 zynqmp_gqspi_write1184 (xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST,1185 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);1186 } else {1187 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,1188 GQSPI_IER_GENFIFOEMPTY_MASK |1189 GQSPI_IER_RXNEMPTY_MASK |1190 GQSPI_IER_RXEMPTY_MASK);1191 }1192 }1193 timeout = zynqmp_qspi_timeout(xqspi, op->data.buswidth,1194 op->data.nbytes);1195 if (!wait_for_completion_timeout(&xqspi->data_completion, timeout))1196 err = -ETIMEDOUT;1197 }1198 1199return_err:1200 1201 zynqmp_qspi_chipselect(mem->spi, true);1202 mutex_unlock(&xqspi->op_lock);1203 1204 return err;1205}1206 1207static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {1208 SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,1209 zynqmp_runtime_resume, NULL)1210 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)1211};1212 1213static const struct qspi_platform_data versal_qspi_def = {1214 .quirks = QSPI_QUIRK_HAS_TAPDELAY,1215};1216 1217static const struct of_device_id zynqmp_qspi_of_match[] = {1218 { .compatible = "xlnx,zynqmp-qspi-1.0"},1219 { .compatible = "xlnx,versal-qspi-1.0", .data = &versal_qspi_def },1220 { /* End of table */ }1221};1222 1223static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = {1224 .exec_op = zynqmp_qspi_exec_op,1225};1226 1227/**1228 * zynqmp_qspi_probe - Probe method for the QSPI driver1229 * @pdev: Pointer to the platform_device structure1230 *1231 * This function initializes the driver data structures and the hardware.1232 *1233 * Return: 0 on success; error value otherwise1234 */1235static int zynqmp_qspi_probe(struct platform_device *pdev)1236{1237 int ret = 0;1238 struct spi_controller *ctlr;1239 struct zynqmp_qspi *xqspi;1240 struct device *dev = &pdev->dev;1241 struct device_node *np = dev->of_node;1242 u32 num_cs;1243 const struct qspi_platform_data *p_data;1244 1245 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*xqspi));1246 if (!ctlr)1247 return -ENOMEM;1248 1249 xqspi = spi_controller_get_devdata(ctlr);1250 xqspi->dev = dev;1251 xqspi->ctlr = ctlr;1252 platform_set_drvdata(pdev, xqspi);1253 1254 p_data = of_device_get_match_data(&pdev->dev);1255 if (p_data && (p_data->quirks & QSPI_QUIRK_HAS_TAPDELAY))1256 xqspi->has_tapdelay = true;1257 1258 xqspi->regs = devm_platform_ioremap_resource(pdev, 0);1259 if (IS_ERR(xqspi->regs))1260 return PTR_ERR(xqspi->regs);1261 1262 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");1263 if (IS_ERR(xqspi->pclk))1264 return dev_err_probe(dev, PTR_ERR(xqspi->pclk),1265 "pclk clock not found.\n");1266 1267 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");1268 if (IS_ERR(xqspi->refclk))1269 return dev_err_probe(dev, PTR_ERR(xqspi->refclk),1270 "ref_clk clock not found.\n");1271 1272 ret = clk_prepare_enable(xqspi->pclk);1273 if (ret)1274 return dev_err_probe(dev, ret, "Unable to enable APB clock.\n");1275 1276 ret = clk_prepare_enable(xqspi->refclk);1277 if (ret) {1278 dev_err(dev, "Unable to enable device clock.\n");1279 goto clk_dis_pclk;1280 }1281 1282 init_completion(&xqspi->data_completion);1283 1284 mutex_init(&xqspi->op_lock);1285 1286 pm_runtime_use_autosuspend(&pdev->dev);1287 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);1288 pm_runtime_set_active(&pdev->dev);1289 pm_runtime_enable(&pdev->dev);1290 1291 ret = pm_runtime_get_sync(&pdev->dev);1292 if (ret < 0) {1293 dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret);1294 goto clk_dis_all;1295 }1296 1297 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |1298 SPI_TX_DUAL | SPI_TX_QUAD;1299 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;1300 xqspi->speed_hz = ctlr->max_speed_hz;1301 1302 /* QSPI controller initializations */1303 zynqmp_qspi_init_hw(xqspi);1304 1305 xqspi->irq = platform_get_irq(pdev, 0);1306 if (xqspi->irq < 0) {1307 ret = xqspi->irq;1308 goto clk_dis_all;1309 }1310 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,1311 0, pdev->name, xqspi);1312 if (ret != 0) {1313 ret = -ENXIO;1314 dev_err(dev, "request_irq failed\n");1315 goto clk_dis_all;1316 }1317 1318 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));1319 if (ret)1320 goto clk_dis_all;1321 1322 ret = of_property_read_u32(np, "num-cs", &num_cs);1323 if (ret < 0) {1324 ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS;1325 } else if (num_cs > GQSPI_MAX_NUM_CS) {1326 ret = -EINVAL;1327 dev_err(&pdev->dev, "only %d chip selects are available\n",1328 GQSPI_MAX_NUM_CS);1329 goto clk_dis_all;1330 } else {1331 ctlr->num_chipselect = num_cs;1332 }1333 1334 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);1335 ctlr->mem_ops = &zynqmp_qspi_mem_ops;1336 ctlr->setup = zynqmp_qspi_setup_op;1337 ctlr->bits_per_word_mask = SPI_BPW_MASK(8);1338 ctlr->dev.of_node = np;1339 ctlr->auto_runtime_pm = true;1340 1341 ret = devm_spi_register_controller(&pdev->dev, ctlr);1342 if (ret) {1343 dev_err(&pdev->dev, "spi_register_controller failed\n");1344 goto clk_dis_all;1345 }1346 1347 pm_runtime_mark_last_busy(&pdev->dev);1348 pm_runtime_put_autosuspend(&pdev->dev);1349 1350 return 0;1351 1352clk_dis_all:1353 pm_runtime_disable(&pdev->dev);1354 pm_runtime_put_noidle(&pdev->dev);1355 pm_runtime_set_suspended(&pdev->dev);1356 clk_disable_unprepare(xqspi->refclk);1357clk_dis_pclk:1358 clk_disable_unprepare(xqspi->pclk);1359 1360 return ret;1361}1362 1363/**1364 * zynqmp_qspi_remove - Remove method for the QSPI driver1365 * @pdev: Pointer to the platform_device structure1366 *1367 * This function is called if a device is physically removed from the system or1368 * if the driver module is being unloaded. It frees all resources allocated to1369 * the device.1370 *1371 * Return: 0 Always1372 */1373static void zynqmp_qspi_remove(struct platform_device *pdev)1374{1375 struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev);1376 1377 pm_runtime_get_sync(&pdev->dev);1378 1379 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);1380 1381 pm_runtime_disable(&pdev->dev);1382 pm_runtime_put_noidle(&pdev->dev);1383 pm_runtime_set_suspended(&pdev->dev);1384 clk_disable_unprepare(xqspi->refclk);1385 clk_disable_unprepare(xqspi->pclk);1386}1387 1388MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);1389 1390static struct platform_driver zynqmp_qspi_driver = {1391 .probe = zynqmp_qspi_probe,1392 .remove_new = zynqmp_qspi_remove,1393 .driver = {1394 .name = "zynqmp-qspi",1395 .of_match_table = zynqmp_qspi_of_match,1396 .pm = &zynqmp_qspi_dev_pm_ops,1397 },1398};1399 1400module_platform_driver(zynqmp_qspi_driver);1401 1402MODULE_AUTHOR("Xilinx, Inc.");1403MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");1404MODULE_LICENSE("GPL");1405