1896 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved.4 */5#include <linux/bitmap.h>6#include <linux/delay.h>7#include <linux/err.h>8#include <linux/interrupt.h>9#include <linux/io.h>10#include <linux/irqchip/chained_irq.h>11#include <linux/irqdomain.h>12#include <linux/irq.h>13#include <linux/kernel.h>14#include <linux/module.h>15#include <linux/of.h>16#include <linux/of_address.h>17#include <linux/of_irq.h>18#include <linux/platform_device.h>19#include <linux/slab.h>20#include <linux/spmi.h>21 22/* PMIC Arbiter configuration registers */23#define PMIC_ARB_VERSION 0x000024#define PMIC_ARB_VERSION_V2_MIN 0x2001000025#define PMIC_ARB_VERSION_V3_MIN 0x3000000026#define PMIC_ARB_VERSION_V5_MIN 0x5000000027#define PMIC_ARB_VERSION_V7_MIN 0x7000000028#define PMIC_ARB_INT_EN 0x000429 30#define PMIC_ARB_FEATURES 0x000431#define PMIC_ARB_FEATURES_PERIPH_MASK GENMASK(10, 0)32 33#define PMIC_ARB_FEATURES1 0x000834 35/* PMIC Arbiter channel registers offsets */36#define PMIC_ARB_CMD 0x0037#define PMIC_ARB_CONFIG 0x0438#define PMIC_ARB_STATUS 0x0839#define PMIC_ARB_WDATA0 0x1040#define PMIC_ARB_WDATA1 0x1441#define PMIC_ARB_RDATA0 0x1842#define PMIC_ARB_RDATA1 0x1C43 44/* Mapping Table */45#define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N)))46#define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF)47#define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1)48#define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)49#define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1)50#define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)51 52#define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */53#define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */54#define PMIC_ARB_APID_VALID BIT(15)55#define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))56#define INVALID_EE 0xFF57 58/* Ownership Table */59#define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7)60 61/* Channel Status fields */62enum pmic_arb_chnl_status {63 PMIC_ARB_STATUS_DONE = BIT(0),64 PMIC_ARB_STATUS_FAILURE = BIT(1),65 PMIC_ARB_STATUS_DENIED = BIT(2),66 PMIC_ARB_STATUS_DROPPED = BIT(3),67};68 69/* Command register fields */70#define PMIC_ARB_CMD_MAX_BYTE_COUNT 871 72/* Command Opcodes */73enum pmic_arb_cmd_op_code {74 PMIC_ARB_OP_EXT_WRITEL = 0,75 PMIC_ARB_OP_EXT_READL = 1,76 PMIC_ARB_OP_EXT_WRITE = 2,77 PMIC_ARB_OP_RESET = 3,78 PMIC_ARB_OP_SLEEP = 4,79 PMIC_ARB_OP_SHUTDOWN = 5,80 PMIC_ARB_OP_WAKEUP = 6,81 PMIC_ARB_OP_AUTHENTICATE = 7,82 PMIC_ARB_OP_MSTR_READ = 8,83 PMIC_ARB_OP_MSTR_WRITE = 9,84 PMIC_ARB_OP_EXT_READ = 13,85 PMIC_ARB_OP_WRITE = 14,86 PMIC_ARB_OP_READ = 15,87 PMIC_ARB_OP_ZERO_WRITE = 16,88};89 90/*91 * PMIC arbiter version 5 uses different register offsets for read/write vs92 * observer channels.93 */94enum pmic_arb_channel {95 PMIC_ARB_CHANNEL_RW,96 PMIC_ARB_CHANNEL_OBS,97};98 99#define PMIC_ARB_MAX_BUSES 2100 101/* Maximum number of support PMIC peripherals */102#define PMIC_ARB_MAX_PERIPHS 512103#define PMIC_ARB_MAX_PERIPHS_V7 1024104#define PMIC_ARB_TIMEOUT_US 1000105#define PMIC_ARB_MAX_TRANS_BYTES (8)106 107#define PMIC_ARB_APID_MASK 0xFF108#define PMIC_ARB_PPID_MASK 0xFFF109 110/* interrupt enable bit */111#define SPMI_PIC_ACC_ENABLE_BIT BIT(0)112 113#define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \114 ((((slave_id) & 0xF) << 28) | \115 (((periph_id) & 0xFF) << 20) | \116 (((irq_id) & 0x7) << 16) | \117 (((apid) & 0x3FF) << 0))118 119#define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)120#define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)121#define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)122#define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x3FF)123 124struct pmic_arb_ver_ops;125 126struct apid_data {127 u16 ppid;128 u8 write_ee;129 u8 irq_ee;130};131 132struct spmi_pmic_arb;133 134/**135 * struct spmi_pmic_arb_bus - SPMI PMIC Arbiter Bus object136 *137 * @pmic_arb: the SPMI PMIC Arbiter the bus belongs to.138 * @domain: irq domain object for PMIC IRQ domain139 * @intr: address of the SPMI interrupt control registers.140 * @cnfg: address of the PMIC Arbiter configuration registers.141 * @spmic: spmi controller registered for this bus142 * @lock: lock to synchronize accesses.143 * @base_apid: on v7: minimum APID associated with the particular SPMI144 * bus instance145 * @apid_count: on v5 and v7: number of APIDs associated with the146 * particular SPMI bus instance147 * @mapping_table: in-memory copy of PPID -> APID mapping table.148 * @mapping_table_valid:bitmap containing valid-only periphs149 * @ppid_to_apid: in-memory copy of PPID -> APID mapping table.150 * @last_apid: Highest value APID in use151 * @apid_data: Table of data for all APIDs152 * @min_apid: minimum APID (used for bounding IRQ search)153 * @max_apid: maximum APID154 * @irq: PMIC ARB interrupt.155 * @id: unique ID of the bus156 */157struct spmi_pmic_arb_bus {158 struct spmi_pmic_arb *pmic_arb;159 struct irq_domain *domain;160 void __iomem *intr;161 void __iomem *cnfg;162 struct spmi_controller *spmic;163 raw_spinlock_t lock;164 u16 base_apid;165 int apid_count;166 u32 *mapping_table;167 DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);168 u16 *ppid_to_apid;169 u16 last_apid;170 struct apid_data *apid_data;171 u16 min_apid;172 u16 max_apid;173 int irq;174 u8 id;175};176 177/**178 * struct spmi_pmic_arb - SPMI PMIC Arbiter object179 *180 * @rd_base: on v1 "core", on v2 "observer" register base off DT.181 * @wr_base: on v1 "core", on v2 "chnls" register base off DT.182 * @core: core register base for v2 and above only (see above)183 * @core_size: core register base size184 * @channel: execution environment channel to use for accesses.185 * @ee: the current Execution Environment186 * @ver_ops: version dependent operations.187 * @max_periphs: Number of elements in apid_data[]188 * @buses: per arbiter buses instances189 * @buses_available: number of buses registered190 */191struct spmi_pmic_arb {192 void __iomem *rd_base;193 void __iomem *wr_base;194 void __iomem *core;195 resource_size_t core_size;196 u8 channel;197 u8 ee;198 const struct pmic_arb_ver_ops *ver_ops;199 int max_periphs;200 struct spmi_pmic_arb_bus *buses[PMIC_ARB_MAX_BUSES];201 int buses_available;202};203 204/**205 * struct pmic_arb_ver_ops - version dependent functionality.206 *207 * @ver_str: version string.208 * @get_core_resources: initializes the core, observer and channels209 * @init_apid: finds the apid base and count210 * @ppid_to_apid: finds the apid for a given ppid.211 * @non_data_cmd: on v1 issues an spmi non-data command.212 * on v2 no HW support, returns -EOPNOTSUPP.213 * @offset: on v1 offset of per-ee channel.214 * on v2 offset of per-ee and per-ppid channel.215 * @fmt_cmd: formats a GENI/SPMI command.216 * @owner_acc_status: on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn217 * on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.218 * @acc_enable: on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn219 * on v2 address of SPMI_PIC_ACC_ENABLEn.220 * @irq_status: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn221 * on v2 address of SPMI_PIC_IRQ_STATUSn.222 * @irq_clear: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn223 * on v2 address of SPMI_PIC_IRQ_CLEARn.224 * @apid_map_offset: offset of PMIC_ARB_REG_CHNLn225 * @apid_owner: on v2 and later address of SPMI_PERIPHn_2OWNER_TABLE_REG226 */227struct pmic_arb_ver_ops {228 const char *ver_str;229 int (*get_core_resources)(struct platform_device *pdev, void __iomem *core);230 int (*init_apid)(struct spmi_pmic_arb_bus *bus, int index);231 int (*ppid_to_apid)(struct spmi_pmic_arb_bus *bus, u16 ppid);232 /* spmi commands (read_cmd, write_cmd, cmd) functionality */233 int (*offset)(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,234 enum pmic_arb_channel ch_type);235 u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);236 int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);237 /* Interrupts controller functionality (offset of PIC registers) */238 void __iomem *(*owner_acc_status)(struct spmi_pmic_arb_bus *bus, u8 m,239 u16 n);240 void __iomem *(*acc_enable)(struct spmi_pmic_arb_bus *bus, u16 n);241 void __iomem *(*irq_status)(struct spmi_pmic_arb_bus *bus, u16 n);242 void __iomem *(*irq_clear)(struct spmi_pmic_arb_bus *bus, u16 n);243 u32 (*apid_map_offset)(u16 n);244 void __iomem *(*apid_owner)(struct spmi_pmic_arb_bus *bus, u16 n);245};246 247static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,248 u32 offset, u32 val)249{250 writel_relaxed(val, pmic_arb->wr_base + offset);251}252 253static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,254 u32 offset, u32 val)255{256 writel_relaxed(val, pmic_arb->rd_base + offset);257}258 259/**260 * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf261 * @pmic_arb: the SPMI PMIC arbiter262 * @bc: byte count -1. range: 0..3263 * @reg: register's address264 * @buf: output parameter, length must be bc + 1265 */266static void267pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)268{269 u32 data = __raw_readl(pmic_arb->rd_base + reg);270 271 memcpy(buf, &data, (bc & 3) + 1);272}273 274/**275 * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register276 * @pmic_arb: the SPMI PMIC arbiter277 * @bc: byte-count -1. range: 0..3.278 * @reg: register's address.279 * @buf: buffer to write. length must be bc + 1.280 */281static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,282 u32 reg, u8 bc)283{284 u32 data = 0;285 286 memcpy(&data, buf, (bc & 3) + 1);287 __raw_writel(data, pmic_arb->wr_base + reg);288}289 290static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,291 void __iomem *base, u8 sid, u16 addr,292 enum pmic_arb_channel ch_type)293{294 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);295 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;296 u32 status = 0;297 u32 timeout = PMIC_ARB_TIMEOUT_US;298 u32 offset;299 int rc;300 301 rc = pmic_arb->ver_ops->offset(bus, sid, addr, ch_type);302 if (rc < 0)303 return rc;304 305 offset = rc;306 offset += PMIC_ARB_STATUS;307 308 while (timeout--) {309 status = readl_relaxed(base + offset);310 311 if (status & PMIC_ARB_STATUS_DONE) {312 if (status & PMIC_ARB_STATUS_DENIED) {313 dev_err(&ctrl->dev, "%s: %#x %#x: transaction denied (%#x)\n",314 __func__, sid, addr, status);315 return -EPERM;316 }317 318 if (status & PMIC_ARB_STATUS_FAILURE) {319 dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x) reg: 0x%x\n",320 __func__, sid, addr, status, offset);321 WARN_ON(1);322 return -EIO;323 }324 325 if (status & PMIC_ARB_STATUS_DROPPED) {326 dev_err(&ctrl->dev, "%s: %#x %#x: transaction dropped (%#x)\n",327 __func__, sid, addr, status);328 return -EIO;329 }330 331 return 0;332 }333 udelay(1);334 }335 336 dev_err(&ctrl->dev, "%s: %#x %#x %#x: timeout, status %#x\n",337 __func__, bus->id, sid, addr, status);338 return -ETIMEDOUT;339}340 341static int342pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)343{344 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);345 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;346 unsigned long flags;347 u32 cmd;348 int rc;349 u32 offset;350 351 rc = pmic_arb->ver_ops->offset(bus, sid, 0, PMIC_ARB_CHANNEL_RW);352 if (rc < 0)353 return rc;354 355 offset = rc;356 cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);357 358 raw_spin_lock_irqsave(&bus->lock, flags);359 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);360 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,361 PMIC_ARB_CHANNEL_RW);362 raw_spin_unlock_irqrestore(&bus->lock, flags);363 364 return rc;365}366 367static int368pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)369{370 return -EOPNOTSUPP;371}372 373/* Non-data command */374static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)375{376 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);377 378 dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);379 380 /* Check for valid non-data command */381 if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)382 return -EINVAL;383 384 return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);385}386 387static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb_bus *bus, u8 opc, u8 sid,388 u16 addr, size_t len, u32 *cmd, u32 *offset)389{390 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;391 u8 bc = len - 1;392 int rc;393 394 rc = pmic_arb->ver_ops->offset(bus, sid, addr,395 PMIC_ARB_CHANNEL_OBS);396 if (rc < 0)397 return rc;398 399 *offset = rc;400 if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {401 dev_err(&bus->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested\n",402 PMIC_ARB_MAX_TRANS_BYTES, len);403 return -EINVAL;404 }405 406 /* Check the opcode */407 if (opc >= 0x60 && opc <= 0x7F)408 opc = PMIC_ARB_OP_READ;409 else if (opc >= 0x20 && opc <= 0x2F)410 opc = PMIC_ARB_OP_EXT_READ;411 else if (opc >= 0x38 && opc <= 0x3F)412 opc = PMIC_ARB_OP_EXT_READL;413 else414 return -EINVAL;415 416 *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);417 418 return 0;419}420 421static int pmic_arb_read_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,422 u32 offset, u8 sid, u16 addr, u8 *buf,423 size_t len)424{425 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);426 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;427 u8 bc = len - 1;428 int rc;429 430 pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);431 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,432 PMIC_ARB_CHANNEL_OBS);433 if (rc)434 return rc;435 436 pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,437 min_t(u8, bc, 3));438 439 if (bc > 3)440 pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,441 bc - 4);442 return 0;443}444 445static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,446 u16 addr, u8 *buf, size_t len)447{448 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);449 unsigned long flags;450 u32 cmd, offset;451 int rc;452 453 rc = pmic_arb_fmt_read_cmd(bus, opc, sid, addr, len, &cmd,454 &offset);455 if (rc)456 return rc;457 458 raw_spin_lock_irqsave(&bus->lock, flags);459 rc = pmic_arb_read_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, len);460 raw_spin_unlock_irqrestore(&bus->lock, flags);461 462 return rc;463}464 465static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb_bus *bus, u8 opc,466 u8 sid, u16 addr, size_t len, u32 *cmd,467 u32 *offset)468{469 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;470 u8 bc = len - 1;471 int rc;472 473 rc = pmic_arb->ver_ops->offset(bus, sid, addr,474 PMIC_ARB_CHANNEL_RW);475 if (rc < 0)476 return rc;477 478 *offset = rc;479 if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {480 dev_err(&bus->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested\n",481 PMIC_ARB_MAX_TRANS_BYTES, len);482 return -EINVAL;483 }484 485 /* Check the opcode */486 if (opc >= 0x40 && opc <= 0x5F)487 opc = PMIC_ARB_OP_WRITE;488 else if (opc <= 0x0F)489 opc = PMIC_ARB_OP_EXT_WRITE;490 else if (opc >= 0x30 && opc <= 0x37)491 opc = PMIC_ARB_OP_EXT_WRITEL;492 else if (opc >= 0x80)493 opc = PMIC_ARB_OP_ZERO_WRITE;494 else495 return -EINVAL;496 497 *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);498 499 return 0;500}501 502static int pmic_arb_write_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd,503 u32 offset, u8 sid, u16 addr,504 const u8 *buf, size_t len)505{506 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);507 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;508 u8 bc = len - 1;509 510 /* Write data to FIFOs */511 pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,512 min_t(u8, bc, 3));513 if (bc > 3)514 pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,515 bc - 4);516 517 /* Start the transaction */518 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);519 return pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,520 PMIC_ARB_CHANNEL_RW);521}522 523static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,524 u16 addr, const u8 *buf, size_t len)525{526 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);527 unsigned long flags;528 u32 cmd, offset;529 int rc;530 531 rc = pmic_arb_fmt_write_cmd(bus, opc, sid, addr, len, &cmd,532 &offset);533 if (rc)534 return rc;535 536 raw_spin_lock_irqsave(&bus->lock, flags);537 rc = pmic_arb_write_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf,538 len);539 raw_spin_unlock_irqrestore(&bus->lock, flags);540 541 return rc;542}543 544static int pmic_arb_masked_write(struct spmi_controller *ctrl, u8 sid, u16 addr,545 const u8 *buf, const u8 *mask, size_t len)546{547 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl);548 u32 read_cmd, read_offset, write_cmd, write_offset;549 u8 temp[PMIC_ARB_MAX_TRANS_BYTES];550 unsigned long flags;551 int rc, i;552 553 rc = pmic_arb_fmt_read_cmd(bus, SPMI_CMD_EXT_READL, sid, addr, len,554 &read_cmd, &read_offset);555 if (rc)556 return rc;557 558 rc = pmic_arb_fmt_write_cmd(bus, SPMI_CMD_EXT_WRITEL, sid, addr,559 len, &write_cmd, &write_offset);560 if (rc)561 return rc;562 563 raw_spin_lock_irqsave(&bus->lock, flags);564 rc = pmic_arb_read_cmd_unlocked(ctrl, read_cmd, read_offset, sid, addr,565 temp, len);566 if (rc)567 goto done;568 569 for (i = 0; i < len; i++)570 temp[i] = (temp[i] & ~mask[i]) | (buf[i] & mask[i]);571 572 rc = pmic_arb_write_cmd_unlocked(ctrl, write_cmd, write_offset, sid,573 addr, temp, len);574done:575 raw_spin_unlock_irqrestore(&bus->lock, flags);576 577 return rc;578}579 580enum qpnpint_regs {581 QPNPINT_REG_RT_STS = 0x10,582 QPNPINT_REG_SET_TYPE = 0x11,583 QPNPINT_REG_POLARITY_HIGH = 0x12,584 QPNPINT_REG_POLARITY_LOW = 0x13,585 QPNPINT_REG_LATCHED_CLR = 0x14,586 QPNPINT_REG_EN_SET = 0x15,587 QPNPINT_REG_EN_CLR = 0x16,588 QPNPINT_REG_LATCHED_STS = 0x18,589};590 591struct spmi_pmic_arb_qpnpint_type {592 u8 type; /* 1 -> edge */593 u8 polarity_high;594 u8 polarity_low;595} __packed;596 597/* Simplified accessor functions for irqchip callbacks */598static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,599 size_t len)600{601 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);602 u8 sid = hwirq_to_sid(d->hwirq);603 u8 per = hwirq_to_per(d->hwirq);604 605 if (pmic_arb_write_cmd(bus->spmic, SPMI_CMD_EXT_WRITEL, sid,606 (per << 8) + reg, buf, len))607 dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x\n",608 d->irq);609}610 611static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)612{613 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);614 u8 sid = hwirq_to_sid(d->hwirq);615 u8 per = hwirq_to_per(d->hwirq);616 617 if (pmic_arb_read_cmd(bus->spmic, SPMI_CMD_EXT_READL, sid,618 (per << 8) + reg, buf, len))619 dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x\n",620 d->irq);621}622 623static int qpnpint_spmi_masked_write(struct irq_data *d, u8 reg,624 const void *buf, const void *mask,625 size_t len)626{627 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);628 u8 sid = hwirq_to_sid(d->hwirq);629 u8 per = hwirq_to_per(d->hwirq);630 int rc;631 632 rc = pmic_arb_masked_write(bus->spmic, sid, (per << 8) + reg, buf,633 mask, len);634 if (rc)635 dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x rc=%d\n",636 d->irq, rc);637 return rc;638}639 640static void cleanup_irq(struct spmi_pmic_arb_bus *bus, u16 apid, int id)641{642 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;643 u16 ppid = bus->apid_data[apid].ppid;644 u8 sid = ppid >> 8;645 u8 per = ppid & 0xFF;646 u8 irq_mask = BIT(id);647 648 dev_err_ratelimited(&bus->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n",649 __func__, apid, sid, per, id);650 writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(bus, apid));651}652 653static int periph_interrupt(struct spmi_pmic_arb_bus *bus, u16 apid)654{655 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;656 unsigned int irq;657 u32 status, id;658 int handled = 0;659 u8 sid = (bus->apid_data[apid].ppid >> 8) & 0xF;660 u8 per = bus->apid_data[apid].ppid & 0xFF;661 662 status = readl_relaxed(pmic_arb->ver_ops->irq_status(bus, apid));663 while (status) {664 id = ffs(status) - 1;665 status &= ~BIT(id);666 irq = irq_find_mapping(bus->domain,667 spec_to_hwirq(sid, per, id, apid));668 if (irq == 0) {669 cleanup_irq(bus, apid, id);670 continue;671 }672 generic_handle_irq(irq);673 handled++;674 }675 676 return handled;677}678 679static void pmic_arb_chained_irq(struct irq_desc *desc)680{681 struct spmi_pmic_arb_bus *bus = irq_desc_get_handler_data(desc);682 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;683 const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;684 struct irq_chip *chip = irq_desc_get_chip(desc);685 int first = bus->min_apid;686 int last = bus->max_apid;687 /*688 * acc_offset will be non-zero for the secondary SPMI bus instance on689 * v7 controllers.690 */691 int acc_offset = bus->base_apid >> 5;692 u8 ee = pmic_arb->ee;693 u32 status, enable, handled = 0;694 int i, id, apid;695 /* status based dispatch */696 bool acc_valid = false;697 u32 irq_status = 0;698 699 chained_irq_enter(chip, desc);700 701 for (i = first >> 5; i <= last >> 5; ++i) {702 status = readl_relaxed(ver_ops->owner_acc_status(bus, ee, i - acc_offset));703 if (status)704 acc_valid = true;705 706 while (status) {707 id = ffs(status) - 1;708 status &= ~BIT(id);709 apid = id + i * 32;710 if (apid < first || apid > last) {711 WARN_ONCE(true, "spurious spmi irq received for apid=%d\n",712 apid);713 continue;714 }715 enable = readl_relaxed(716 ver_ops->acc_enable(bus, apid));717 if (enable & SPMI_PIC_ACC_ENABLE_BIT)718 if (periph_interrupt(bus, apid) != 0)719 handled++;720 }721 }722 723 /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */724 if (!acc_valid) {725 for (i = first; i <= last; i++) {726 /* skip if APPS is not irq owner */727 if (bus->apid_data[i].irq_ee != pmic_arb->ee)728 continue;729 730 irq_status = readl_relaxed(731 ver_ops->irq_status(bus, i));732 if (irq_status) {733 enable = readl_relaxed(734 ver_ops->acc_enable(bus, i));735 if (enable & SPMI_PIC_ACC_ENABLE_BIT) {736 dev_dbg(&bus->spmic->dev,737 "Dispatching IRQ for apid=%d status=%x\n",738 i, irq_status);739 if (periph_interrupt(bus, i) != 0)740 handled++;741 }742 }743 }744 }745 746 if (handled == 0)747 handle_bad_irq(desc);748 749 chained_irq_exit(chip, desc);750}751 752static void qpnpint_irq_ack(struct irq_data *d)753{754 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);755 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;756 u8 irq = hwirq_to_irq(d->hwirq);757 u16 apid = hwirq_to_apid(d->hwirq);758 u8 data;759 760 writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(bus, apid));761 762 data = BIT(irq);763 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);764}765 766static void qpnpint_irq_mask(struct irq_data *d)767{768 u8 irq = hwirq_to_irq(d->hwirq);769 u8 data = BIT(irq);770 771 qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);772}773 774static void qpnpint_irq_unmask(struct irq_data *d)775{776 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);777 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;778 const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;779 u8 irq = hwirq_to_irq(d->hwirq);780 u16 apid = hwirq_to_apid(d->hwirq);781 u8 buf[2];782 783 writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,784 ver_ops->acc_enable(bus, apid));785 786 qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);787 if (!(buf[0] & BIT(irq))) {788 /*789 * Since the interrupt is currently disabled, write to both the790 * LATCHED_CLR and EN_SET registers so that a spurious interrupt791 * cannot be triggered when the interrupt is enabled792 */793 buf[0] = BIT(irq);794 buf[1] = BIT(irq);795 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2);796 }797}798 799static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)800{801 struct spmi_pmic_arb_qpnpint_type type = {0};802 struct spmi_pmic_arb_qpnpint_type mask;803 irq_flow_handler_t flow_handler;804 u8 irq_bit = BIT(hwirq_to_irq(d->hwirq));805 int rc;806 807 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {808 type.type = irq_bit;809 if (flow_type & IRQF_TRIGGER_RISING)810 type.polarity_high = irq_bit;811 if (flow_type & IRQF_TRIGGER_FALLING)812 type.polarity_low = irq_bit;813 814 flow_handler = handle_edge_irq;815 } else {816 if ((flow_type & (IRQF_TRIGGER_HIGH)) &&817 (flow_type & (IRQF_TRIGGER_LOW)))818 return -EINVAL;819 820 if (flow_type & IRQF_TRIGGER_HIGH)821 type.polarity_high = irq_bit;822 else823 type.polarity_low = irq_bit;824 825 flow_handler = handle_level_irq;826 }827 828 mask.type = irq_bit;829 mask.polarity_high = irq_bit;830 mask.polarity_low = irq_bit;831 832 rc = qpnpint_spmi_masked_write(d, QPNPINT_REG_SET_TYPE, &type, &mask,833 sizeof(type));834 irq_set_handler_locked(d, flow_handler);835 836 return rc;837}838 839static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)840{841 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);842 843 return irq_set_irq_wake(bus->irq, on);844}845 846static int qpnpint_get_irqchip_state(struct irq_data *d,847 enum irqchip_irq_state which,848 bool *state)849{850 u8 irq = hwirq_to_irq(d->hwirq);851 u8 status = 0;852 853 if (which != IRQCHIP_STATE_LINE_LEVEL)854 return -EINVAL;855 856 qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);857 *state = !!(status & BIT(irq));858 859 return 0;860}861 862static int qpnpint_irq_domain_activate(struct irq_domain *domain,863 struct irq_data *d, bool reserve)864{865 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d);866 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;867 u16 periph = hwirq_to_per(d->hwirq);868 u16 apid = hwirq_to_apid(d->hwirq);869 u16 sid = hwirq_to_sid(d->hwirq);870 u16 irq = hwirq_to_irq(d->hwirq);871 u8 buf;872 873 if (bus->apid_data[apid].irq_ee != pmic_arb->ee) {874 dev_err(&bus->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",875 sid, periph, irq, pmic_arb->ee,876 bus->apid_data[apid].irq_ee);877 return -ENODEV;878 }879 880 buf = BIT(irq);881 qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1);882 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1);883 884 return 0;885}886 887static struct irq_chip pmic_arb_irqchip = {888 .name = "pmic_arb",889 .irq_ack = qpnpint_irq_ack,890 .irq_mask = qpnpint_irq_mask,891 .irq_unmask = qpnpint_irq_unmask,892 .irq_set_type = qpnpint_irq_set_type,893 .irq_set_wake = qpnpint_irq_set_wake,894 .irq_get_irqchip_state = qpnpint_get_irqchip_state,895 .flags = IRQCHIP_MASK_ON_SUSPEND,896};897 898static int qpnpint_irq_domain_translate(struct irq_domain *d,899 struct irq_fwspec *fwspec,900 unsigned long *out_hwirq,901 unsigned int *out_type)902{903 struct spmi_pmic_arb_bus *bus = d->host_data;904 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;905 u32 *intspec = fwspec->param;906 u16 apid, ppid;907 int rc;908 909 dev_dbg(&bus->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",910 intspec[0], intspec[1], intspec[2]);911 912 if (irq_domain_get_of_node(d) != bus->spmic->dev.of_node)913 return -EINVAL;914 if (fwspec->param_count != 4)915 return -EINVAL;916 if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)917 return -EINVAL;918 919 ppid = intspec[0] << 8 | intspec[1];920 rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid);921 if (rc < 0) {922 dev_err(&bus->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",923 intspec[0], intspec[1], intspec[2], rc);924 return rc;925 }926 927 apid = rc;928 /* Keep track of {max,min}_apid for bounding search during interrupt */929 if (apid > bus->max_apid)930 bus->max_apid = apid;931 if (apid < bus->min_apid)932 bus->min_apid = apid;933 934 *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);935 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;936 937 dev_dbg(&bus->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);938 939 return 0;940}941 942static struct lock_class_key qpnpint_irq_lock_class, qpnpint_irq_request_class;943 944static void qpnpint_irq_domain_map(struct spmi_pmic_arb_bus *bus,945 struct irq_domain *domain, unsigned int virq,946 irq_hw_number_t hwirq, unsigned int type)947{948 irq_flow_handler_t handler;949 950 dev_dbg(&bus->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n",951 virq, hwirq, type);952 953 if (type & IRQ_TYPE_EDGE_BOTH)954 handler = handle_edge_irq;955 else956 handler = handle_level_irq;957 958 959 irq_set_lockdep_class(virq, &qpnpint_irq_lock_class,960 &qpnpint_irq_request_class);961 irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, bus,962 handler, NULL, NULL);963}964 965static int qpnpint_irq_domain_alloc(struct irq_domain *domain,966 unsigned int virq, unsigned int nr_irqs,967 void *data)968{969 struct spmi_pmic_arb_bus *bus = domain->host_data;970 struct irq_fwspec *fwspec = data;971 irq_hw_number_t hwirq;972 unsigned int type;973 int ret, i;974 975 ret = qpnpint_irq_domain_translate(domain, fwspec, &hwirq, &type);976 if (ret)977 return ret;978 979 for (i = 0; i < nr_irqs; i++)980 qpnpint_irq_domain_map(bus, domain, virq + i, hwirq + i,981 type);982 983 return 0;984}985 986static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb_bus *bus)987{988 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;989 990 /*991 * Initialize max_apid/min_apid to the opposite bounds, during992 * the irq domain translation, we are sure to update these993 */994 bus->max_apid = 0;995 bus->min_apid = pmic_arb->max_periphs - 1;996 997 return 0;998}999 1000static int pmic_arb_get_core_resources_v1(struct platform_device *pdev,1001 void __iomem *core)1002{1003 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);1004 1005 pmic_arb->wr_base = core;1006 pmic_arb->rd_base = core;1007 1008 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS;1009 1010 return 0;1011}1012 1013static int pmic_arb_init_apid_v1(struct spmi_pmic_arb_bus *bus, int index)1014{1015 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1016 u32 *mapping_table;1017 1018 if (index) {1019 dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n",1020 index);1021 return -EINVAL;1022 }1023 1024 mapping_table = devm_kcalloc(&bus->spmic->dev, pmic_arb->max_periphs,1025 sizeof(*mapping_table), GFP_KERNEL);1026 if (!mapping_table)1027 return -ENOMEM;1028 1029 bus->mapping_table = mapping_table;1030 1031 return pmic_arb_init_apid_min_max(bus);1032}1033 1034static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb_bus *bus, u16 ppid)1035{1036 u32 *mapping_table = bus->mapping_table;1037 int index = 0, i;1038 u16 apid_valid;1039 u16 apid;1040 u32 data;1041 1042 apid_valid = bus->ppid_to_apid[ppid];1043 if (apid_valid & PMIC_ARB_APID_VALID) {1044 apid = apid_valid & ~PMIC_ARB_APID_VALID;1045 return apid;1046 }1047 1048 for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {1049 if (!test_and_set_bit(index, bus->mapping_table_valid))1050 mapping_table[index] = readl_relaxed(bus->cnfg +1051 SPMI_MAPPING_TABLE_REG(index));1052 1053 data = mapping_table[index];1054 1055 if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) {1056 if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {1057 index = SPMI_MAPPING_BIT_IS_1_RESULT(data);1058 } else {1059 apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);1060 bus->ppid_to_apid[ppid]1061 = apid | PMIC_ARB_APID_VALID;1062 bus->apid_data[apid].ppid = ppid;1063 return apid;1064 }1065 } else {1066 if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {1067 index = SPMI_MAPPING_BIT_IS_0_RESULT(data);1068 } else {1069 apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);1070 bus->ppid_to_apid[ppid]1071 = apid | PMIC_ARB_APID_VALID;1072 bus->apid_data[apid].ppid = ppid;1073 return apid;1074 }1075 }1076 }1077 1078 return -ENODEV;1079}1080 1081/* v1 offset per ee */1082static int pmic_arb_offset_v1(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,1083 enum pmic_arb_channel ch_type)1084{1085 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1086 return 0x800 + 0x80 * pmic_arb->channel;1087}1088 1089static u16 pmic_arb_find_apid(struct spmi_pmic_arb_bus *bus, u16 ppid)1090{1091 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1092 struct apid_data *apidd = &bus->apid_data[bus->last_apid];1093 u32 regval, offset;1094 u16 id, apid;1095 1096 for (apid = bus->last_apid; ; apid++, apidd++) {1097 offset = pmic_arb->ver_ops->apid_map_offset(apid);1098 if (offset >= pmic_arb->core_size)1099 break;1100 1101 regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus,1102 apid));1103 apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);1104 apidd->write_ee = apidd->irq_ee;1105 1106 regval = readl_relaxed(pmic_arb->core + offset);1107 if (!regval)1108 continue;1109 1110 id = (regval >> 8) & PMIC_ARB_PPID_MASK;1111 bus->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;1112 apidd->ppid = id;1113 if (id == ppid) {1114 apid |= PMIC_ARB_APID_VALID;1115 break;1116 }1117 }1118 bus->last_apid = apid & ~PMIC_ARB_APID_VALID;1119 1120 return apid;1121}1122 1123static int pmic_arb_get_obsrvr_chnls_v2(struct platform_device *pdev)1124{1125 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);1126 1127 pmic_arb->rd_base = devm_platform_ioremap_resource_byname(pdev, "obsrvr");1128 if (IS_ERR(pmic_arb->rd_base))1129 return PTR_ERR(pmic_arb->rd_base);1130 1131 pmic_arb->wr_base = devm_platform_ioremap_resource_byname(pdev, "chnls");1132 if (IS_ERR(pmic_arb->wr_base))1133 return PTR_ERR(pmic_arb->wr_base);1134 1135 return 0;1136}1137 1138static int pmic_arb_get_core_resources_v2(struct platform_device *pdev,1139 void __iomem *core)1140{1141 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);1142 1143 pmic_arb->core = core;1144 1145 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS;1146 1147 return pmic_arb_get_obsrvr_chnls_v2(pdev);1148}1149 1150static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb_bus *bus, u16 ppid)1151{1152 u16 apid_valid;1153 1154 apid_valid = bus->ppid_to_apid[ppid];1155 if (!(apid_valid & PMIC_ARB_APID_VALID))1156 apid_valid = pmic_arb_find_apid(bus, ppid);1157 if (!(apid_valid & PMIC_ARB_APID_VALID))1158 return -ENODEV;1159 1160 return apid_valid & ~PMIC_ARB_APID_VALID;1161}1162 1163static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus)1164{1165 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1166 struct apid_data *apidd;1167 struct apid_data *prev_apidd;1168 u16 i, apid, ppid, apid_max;1169 bool valid, is_irq_ee;1170 u32 regval, offset;1171 1172 /*1173 * In order to allow multiple EEs to write to a single PPID in arbiter1174 * version 5 and 7, there is more than one APID mapped to each PPID.1175 * The owner field for each of these mappings specifies the EE which is1176 * allowed to write to the APID. The owner of the last (highest) APID1177 * which has the IRQ owner bit set for a given PPID will receive1178 * interrupts from the PPID.1179 *1180 * In arbiter version 7, the APID numbering space is divided between1181 * the primary bus (0) and secondary bus (1) such that:1182 * APID = 0 to N-1 are assigned to the primary bus1183 * APID = N to N+M-1 are assigned to the secondary bus1184 * where N = number of APIDs supported by the primary bus and1185 * M = number of APIDs supported by the secondary bus1186 */1187 apidd = &bus->apid_data[bus->base_apid];1188 apid_max = bus->base_apid + bus->apid_count;1189 for (i = bus->base_apid; i < apid_max; i++, apidd++) {1190 offset = pmic_arb->ver_ops->apid_map_offset(i);1191 if (offset >= pmic_arb->core_size)1192 break;1193 1194 regval = readl_relaxed(pmic_arb->core + offset);1195 if (!regval)1196 continue;1197 ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;1198 is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);1199 1200 regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus, i));1201 apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);1202 1203 apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;1204 1205 valid = bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;1206 apid = bus->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;1207 prev_apidd = &bus->apid_data[apid];1208 1209 if (!valid || apidd->write_ee == pmic_arb->ee) {1210 /* First PPID mapping or one for this EE */1211 bus->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;1212 } else if (valid && is_irq_ee &&1213 prev_apidd->write_ee == pmic_arb->ee) {1214 /*1215 * Duplicate PPID mapping after the one for this EE;1216 * override the irq owner1217 */1218 prev_apidd->irq_ee = apidd->irq_ee;1219 }1220 1221 apidd->ppid = ppid;1222 bus->last_apid = i;1223 }1224 1225 /* Dump the mapping table for debug purposes. */1226 dev_dbg(&bus->spmic->dev, "PPID APID Write-EE IRQ-EE\n");1227 for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {1228 apid = bus->ppid_to_apid[ppid];1229 if (apid & PMIC_ARB_APID_VALID) {1230 apid &= ~PMIC_ARB_APID_VALID;1231 apidd = &bus->apid_data[apid];1232 dev_dbg(&bus->spmic->dev, "%#03X %3u %2u %2u\n",1233 ppid, apid, apidd->write_ee, apidd->irq_ee);1234 }1235 }1236 1237 return 0;1238}1239 1240static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb_bus *bus, u16 ppid)1241{1242 if (!(bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))1243 return -ENODEV;1244 1245 return bus->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;1246}1247 1248/* v2 offset per ppid and per ee */1249static int pmic_arb_offset_v2(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,1250 enum pmic_arb_channel ch_type)1251{1252 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1253 u16 apid;1254 u16 ppid;1255 int rc;1256 1257 ppid = sid << 8 | ((addr >> 8) & 0xFF);1258 rc = pmic_arb_ppid_to_apid_v2(bus, ppid);1259 if (rc < 0)1260 return rc;1261 1262 apid = rc;1263 return 0x1000 * pmic_arb->ee + 0x8000 * apid;1264}1265 1266static int pmic_arb_init_apid_v5(struct spmi_pmic_arb_bus *bus, int index)1267{1268 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1269 int ret;1270 1271 if (index) {1272 dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n",1273 index);1274 return -EINVAL;1275 }1276 1277 bus->base_apid = 0;1278 bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &1279 PMIC_ARB_FEATURES_PERIPH_MASK;1280 1281 if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) {1282 dev_err(&bus->spmic->dev, "Unsupported APID count %d detected\n",1283 bus->base_apid + bus->apid_count);1284 return -EINVAL;1285 }1286 1287 ret = pmic_arb_init_apid_min_max(bus);1288 if (ret)1289 return ret;1290 1291 ret = pmic_arb_read_apid_map_v5(bus);1292 if (ret) {1293 dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n",1294 ret);1295 return ret;1296 }1297 1298 return 0;1299}1300 1301/*1302 * v5 offset per ee and per apid for observer channels and per apid for1303 * read/write channels.1304 */1305static int pmic_arb_offset_v5(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,1306 enum pmic_arb_channel ch_type)1307{1308 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1309 u16 apid;1310 int rc;1311 u32 offset = 0;1312 u16 ppid = (sid << 8) | (addr >> 8);1313 1314 rc = pmic_arb_ppid_to_apid_v5(bus, ppid);1315 if (rc < 0)1316 return rc;1317 1318 apid = rc;1319 switch (ch_type) {1320 case PMIC_ARB_CHANNEL_OBS:1321 offset = 0x10000 * pmic_arb->ee + 0x80 * apid;1322 break;1323 case PMIC_ARB_CHANNEL_RW:1324 if (bus->apid_data[apid].write_ee != pmic_arb->ee) {1325 dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",1326 sid, addr);1327 return -EPERM;1328 }1329 offset = 0x10000 * apid;1330 break;1331 }1332 1333 return offset;1334}1335 1336static int pmic_arb_get_core_resources_v7(struct platform_device *pdev,1337 void __iomem *core)1338{1339 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);1340 1341 pmic_arb->core = core;1342 1343 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V7;1344 1345 return pmic_arb_get_obsrvr_chnls_v2(pdev);1346}1347 1348/*1349 * Only v7 supports 2 buses. Each bus will get a different apid count, read1350 * from different registers.1351 */1352static int pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index)1353{1354 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1355 int ret;1356 1357 if (index == 0) {1358 bus->base_apid = 0;1359 bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &1360 PMIC_ARB_FEATURES_PERIPH_MASK;1361 } else if (index == 1) {1362 bus->base_apid = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) &1363 PMIC_ARB_FEATURES_PERIPH_MASK;1364 bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES1) &1365 PMIC_ARB_FEATURES_PERIPH_MASK;1366 } else {1367 dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n",1368 bus->id);1369 return -EINVAL;1370 }1371 1372 if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) {1373 dev_err(&bus->spmic->dev, "Unsupported APID count %d detected\n",1374 bus->base_apid + bus->apid_count);1375 return -EINVAL;1376 }1377 1378 ret = pmic_arb_init_apid_min_max(bus);1379 if (ret)1380 return ret;1381 1382 ret = pmic_arb_read_apid_map_v5(bus);1383 if (ret) {1384 dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n",1385 ret);1386 return ret;1387 }1388 1389 return 0;1390}1391 1392/*1393 * v7 offset per ee and per apid for observer channels and per apid for1394 * read/write channels.1395 */1396static int pmic_arb_offset_v7(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr,1397 enum pmic_arb_channel ch_type)1398{1399 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1400 u16 apid;1401 int rc;1402 u32 offset = 0;1403 u16 ppid = (sid << 8) | (addr >> 8);1404 1405 rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid);1406 if (rc < 0)1407 return rc;1408 1409 apid = rc;1410 switch (ch_type) {1411 case PMIC_ARB_CHANNEL_OBS:1412 offset = 0x8000 * pmic_arb->ee + 0x20 * apid;1413 break;1414 case PMIC_ARB_CHANNEL_RW:1415 if (bus->apid_data[apid].write_ee != pmic_arb->ee) {1416 dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",1417 sid, addr);1418 return -EPERM;1419 }1420 offset = 0x1000 * apid;1421 break;1422 }1423 1424 return offset;1425}1426 1427static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)1428{1429 return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);1430}1431 1432static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)1433{1434 return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);1435}1436 1437static void __iomem *1438pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb_bus *bus, u8 m, u16 n)1439{1440 return bus->intr + 0x20 * m + 0x4 * n;1441}1442 1443static void __iomem *1444pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb_bus *bus, u8 m, u16 n)1445{1446 return bus->intr + 0x100000 + 0x1000 * m + 0x4 * n;1447}1448 1449static void __iomem *1450pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb_bus *bus, u8 m, u16 n)1451{1452 return bus->intr + 0x200000 + 0x1000 * m + 0x4 * n;1453}1454 1455static void __iomem *1456pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb_bus *bus, u8 m, u16 n)1457{1458 return bus->intr + 0x10000 * m + 0x4 * n;1459}1460 1461static void __iomem *1462pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb_bus *bus, u8 m, u16 n)1463{1464 return bus->intr + 0x1000 * m + 0x4 * n;1465}1466 1467static void __iomem *1468pmic_arb_acc_enable_v1(struct spmi_pmic_arb_bus *bus, u16 n)1469{1470 return bus->intr + 0x200 + 0x4 * n;1471}1472 1473static void __iomem *1474pmic_arb_acc_enable_v2(struct spmi_pmic_arb_bus *bus, u16 n)1475{1476 return bus->intr + 0x1000 * n;1477}1478 1479static void __iomem *1480pmic_arb_acc_enable_v5(struct spmi_pmic_arb_bus *bus, u16 n)1481{1482 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1483 return pmic_arb->wr_base + 0x100 + 0x10000 * n;1484}1485 1486static void __iomem *1487pmic_arb_acc_enable_v7(struct spmi_pmic_arb_bus *bus, u16 n)1488{1489 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1490 return pmic_arb->wr_base + 0x100 + 0x1000 * n;1491}1492 1493static void __iomem *1494pmic_arb_irq_status_v1(struct spmi_pmic_arb_bus *bus, u16 n)1495{1496 return bus->intr + 0x600 + 0x4 * n;1497}1498 1499static void __iomem *1500pmic_arb_irq_status_v2(struct spmi_pmic_arb_bus *bus, u16 n)1501{1502 return bus->intr + 0x4 + 0x1000 * n;1503}1504 1505static void __iomem *1506pmic_arb_irq_status_v5(struct spmi_pmic_arb_bus *bus, u16 n)1507{1508 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1509 return pmic_arb->wr_base + 0x104 + 0x10000 * n;1510}1511 1512static void __iomem *1513pmic_arb_irq_status_v7(struct spmi_pmic_arb_bus *bus, u16 n)1514{1515 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1516 return pmic_arb->wr_base + 0x104 + 0x1000 * n;1517}1518 1519static void __iomem *1520pmic_arb_irq_clear_v1(struct spmi_pmic_arb_bus *bus, u16 n)1521{1522 return bus->intr + 0xA00 + 0x4 * n;1523}1524 1525static void __iomem *1526pmic_arb_irq_clear_v2(struct spmi_pmic_arb_bus *bus, u16 n)1527{1528 return bus->intr + 0x8 + 0x1000 * n;1529}1530 1531static void __iomem *1532pmic_arb_irq_clear_v5(struct spmi_pmic_arb_bus *bus, u16 n)1533{1534 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1535 return pmic_arb->wr_base + 0x108 + 0x10000 * n;1536}1537 1538static void __iomem *1539pmic_arb_irq_clear_v7(struct spmi_pmic_arb_bus *bus, u16 n)1540{1541 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb;1542 return pmic_arb->wr_base + 0x108 + 0x1000 * n;1543}1544 1545static u32 pmic_arb_apid_map_offset_v2(u16 n)1546{1547 return 0x800 + 0x4 * n;1548}1549 1550static u32 pmic_arb_apid_map_offset_v5(u16 n)1551{1552 return 0x900 + 0x4 * n;1553}1554 1555static u32 pmic_arb_apid_map_offset_v7(u16 n)1556{1557 return 0x2000 + 0x4 * n;1558}1559 1560static void __iomem *1561pmic_arb_apid_owner_v2(struct spmi_pmic_arb_bus *bus, u16 n)1562{1563 return bus->cnfg + 0x700 + 0x4 * n;1564}1565 1566/*1567 * For arbiter version 7, APID ownership table registers have independent1568 * numbering space for each SPMI bus instance, so each is indexed starting from1569 * 0.1570 */1571static void __iomem *1572pmic_arb_apid_owner_v7(struct spmi_pmic_arb_bus *bus, u16 n)1573{1574 return bus->cnfg + 0x4 * (n - bus->base_apid);1575}1576 1577static const struct pmic_arb_ver_ops pmic_arb_v1 = {1578 .ver_str = "v1",1579 .get_core_resources = pmic_arb_get_core_resources_v1,1580 .init_apid = pmic_arb_init_apid_v1,1581 .ppid_to_apid = pmic_arb_ppid_to_apid_v1,1582 .non_data_cmd = pmic_arb_non_data_cmd_v1,1583 .offset = pmic_arb_offset_v1,1584 .fmt_cmd = pmic_arb_fmt_cmd_v1,1585 .owner_acc_status = pmic_arb_owner_acc_status_v1,1586 .acc_enable = pmic_arb_acc_enable_v1,1587 .irq_status = pmic_arb_irq_status_v1,1588 .irq_clear = pmic_arb_irq_clear_v1,1589 .apid_map_offset = pmic_arb_apid_map_offset_v2,1590 .apid_owner = pmic_arb_apid_owner_v2,1591};1592 1593static const struct pmic_arb_ver_ops pmic_arb_v2 = {1594 .ver_str = "v2",1595 .get_core_resources = pmic_arb_get_core_resources_v2,1596 .init_apid = pmic_arb_init_apid_v1,1597 .ppid_to_apid = pmic_arb_ppid_to_apid_v2,1598 .non_data_cmd = pmic_arb_non_data_cmd_v2,1599 .offset = pmic_arb_offset_v2,1600 .fmt_cmd = pmic_arb_fmt_cmd_v2,1601 .owner_acc_status = pmic_arb_owner_acc_status_v2,1602 .acc_enable = pmic_arb_acc_enable_v2,1603 .irq_status = pmic_arb_irq_status_v2,1604 .irq_clear = pmic_arb_irq_clear_v2,1605 .apid_map_offset = pmic_arb_apid_map_offset_v2,1606 .apid_owner = pmic_arb_apid_owner_v2,1607};1608 1609static const struct pmic_arb_ver_ops pmic_arb_v3 = {1610 .ver_str = "v3",1611 .get_core_resources = pmic_arb_get_core_resources_v2,1612 .init_apid = pmic_arb_init_apid_v1,1613 .ppid_to_apid = pmic_arb_ppid_to_apid_v2,1614 .non_data_cmd = pmic_arb_non_data_cmd_v2,1615 .offset = pmic_arb_offset_v2,1616 .fmt_cmd = pmic_arb_fmt_cmd_v2,1617 .owner_acc_status = pmic_arb_owner_acc_status_v3,1618 .acc_enable = pmic_arb_acc_enable_v2,1619 .irq_status = pmic_arb_irq_status_v2,1620 .irq_clear = pmic_arb_irq_clear_v2,1621 .apid_map_offset = pmic_arb_apid_map_offset_v2,1622 .apid_owner = pmic_arb_apid_owner_v2,1623};1624 1625static const struct pmic_arb_ver_ops pmic_arb_v5 = {1626 .ver_str = "v5",1627 .get_core_resources = pmic_arb_get_core_resources_v2,1628 .init_apid = pmic_arb_init_apid_v5,1629 .ppid_to_apid = pmic_arb_ppid_to_apid_v5,1630 .non_data_cmd = pmic_arb_non_data_cmd_v2,1631 .offset = pmic_arb_offset_v5,1632 .fmt_cmd = pmic_arb_fmt_cmd_v2,1633 .owner_acc_status = pmic_arb_owner_acc_status_v5,1634 .acc_enable = pmic_arb_acc_enable_v5,1635 .irq_status = pmic_arb_irq_status_v5,1636 .irq_clear = pmic_arb_irq_clear_v5,1637 .apid_map_offset = pmic_arb_apid_map_offset_v5,1638 .apid_owner = pmic_arb_apid_owner_v2,1639};1640 1641static const struct pmic_arb_ver_ops pmic_arb_v7 = {1642 .ver_str = "v7",1643 .get_core_resources = pmic_arb_get_core_resources_v7,1644 .init_apid = pmic_arb_init_apid_v7,1645 .ppid_to_apid = pmic_arb_ppid_to_apid_v5,1646 .non_data_cmd = pmic_arb_non_data_cmd_v2,1647 .offset = pmic_arb_offset_v7,1648 .fmt_cmd = pmic_arb_fmt_cmd_v2,1649 .owner_acc_status = pmic_arb_owner_acc_status_v7,1650 .acc_enable = pmic_arb_acc_enable_v7,1651 .irq_status = pmic_arb_irq_status_v7,1652 .irq_clear = pmic_arb_irq_clear_v7,1653 .apid_map_offset = pmic_arb_apid_map_offset_v7,1654 .apid_owner = pmic_arb_apid_owner_v7,1655};1656 1657static const struct irq_domain_ops pmic_arb_irq_domain_ops = {1658 .activate = qpnpint_irq_domain_activate,1659 .alloc = qpnpint_irq_domain_alloc,1660 .free = irq_domain_free_irqs_common,1661 .translate = qpnpint_irq_domain_translate,1662};1663 1664static int spmi_pmic_arb_bus_init(struct platform_device *pdev,1665 struct device_node *node,1666 struct spmi_pmic_arb *pmic_arb)1667{1668 int bus_index = pmic_arb->buses_available;1669 struct spmi_pmic_arb_bus *bus;1670 struct device *dev = &pdev->dev;1671 struct spmi_controller *ctrl;1672 void __iomem *intr;1673 void __iomem *cnfg;1674 int index, ret;1675 int irq;1676 1677 ctrl = devm_spmi_controller_alloc(dev, sizeof(*bus));1678 if (IS_ERR(ctrl))1679 return PTR_ERR(ctrl);1680 1681 ctrl->cmd = pmic_arb_cmd;1682 ctrl->read_cmd = pmic_arb_read_cmd;1683 ctrl->write_cmd = pmic_arb_write_cmd;1684 1685 bus = spmi_controller_get_drvdata(ctrl);1686 1687 pmic_arb->buses[bus_index] = bus;1688 1689 raw_spin_lock_init(&bus->lock);1690 1691 bus->ppid_to_apid = devm_kcalloc(dev, PMIC_ARB_MAX_PPID,1692 sizeof(*bus->ppid_to_apid),1693 GFP_KERNEL);1694 if (!bus->ppid_to_apid)1695 return -ENOMEM;1696 1697 bus->apid_data = devm_kcalloc(dev, pmic_arb->max_periphs,1698 sizeof(*bus->apid_data),1699 GFP_KERNEL);1700 if (!bus->apid_data)1701 return -ENOMEM;1702 1703 index = of_property_match_string(node, "reg-names", "cnfg");1704 if (index < 0) {1705 dev_err(dev, "cnfg reg region missing\n");1706 return -EINVAL;1707 }1708 1709 cnfg = devm_of_iomap(dev, node, index, NULL);1710 if (IS_ERR(cnfg))1711 return PTR_ERR(cnfg);1712 1713 index = of_property_match_string(node, "reg-names", "intr");1714 if (index < 0) {1715 dev_err(dev, "intr reg region missing\n");1716 return -EINVAL;1717 }1718 1719 intr = devm_of_iomap(dev, node, index, NULL);1720 if (IS_ERR(intr))1721 return PTR_ERR(intr);1722 1723 irq = of_irq_get_byname(node, "periph_irq");1724 if (irq <= 0)1725 return irq ?: -ENXIO;1726 1727 bus->pmic_arb = pmic_arb;1728 bus->intr = intr;1729 bus->cnfg = cnfg;1730 bus->irq = irq;1731 bus->spmic = ctrl;1732 bus->id = bus_index;1733 1734 ret = pmic_arb->ver_ops->init_apid(bus, bus_index);1735 if (ret)1736 return ret;1737 1738 dev_dbg(&pdev->dev, "adding irq domain for bus %d\n", bus_index);1739 1740 bus->domain = irq_domain_add_tree(node, &pmic_arb_irq_domain_ops, bus);1741 if (!bus->domain) {1742 dev_err(&pdev->dev, "unable to create irq_domain\n");1743 return -ENOMEM;1744 }1745 1746 irq_set_chained_handler_and_data(bus->irq,1747 pmic_arb_chained_irq, bus);1748 1749 ctrl->dev.of_node = node;1750 dev_set_name(&ctrl->dev, "spmi-%d", bus_index);1751 1752 ret = devm_spmi_controller_add(dev, ctrl);1753 if (ret)1754 return ret;1755 1756 pmic_arb->buses_available++;1757 1758 return 0;1759}1760 1761static int spmi_pmic_arb_register_buses(struct spmi_pmic_arb *pmic_arb,1762 struct platform_device *pdev)1763{1764 struct device *dev = &pdev->dev;1765 struct device_node *node = dev->of_node;1766 struct device_node *child;1767 int ret;1768 1769 /* legacy mode doesn't provide child node for the bus */1770 if (of_device_is_compatible(node, "qcom,spmi-pmic-arb"))1771 return spmi_pmic_arb_bus_init(pdev, node, pmic_arb);1772 1773 for_each_available_child_of_node(node, child) {1774 if (of_node_name_eq(child, "spmi")) {1775 ret = spmi_pmic_arb_bus_init(pdev, child, pmic_arb);1776 if (ret)1777 return ret;1778 }1779 }1780 1781 return ret;1782}1783 1784static void spmi_pmic_arb_deregister_buses(struct spmi_pmic_arb *pmic_arb)1785{1786 int i;1787 1788 for (i = 0; i < pmic_arb->buses_available; i++) {1789 struct spmi_pmic_arb_bus *bus = pmic_arb->buses[i];1790 1791 irq_set_chained_handler_and_data(bus->irq,1792 NULL, NULL);1793 irq_domain_remove(bus->domain);1794 }1795}1796 1797static int spmi_pmic_arb_probe(struct platform_device *pdev)1798{1799 struct spmi_pmic_arb *pmic_arb;1800 struct device *dev = &pdev->dev;1801 struct resource *res;1802 void __iomem *core;1803 u32 channel, ee, hw_ver;1804 int err;1805 1806 pmic_arb = devm_kzalloc(dev, sizeof(*pmic_arb), GFP_KERNEL);1807 if (!pmic_arb)1808 return -ENOMEM;1809 1810 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");1811 core = devm_ioremap(dev, res->start, resource_size(res));1812 if (!core)1813 return -ENOMEM;1814 1815 pmic_arb->core_size = resource_size(res);1816 1817 platform_set_drvdata(pdev, pmic_arb);1818 1819 hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);1820 1821 if (hw_ver < PMIC_ARB_VERSION_V2_MIN)1822 pmic_arb->ver_ops = &pmic_arb_v1;1823 else if (hw_ver < PMIC_ARB_VERSION_V3_MIN)1824 pmic_arb->ver_ops = &pmic_arb_v2;1825 else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)1826 pmic_arb->ver_ops = &pmic_arb_v3;1827 else if (hw_ver < PMIC_ARB_VERSION_V7_MIN)1828 pmic_arb->ver_ops = &pmic_arb_v5;1829 else1830 pmic_arb->ver_ops = &pmic_arb_v7;1831 1832 err = pmic_arb->ver_ops->get_core_resources(pdev, core);1833 if (err)1834 return err;1835 1836 dev_info(dev, "PMIC arbiter version %s (0x%x)\n",1837 pmic_arb->ver_ops->ver_str, hw_ver);1838 1839 err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);1840 if (err) {1841 dev_err(&pdev->dev, "channel unspecified.\n");1842 return err;1843 }1844 1845 if (channel > 5) {1846 dev_err(&pdev->dev, "invalid channel (%u) specified.\n",1847 channel);1848 return -EINVAL;1849 }1850 1851 pmic_arb->channel = channel;1852 1853 err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);1854 if (err) {1855 dev_err(&pdev->dev, "EE unspecified.\n");1856 return err;1857 }1858 1859 if (ee > 5) {1860 dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);1861 return -EINVAL;1862 }1863 1864 pmic_arb->ee = ee;1865 1866 return spmi_pmic_arb_register_buses(pmic_arb, pdev);1867}1868 1869static void spmi_pmic_arb_remove(struct platform_device *pdev)1870{1871 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev);1872 1873 spmi_pmic_arb_deregister_buses(pmic_arb);1874}1875 1876static const struct of_device_id spmi_pmic_arb_match_table[] = {1877 { .compatible = "qcom,spmi-pmic-arb", },1878 { .compatible = "qcom,x1e80100-spmi-pmic-arb", },1879 {},1880};1881MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);1882 1883static struct platform_driver spmi_pmic_arb_driver = {1884 .probe = spmi_pmic_arb_probe,1885 .remove_new = spmi_pmic_arb_remove,1886 .driver = {1887 .name = "spmi_pmic_arb",1888 .of_match_table = spmi_pmic_arb_match_table,1889 },1890};1891module_platform_driver(spmi_pmic_arb_driver);1892 1893MODULE_DESCRIPTION("Qualcomm MSM SPMI Controller (PMIC Arbiter) driver");1894MODULE_LICENSE("GPL v2");1895MODULE_ALIAS("platform:spmi_pmic_arb");1896