290 lines · c
1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Driver for Realtek PCI-Express card reader4 *5 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.6 *7 * Author:8 * Wei WANG (wei_wang@realsil.com.cn)9 * Micky Ching (micky_ching@realsil.com.cn)10 */11 12#ifndef __REALTEK_RTSX_SD_H13#define __REALTEK_RTSX_SD_H14 15#include "rtsx_chip.h"16 17#define SUPPORT_VOLTAGE 0x003C000018 19/* Error Code */20#define SD_NO_ERROR 0x021#define SD_CRC_ERR 0x8022#define SD_TO_ERR 0x4023#define SD_NO_CARD 0x2024#define SD_BUSY 0x1025#define SD_STS_ERR 0x0826#define SD_RSP_TIMEOUT 0x0427#define SD_IO_ERR 0x0228 29/* Return code for MMC switch bus */30#define SWITCH_SUCCESS 031#define SWITCH_ERR 132#define SWITCH_FAIL 233 34/* MMC/SD Command Index */35/* Basic command (class 0) */36#define GO_IDLE_STATE 037#define SEND_OP_COND 138#define ALL_SEND_CID 239#define SET_RELATIVE_ADDR 340#define SEND_RELATIVE_ADDR 341#define SET_DSR 442#define IO_SEND_OP_COND 543#define SWITCH 644#define SELECT_CARD 745#define DESELECT_CARD 746/* CMD8 is "SEND_EXT_CSD" for MMC4.x Spec47 * while is "SEND_IF_COND" for SD 2.048 */49#define SEND_EXT_CSD 850#define SEND_IF_COND 851 52#define SEND_CSD 953#define SEND_CID 1054#define VOLTAGE_SWITCH 1155#define READ_DAT_UTIL_STOP 1156#define STOP_TRANSMISSION 1257#define SEND_STATUS 1358#define GO_INACTIVE_STATE 1559 60#define SET_BLOCKLEN 1661#define READ_SINGLE_BLOCK 1762#define READ_MULTIPLE_BLOCK 1863#define SEND_TUNING_PATTERN 1964 65#define BUSTEST_R 1466#define BUSTEST_W 1967 68#define WRITE_BLOCK 2469#define WRITE_MULTIPLE_BLOCK 2570#define PROGRAM_CSD 2771 72#define ERASE_WR_BLK_START 3273#define ERASE_WR_BLK_END 3374#define ERASE_CMD 3875 76#define LOCK_UNLOCK 4277#define IO_RW_DIRECT 5278 79#define APP_CMD 5580#define GEN_CMD 5681 82#define SET_BUS_WIDTH 683#define SD_STATUS 1384#define SEND_NUM_WR_BLOCKS 2285#define SET_WR_BLK_ERASE_COUNT 2386#define SD_APP_OP_COND 4187#define SET_CLR_CARD_DETECT 4288#define SEND_SCR 5189 90#define SD_READ_COMPLETE 0x0091#define SD_READ_TO 0x0192#define SD_READ_ADVENCE 0x0293 94#define SD_CHECK_MODE 0x0095#define SD_SWITCH_MODE 0x8096#define SD_FUNC_GROUP_1 0x0197#define SD_FUNC_GROUP_2 0x0298#define SD_FUNC_GROUP_3 0x0399#define SD_FUNC_GROUP_4 0x04100#define SD_CHECK_SPEC_V1_1 0xFF101 102#define NO_ARGUMENT 0x00103#define CHECK_PATTERN 0x000000AA104#define VOLTAGE_SUPPLY_RANGE 0x00000100105#define SUPPORT_HIGH_AND_EXTENDED_CAPACITY 0x40000000106#define SUPPORT_MAX_POWER_PERMANCE 0x10000000107#define SUPPORT_1V8 0x01000000108 109#define SWITCH_NO_ERR 0x00110#define CARD_NOT_EXIST 0x01111#define SPEC_NOT_SUPPORT 0x02112#define CHECK_MODE_ERR 0x03113#define CHECK_NOT_READY 0x04114#define SWITCH_CRC_ERR 0x05115#define SWITCH_MODE_ERR 0x06116#define SWITCH_PASS 0x07117 118#ifdef SUPPORT_SD_LOCK119#define SD_ERASE 0x08120#define SD_LOCK 0x04121#define SD_UNLOCK 0x00122#define SD_CLR_PWD 0x02123#define SD_SET_PWD 0x01124 125#define SD_PWD_LEN 0x10126 127#define SD_LOCKED 0x80128#define SD_LOCK_1BIT_MODE 0x40129#define SD_PWD_EXIST 0x20130#define SD_UNLOCK_POW_ON 0x01131#define SD_SDR_RST 0x02132 133#define SD_NOT_ERASE 0x00134#define SD_UNDER_ERASING 0x01135#define SD_COMPLETE_ERASE 0x02136 137#define SD_RW_FORBIDDEN 0x0F138 139#endif140 141#define HS_SUPPORT 0x01142#define SDR50_SUPPORT 0x02143#define SDR104_SUPPORT 0x03144#define DDR50_SUPPORT 0x04145 146#define HS_SUPPORT_MASK 0x02147#define SDR50_SUPPORT_MASK 0x04148#define SDR104_SUPPORT_MASK 0x08149#define DDR50_SUPPORT_MASK 0x10150 151#define HS_QUERY_SWITCH_OK 0x01152#define SDR50_QUERY_SWITCH_OK 0x02153#define SDR104_QUERY_SWITCH_OK 0x03154#define DDR50_QUERY_SWITCH_OK 0x04155 156#define HS_SWITCH_BUSY 0x02157#define SDR50_SWITCH_BUSY 0x04158#define SDR104_SWITCH_BUSY 0x08159#define DDR50_SWITCH_BUSY 0x10160 161#define FUNCTION_GROUP1_SUPPORT_OFFSET 0x0D162#define FUNCTION_GROUP1_QUERY_SWITCH_OFFSET 0x10163#define FUNCTION_GROUP1_CHECK_BUSY_OFFSET 0x1D164 165#define DRIVING_TYPE_A 0x01166#define DRIVING_TYPE_B 0x00167#define DRIVING_TYPE_C 0x02168#define DRIVING_TYPE_D 0x03169 170#define DRIVING_TYPE_A_MASK 0x02171#define DRIVING_TYPE_B_MASK 0x01172#define DRIVING_TYPE_C_MASK 0x04173#define DRIVING_TYPE_D_MASK 0x08174 175#define TYPE_A_QUERY_SWITCH_OK 0x01176#define TYPE_B_QUERY_SWITCH_OK 0x00177#define TYPE_C_QUERY_SWITCH_OK 0x02178#define TYPE_D_QUERY_SWITCH_OK 0x03179 180#define TYPE_A_SWITCH_BUSY 0x02181#define TYPE_B_SWITCH_BUSY 0x01182#define TYPE_C_SWITCH_BUSY 0x04183#define TYPE_D_SWITCH_BUSY 0x08184 185#define FUNCTION_GROUP3_SUPPORT_OFFSET 0x09186#define FUNCTION_GROUP3_QUERY_SWITCH_OFFSET 0x0F187#define FUNCTION_GROUP3_CHECK_BUSY_OFFSET 0x19188 189#define CURRENT_LIMIT_200 0x00190#define CURRENT_LIMIT_400 0x01191#define CURRENT_LIMIT_600 0x02192#define CURRENT_LIMIT_800 0x03193 194#define CURRENT_LIMIT_200_MASK 0x01195#define CURRENT_LIMIT_400_MASK 0x02196#define CURRENT_LIMIT_600_MASK 0x04197#define CURRENT_LIMIT_800_MASK 0x08198 199#define CURRENT_LIMIT_200_QUERY_SWITCH_OK 0x00200#define CURRENT_LIMIT_400_QUERY_SWITCH_OK 0x01201#define CURRENT_LIMIT_600_QUERY_SWITCH_OK 0x02202#define CURRENT_LIMIT_800_QUERY_SWITCH_OK 0x03203 204#define CURRENT_LIMIT_200_SWITCH_BUSY 0x01205#define CURRENT_LIMIT_400_SWITCH_BUSY 0x02206#define CURRENT_LIMIT_600_SWITCH_BUSY 0x04207#define CURRENT_LIMIT_800_SWITCH_BUSY 0x08208 209#define FUNCTION_GROUP4_SUPPORT_OFFSET 0x07210#define FUNCTION_GROUP4_QUERY_SWITCH_OFFSET 0x0F211#define FUNCTION_GROUP4_CHECK_BUSY_OFFSET 0x17212 213#define DATA_STRUCTURE_VER_OFFSET 0x11214 215#define MAX_PHASE 31216 217#define MMC_8BIT_BUS 0x0010218#define MMC_4BIT_BUS 0x0020219 220#define MMC_SWITCH_ERR 0x80221 222#define SD_IO_3V3 0223#define SD_IO_1V8 1224 225#define TUNE_TX 0x00226#define TUNE_RX 0x01227 228#define CHANGE_TX 0x00229#define CHANGE_RX 0x01230 231#define DCM_HIGH_FREQUENCY_MODE 0x00232#define DCM_LOW_FREQUENCY_MODE 0x01233 234#define DCM_HIGH_FREQUENCY_MODE_SET 0x0C235#define DCM_LOW_FREQUENCY_MODE_SET 0x00236 237#define MULTIPLY_BY_1 0x00238#define MULTIPLY_BY_2 0x01239#define MULTIPLY_BY_3 0x02240#define MULTIPLY_BY_4 0x03241#define MULTIPLY_BY_5 0x04242#define MULTIPLY_BY_6 0x05243#define MULTIPLY_BY_7 0x06244#define MULTIPLY_BY_8 0x07245#define MULTIPLY_BY_9 0x08246#define MULTIPLY_BY_10 0x09247 248#define DIVIDE_BY_2 0x01249#define DIVIDE_BY_3 0x02250#define DIVIDE_BY_4 0x03251#define DIVIDE_BY_5 0x04252#define DIVIDE_BY_6 0x05253#define DIVIDE_BY_7 0x06254#define DIVIDE_BY_8 0x07255#define DIVIDE_BY_9 0x08256#define DIVIDE_BY_10 0x09257 258struct timing_phase_path {259 int start;260 int end;261 int mid;262 int len;263};264 265int sd_select_card(struct rtsx_chip *chip, int select);266int sd_pull_ctl_enable(struct rtsx_chip *chip);267int reset_sd_card(struct rtsx_chip *chip);268int sd_switch_clock(struct rtsx_chip *chip);269void sd_stop_seq_mode(struct rtsx_chip *chip);270int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,271 u32 start_sector, u16 sector_cnt);272void sd_cleanup_work(struct rtsx_chip *chip);273int sd_power_off_card3v3(struct rtsx_chip *chip);274int release_sd_card(struct rtsx_chip *chip);275#ifdef SUPPORT_CPRM276int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,277 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len,278 bool special_check);279int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type);280 281int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip);282int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip);283int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip);284int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip);285int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip);286int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip);287#endif288 289#endif /* __REALTEK_RTSX_SD_H */290